8085 - Study Material PDF
8085 - Study Material PDF
8085 - Study Material PDF
Architecture
using intel 8085 as a classic processor.
By:
Mayank Dev
Astt.. Prof. ET Deptt.
Astt Deptt.
(Advance microprocessros TEC- 504,
Prepared by: Mayank Dev) 1
Intel 8085 (Source:
Source: Intel Corp)
(Advance microprocessros TEC- 504,
Prepared by: Mayank Dev) 3
Fig-2:8085 Signals and I/O Pins
(Source:
Source: Intel Corp )
(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 4 4
Fig: Architecture-
Architecture-8085A
Source: Intel Corp (Advance microprocessros TEC- 504,
Prepared by: Mayank Dev) 5 5
The 8085 and Its Buses
The 8085 is an 8-bit general purpose microprocessor that
can address 64K Byte of memory.
It has 40 pins and uses +5V for power. It can run at a
maximum frequency of 3 MHz.
◦ The pins on the chip can be grouped into 6 groups:
Address Bus.
Data Bus.
Control and Status Signals.
Power supply and frequency.
Externally Initiated Signals.
Serial I/O ports.
(Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 6
The Address and Data Bus Systems
The address bus has 8 signal lines A8 – A15 which are
unidirectional.
The other 8 address bits are multiplexed (time shared)
with the 8 data bits.
◦ So, the bits AD0 – AD7 are bi-directional and serve as
A0 – A7 and D0 – D7 at the same time.
During the execution of the instruction, these lines
carry the address bits during the early part, then
during the late parts of the execution, they carry the
8 data bits.
◦ In order to separate the address from the data, we can
use a latch to save the value before the function of the
bits changes. (Advance microprocessros TEC- 504, Prepared by: Mayank Dev) 7
ALE used to demultiplex address/data bus
(Advance microprocessros
8 TEC- 504, Prepared by: Mayank Dev)
The Control and Status Signals
There are 4 main control and status signals.These are:
ALE: Address Latch Enable. This signal is a pulse that
become 1 when the AD0 – AD7 lines have an address
on them. It becomes 0 after that. This signal can be
used to enable a latch to save the address bits from
the AD lines.
RD: Read.Active low.
WR:Write.Active low.
IO/M: This signal specifies whether the operation is a
memory operation (IO/M=0) or an I/O operation
(IO/M=1).
S1 and S0 : Status signals to specify the kind of
operation being performed. Usually not used in small
systems. (Advance microprocessros TEC- 504,
Prepared by: Mayank Dev) 9
Frequency Control Signals
There are 3 important pins in the frequency control
group.
◦ X0 and X1 are the inputs from the crystal or clock
generating circuit.
The frequency is internally divided by 2.
So, to run the microprocessor at 3 MHz, a clock
running at 6 MHz should be connected to the X0
and X1 pins.
Accumulator (8-bit)
Flag Register (8-bit)
Register(s)
B(8-bit),C(8-bit),
D(8-bit),E(8-bit),
H(8-bit),L(8-bit)
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR
Data Lines
ROM
RAM
Input Buffer WR
Address CS
Lines
Address CS
Lines
Output Buffer RD
Output Buffer RD
Date
Lines
Data Lines
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR
When INTR is
asserted, 8085
response with
INTA pulse.
During INTA
pulse, 8085
expect to see
an instruction
applied to its
data bus.
Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A .
(Advance microprocessros
39 TEC- 504, Prepared by: Mayank Dev)
MPU Communication and Bus Timing
Initialize
Body of loop
Update the
count
No Is this
Final
Count
?
Yes
MVI C, 15H
LOOP: DCR C
JNZ LOOP
• TO = 7 T-States
– Delay of the MVI instruction
• TO = 10 T-States
– The delay for the LXI instruction
loop. N
o
Is this
Final
– In the figure, the body Count
?
of loop2 can be before Ye
s
or after loop1.
• Total Delay
– TDelay = 57412 X 0.5 Sec = 28.706 mSec
Instruction Cycle: The time taken by the processor to complete the execution of an instruction. An
instruction cycle consists of one to six machine cycles.
Machine Cycle: The time required to complete one operation; accessing either the memory or I/O
device. A machine cycle consists of three to six T-states.
T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of
instructions or programs in a processor.
It is the first step in the execution of any instruction. The timing diagram of this cycle is given in
next Figure. The following points explain the various operations that take place and the signals
that are changed during the execution of opcode fetch machine cycle:
T1 clock cycle
i.The content of PC is placed in the address bus; AD0 - AD7 lines contains lower bit address and A8
– A15 contains higher bitaddress.
ii.IO/Msignal is low indicating that a memory location is being accessed. S1 and S0 also changed
to the levels as indicated in Table 1.
iii. ALE is high, indicates that multiplexed AD0 – AD7 act as lower order bus.
T2 clock cycle
ii.The RD signal is made low by the processor. This signal makes the memory device load the data
bus with the contents of the location addressed by the processor.
T4 clock cycle
The memory read cycle is executed by the processor to read a data byte from memory.
The machine cycle is exactly same to opcode fetch except: a) It has three T-states b) The
S0 signal is set to 0. The timing diagram of this cycle is given in the following Figure.
The memory write cycle is executed by the processor to write a data byte in a memory
location. The processor takes three T-states and WR signal is made low. The timing diagram
of this cycle is given in the following Figure.
A processor have to execute the program. A program is just a set of instructions written in a sequence. Multiple machine cycles are
required to execute an instruction. The processor fetches an instruction from memory, Decodes it and then executes it. This fetching,
decoding and executing an instruction makes an instructiion cycle. Basically we have an equation for instruction cycle....
IC = FC + EC
where IC is instruction cycle, FC is fetch cycle and EC is the execution cycle. Every instruction will have a fetch machine cycle. Mainly
a processor have three machine cycles: (i) Fetch, (ii) Read, (iii) Write.
Fetch Machine cycle: Fetch machine cycle is made up of two parts, First read an instruction from memory, Second Decode the
instruction code. It requires 4 t-states in case of Intel 8085 MP.
Some of the instruction that dont require any memory or I/O operation will be over in the same machine cycle, others may require
some read or write machine cycles.
Read Machine cycle: This requires 3 T-states. In this microprocessor will read the contents of memory or I/O device.
Write Machine Cycle: In this the microprocessor will write the contents on memory or I/O devce. It again requires 3 T-States.
Corresponding
Coding: A000h 78
OFC
8085 Memory
RD
OFC WR
IO/M
8085 Memory
Op-code fetch
Cycle
A0h A0h
A15- A8 (Higher OrderAddress bus)
00h 3Eh 01h 45h
DA7-DA0 (Lower order address/data
Instruction: Bus)
A000h 3E
A001h 45 WR
IO/M
A000h 21 MEMR
MEMR
A001h 45
A002h F0 808 Memor
5 y
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
ALE
RD
WR
IO/M
Corresponding MEMR
Coding: A000h 7E
808 Memor
5 y
WR
IO/M
Instruction:
A000h MOV M,A
Corresponding Coding: A000h 77
Corresponding MEMW
Coding: A000h 77
8085 Memory
WR
IO/M