IR Camera Validation of IGBT Junction Temperature

Measurement via Peak Gate Current

Nick Baker, Laurent Dupont, Stig Munk-Nielsen, Francesco Iannuzzo, Marco
Liserre

To cite this version:

Nick Baker, Laurent Dupont, Stig Munk-Nielsen, Francesco Iannuzzo, Marco Liserre. IR Camera
Validation of IGBT Junction Temperature Measurement via Peak Gate Current. IEEE Transactions
on Power Electronics, 2017, 32 (4), pp.3099 - 3111. <10.1109/TPEL.2016.2573761>. <hal-01704618>

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https://hal.archives-ouvertes.fr/hal-01704618
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IEEE Transactions on Power Electronics 1

IR Camera Validation of IGBT Junction

Temperature Measurement via Peak Gate
Current
Nick Baker, Laurent Dupont, Stig Munk-Nielsen, Francesco Iannuzzo and Marco Liserre

 the on-state voltage drop or threshold voltage, junction

Abstract—Infra-red measurements are used to assess the temperature measurements can be performed on standard
measurement accuracy of the Peak Gate Current (IGPeak) method power modules without modification to their structure [2]-[4].
for IGBT junction temperature measurement. Single IGBT chips Electrical methods for junction temperature measurement
with the gate pad in both the centre and the edge are
have been used for many decades on transistors, particularly
investigated, along with paralleled chips, as well as chips
suffering partial bond-wire lift-off. Results are also compared for offline thermal characterisation of devices. Nevertheless,
with a traditional electrical temperature measurement method: TSEP-based methods face many challenges in online
the voltage drop under low current (VCE(low)). In all cases, the implementation (i.e. during normal transistor operation) [4][5].
IGPeak method is found to provide a temperature slightly Issues regarding online TSEP usage generally involve the
overestimating the temperature of the gate pad. Consequently, need to compensate for operating conditions other than
both the gate pad position and chip temperature distribution
temperature (such as load current), and the need for complex
influence whether the measurement is representative of the mean
junction temperature. These results remain consistent after chips measurement circuitry or alteration to converter structure or
are degraded through bondwire lift-off. In a paralleled IGBT control. Calibration procedures can also present substantial
configuration with non-negligible temperature disequilibrium problems when self-heating compensation is required for
between chips, the IGPeak method delivers a measurement based higher current levels [6][7].
on the average temperature of the gate pads. In the past two years, a significant number of proposals for
online TSEP measurements have been presented [8]-[15]. This
Index Terms—Power semiconductor devices, insulated-gate
bipolar-transistor (IGBT), temperature measurement. paper extends on the work displayed in [11] and [12], by
providing a detailed evaluation on the accuracy of IGBT
I. INTRODUCTION temperature measurement using the Peak Gate Current (I GPeak).
Although this method claims to resolve some of the TSEP
T he junction temperature of a power semiconductor device
is a key parameter that influences both performance and
reliability. Knowledge of this temperature during operation
implementation issues highlighted above, no validation is
currently available regarding whether the measured
temperature suitably represents the junction temperature in an
could improve condition monitoring systems, and allow
operating IGBT.
temperature based control algorithms that enhance module
Validating the accuracy of a TSEP is of fundamental
lifetime [1].
importance if a TSEP is to be considered for real-world use,
Real-time junction temperature measurement is however
since a TSEP may not always provide accurate results. In fact,
often difficult. Physical or contact measurement methods such
inconsistencies between different TSEP measurements have
as optical fibres, on-chip sensors, or infra-red cameras are
been found as far back as 1966 [16]. Since then, there is ample
expensive and require substantial modification to standard
research to back up the assertion that TSEPs can deliver
power module packaging. For these reasons, electrical
widely varying temperature measurements. A notable example
measurement methods are often preferred. Using a
is the VCE at high current, which can give vastly erroneous
Temperature Sensitive Electrical Parameter (TSEP), such as
temperatures due to the series resistance contribution of the
packaging interconnections [7][17]. The discrepancies
Nick Baker, Stig Munk-Nielsen and Francesco Iannuzzo are at the between different TSEPs may also change depending on the
Department of Energy Technology, Aalborg University, Denmark. (emails: device and dissipation conditions [18]-[20]. Nevertheless,
nba@et.aau.dk, smn@et.aau.dk, fia@et.aau.dk). many recent TSEP proposals come with little or no validation
L. Dupont is with the Laboratory of New Technologies, French Institute of
Science and Technology for Transport, Development and Networks, 78000 (perhaps limited to one single chip) of the temperature
Versailles, France (e-mail: laurent.dupont@ifsttar.fr). provided.
Marco Liserre is with the Chair of Power Electronics at Christian- As a result, this paper focuses on evaluating the accuracy of
Albrechts-University of Kiel, Germany. (email: ml@tf.uni-kiel.de).
the IGPeak method for IGBT junction temperature measurement.
First of all, infra-red (IR) measurements are used to validate
the IGPeak method on two identically rated IGBTs with
IEEE Transactions on Power Electronics 2

differing geometry (shape and gate pad position). The IGBTs

are also investigated in a paralleled configuration – both with ⁄
( )
and without large temperature disequilibrium between the
paralleled IGBTs. Finally, since the electrical parameters of a
device are prone to alter throughout its lifetime, a pertinent The peak current can therefore be approximated by using
question is whether the accuracy of a TSEP method is resistant Ohm’s Law, I ≈ V/R; where V is the voltage swing of the gate
to these effects. To begin a preliminary assessment on this driver, and R is the total gate resistance.
question, an IGBT is investigated both before and after several It is possible to monitor IGPeak by measuring the peak value
bondwires are disconnected from the die, which mimics one of of the voltage across the external gate resistor, since this
the most common degradation mechanisms reported in prior voltage is directly proportional to the gate current. A peak
literature. detector circuit is integrated into the gate driver and consists
All results obtained using the IGPeak method are compared to of a differential amplifier, a peak detector, a memory capacitor
measurements made using a conventional TSEP method, the and a reset switch that is controlled by the gate voltage signal,
voltage drop under low current injection (V CE(low)). This TSEP as seen in Fig. 1.
is selected for comparison with IGPeak due to its widespread use Along with the output of the peak detector circuit
and repeated evidence of correlation with mean junction (VPeakdetector), the gate voltage just before turn-on is measured
temperature [7][18][21]. (VGneg), as well as the positive supply from the gate driver
The paper will first provide a short description of the (VGpos). These three values are then used in (3) to calculate a
procedure for junction temperature measurement using both value for RGint.
IGPeak and VCE(low). Details will then be provided on the IGBT
chips studied, and the methodology behind the IR
( )
measurements. The electrical test bench will also be described, ( ⁄ )
which allows thermal measurements to be conducted on
IGBTs operating under constant current injection. The results This paper uses a prototype measurement circuit previously
of each temperature measurement on the variety of IGBT detailed in [11]. High power verification of the measurement
configurations are then presented. in the form of a double pulse test, along with discussion of
several implementation issues can be found in [11]. This paper
II. TSEP MEASUREMENTS however focuses on evaluating the fundamental accuracy of
A. Peak Gate Current - IGPeak the IGPeak method; therefore, implementation issues relating to
real-world use in commercial converters will not be
This measurement method relies on the temperature
extensively discussed.
dependence of the internal gate resistance (RGint), which is
located in the IGBT chip itself. If the peak gate current and
voltage swing of the gate driver are known, these values can
be used to calculate a value for RGint. A detailed explanation of
this method is provided in [11]; however the basic
measurement principle will be outlined in the following
paragraphs.
IGPeak is measured during the normal charging cycle of the
gate terminal during turn-on. The time constant for the
charging of the gate in a MOS-gated device before the
threshold voltage is reached (i.e. during the turn-on delay) can
be written as [22]:
Fig. 1. Peak Detector Schematic to detect peak voltage over the external
( ) ( ) gate resistor [11]

where RG is the gate resistance, CGS is the gate-source B. Forward Voltage under Low Current Injection – VCE(low)
capacitance (gate-emitter in IGBTs), CGD is the gate-drain The VCE(low) has been used for the thermal characterisation
capacitance (gate-collector in IGBTs) and VDS is the drain- of bipolar transistors for many decades [3][16][21][25]. By
source voltage (collector-emitter in IGBTs). taking advantage of the temperature dependence of the voltage
During the turn-on delay, the capacitance CGD remains drop across a PN junction, this parameter generally exhibits a
small and constant due to a high and unchanged value of V DS negative temperature dependence of approximately -2mV/°C
[23][24]. Thus, if the parasitic gate inductance is kept in silicon devices.
negligible, the gate current during the turn-on delay can be The measurement process is very simple: a constant sensing
viewed as a step response of a first order RC circuit where the current generally in the range of 1mA – 100mA is fed into the
initial (and peak) charging current into the gate capacitor can power device, and the subsequent voltage drop is measured.
be calculated as: Typically, the sensing current is injected into the device after a
IEEE Transactions on Power Electronics 3

sufficient delay (up to a few hundred µs) once the load current The IR camera used is a CEDIP-FLIR SC7500. For each
has been removed in order to be sure that excess carriers are measurement, 100 IR frames (100Hz frequency) are acquired
completely swept away or recombined. Since the sense current while the IGBTs conduct a constant current in a thermal
induces negligible self-heating, the voltage drop can be steady-state. To fix identical positioning for each image
recorded as the device is cooling and a linear regression vs. acquisition, the position of the camera was controlled by a 3-
the square root of time used to estimate the temperature value axis positioning system.
at the moment the load current is switched off [3][21]. 13.62mm
Although the VCE(low) has been experimentally validated in
numerous studies and shown to provide a temperature close to
the mean temperature of the chip [7][18][21], it is problematic

13.78mm
to implement in real switching conditions due to requiring a
suitable window to inject the sensing current [26][27].
Nevertheless, its traditional use and repeated evidence of
correlation with mean junction temperature is why the method
is chosen as the current state-of-the-art for comparison with
(a) (b)
the recently proposed IGPeak method.
Fig. 2. IGBT A:
(a) Geometry of Infineon IGC189T120T8RL bare die.
III. TSEP MEASUREMENTS (b) Dies inside FS200R12PT4 module after dielectric gel is
removed.
A. IGBTs under test
15.99mm
Two Infineon IGBTs are chosen for investigation, both
rated at 1200V/200A. Additionally, each IGBT contains an
RGint of 3.5Ω. Although these IGBTs have identical

12.08mm
specifications, the geometry of the chips is dissimilar and is
the primary reason for their selection.
The first IGBT (Die: IGC189T120T8RL [28], Module:
FS200R12PT4) is square in profile with the gate pad in the
centre, while the second IGBT (Die: IGC193T120T8RM [29], (b)
(a)
Module: FF600R12ME4) has a rectangular profile with the
Fig. 3. IGBT B:
gate pad at the side. The geometry and dimensions of the dies (a) Geometry of Infineon IGC193T120T8RM bare die.
are shown in Fig. 2 and Fig. 3. These IGBTs will subsequently (b) Dies inside FF600R12ME4 module after dielectric gel is
be referred to as Type A and Type B respectively. removed.
Because functional dies complete with bondwires and
packaging could not be obtained individually, the experiments
are performed on individual dies isolated from inside
commercial multi-chip power modules. The module layout for
IGBT A (square, gate pad centre) also allowed investigation of
two IGBTs in parallel. In addition, IGBT A is investigated
both with and without bond-wire removal.
Fig. 4. IGBT B before painting (left) and after painting (right).
B. IR Thermal Measurements
C. Test Bench Operation
To prepare the power modules for IR measurements, the
A panoramic view of the test bench, along with a close up
dielectric gel was first removed by soaking for several hours
of the IR camera, power module and gate driver with the IGPeak
in Ardrox 2312 at 75°C. The modules were then cleaned with
measurement circuit is shown in Fig. 5. A schematic of the test
Acetone and deionised water, before being painted with
setup is displayed in Fig. 6, which allowed the TSEPs to be
PYROMARK 1200 high temperature paint. Care was taken
evaluated with IGBTs operating under constant current
during the painting process to achieve as consistent emissivity
injection. The operating principle is described below, with the
as possible across the chip surface: the paint was filtered to
basic premise being a two stage operation: a heating phase and
attain a uniform particle size, and micro-spraying equipment
a measurement phase.
was used that allowed tight control over the paint thickness.
The first step is the heating step, where a high current is fed
Before and after painting photos of IGBT B are shown in Fig.
into the DUT IGBT from the current source I1. This induces
4.
self-heating in the device, which can last for several minutes
The thickness of the paint was selected as a trade-off
until a thermal steady-state is reached. The second step is the
between achieving uniform emissivity, while minimising the
measurement step. At this point, the IGBT temperature is
impact on the thermal behaviour of the IGBTs. The paint
measured using the three presented measurement methods: IR
thickness in all cases is between 10-16µm, compared to the
camera, VCE(low) and IGPeak.
115-120µm thickness of the IGBT dies.
IEEE Transactions on Power Electronics 4

IR Camera and 3-axis HBM Data Recorder

positioning system

Gate Driver
IGBT module

(a) (b)
Fig. 5. (a) Panoramic view of test bench (b) Close up of power module, IR Camera, and gate driver with peak detector measurement circuit [11]

In total, IGPeak is measured 200µs after the heating current is

removed. The negative gate voltage and the positive voltage
supply of the gate driver are sampled 500ns before turn-on,
while the output of the peak detector is recorded 1µs after
turn-on.
Now that the IGPeak measurement is completed, MOS3 is
opened and a 100mA sensing current (I2) is injected into the
DUT IGBT during t3. The VCE(low) is recorded for a period of
250µs, and a linear regression vs. the square root of time is
used to estimate the VCE(low) at the instant the load current is
removed the DUT IGBT [3]. Finally, the original IDUT is
Fig. 6. Test Bench Schematic
returned to the DUT IGBT in t4.
All electrical measurements are performed using a HBM This procedure is repeated 10 times and the mean value of
Gen3i data recorder. To measure IGPeak, the peak detector these measurements is used for analysis. For calibration of
prototype described in [11] is used, and the circuit output VCE(low) and IGPeak, the cooling fluid to the IGBT heatsink is
along with the gate voltage is sampled at 100MS/s (14-bit varied from 40°C to 180°C, and the procedure described
resolution). The VCE of the DUT IGBT is recorded at 2MS/s above is performed with IDUT set to 0A. A type-K open
(16-bit resolution). thermocouple is placed on the copper base of the power
It is clear that both VCE(low) and IGPeak cannot be performed module and used as the reference temperature during the
while conducting the full dissipation current: VCE(low) requires calibration procedure.
a low sensing current of 100mA and IGPeak must be recorded
Test Bench Waveforms
during an IGBT turn-on. Therefore, synchronisation of 120 1.7
MOSFETs MOS1, MOS2, MOS3, and current source I2 are IDUT
100 Vce 1.4
used in order to facilitate these measurements. 80 1.1

VCE (V)
IDUT (A)

The current source I2 is fixed at 100mA and provides the 60 0.8

sensing current to perform a temperature measurement using 40 0.5
VCE(low). MOS1 and MOS2 on the other hand are used to 20 0.2
0 -0.1
control the injection of the high heating current into the IGBT. t0 t1 t2 t3 t4
MOS3 is used to force a zero collector-emitter voltage during 6 20
Peak Detector (V)

Gate Voltage (V)

5 15
measurement of IGPeak. 4 10
The general procedure is as follows and depicted in Fig. 7. 3 5
First of all, t0 depicts the end of the heating phase which may 2 0
1 Peak Detector -5
have been ongoing for several minutes previously, with the 0 Gate Voltage -10
DUT IGBT conducting a high current. In this phase, the -1 -15
temperature evolution of the IGBT is monitored using the IR 0.4 0.50.80.60.9 0.7
1.0 1.1 1.2
Time (ms)
camera. Once a thermal steady-state is reached, 100 IR images
Fig. 7. Synchronisation of Electrical Measurements
are sampled at 100Hz. Following this, t1 commences with IDUT
redirected into MOS1, and the DUT IGBT switched off – a D. Gate Capacitance Stability at VCE = 0V
transition that lasts 100µs in total. In t2, MOS3 is closed to Although the measurement of IGPeak is conducted at a
short the collector and emitter of the DUT IGBT. This fixes constant VCE, previous assumptions have stipulated that a high
the VCE at 0V and is vital to ensure a stable CG for the IGPeak VCE is also required for CG to be stable [11][23]. Since IGPeak is
measurement [11]. The IGBT is turned on again and a measured at a VCE of 0V in these experiments, a short
measurement of IGPeak occurs using the peak detector circuit. validation of the stability of CG in this condition was
IEEE Transactions on Power Electronics 5

conducted. Fig. 8 displays a CGE-VGE profile vs. temperature die, while the minimum is more than 6°C lower. Nonetheless,
on IGBT A with the collector-emitter shorted (i.e. the same the overall mean temperature of both structures is similar, with
conditions for IGPeak measurement in the test bench). the mean temperature of the bondwires just 0.4°C higher than
the die surface.
CG-VGE vs. Temperature at VCE = 0V
90
75
60
CG (nF)

45 25°C
50°C
30 75°C
100°C Chip: IGC189T120T8RL
15 125°C Module: FS200R12PT4
150°C
0
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1
VGE (V)
Fig. 8. CG-VGE vs. temperature profile for IGBT A (Infineon FS200R12PT4)
(a)
The profile shows that CGE is around 80nF and stable with
temperature while VGE remains below approximately -1V.
Given that the Concept2 gate driver used in the peak detector
prototype has a negative turn-off voltage of -10V [30], IGPeak
should be detected well before the voltage on the gate
capacitor reaches -1V. Therefore, the fluctuation of CGE with
temperature at a VGE beyond -1V should not impact the
measurement of IGPeak. For the experiments conducted in this
paper, a unipolar gate driver with a turn-off voltage of 0V (or
within temperature dependent region of Fig. 8) would yield (b)
fallacious results. Max:
190.5°C
IV. RESULTS
In the following sections, all raw data values for the
Mean:
dissipation results are included in the tables in Appendix A. 177.2°C
A. Definition of ‘Junction Temperature’
The term ‘junction temperature’ is ambiguous, since the
temperature of a power semiconductor cannot be described Min:
using a single temperature value. Instead, the junction is made 146.3°C
(c)
up of a large distribution of temperatures. In prior literature
concerning the evaluation of TSEP accuracy, the mean surface Max:
temperature and the absolute maximum temperature of the 187.7°C
chip are the two most common measurements chosen for
comparison with the TSEP measurement. In this work, the Mean:
‘junction temperature’ is assumed to be the mean surface 176.8°C
temperature of the emitter metallisation on the IGBT die.
These emitter pads can be seen in the die datasheets [28][29]
and in Figs. 2 and 3. As a result, the ‘junction temperature’ Min:
does not include the entirety of the die area, or any of the 152.7°C
attached bondwires. (d)
To extract the mean surface temperature of the emitter pads, Fig. 9. Processing of IR images to extract the junction temperature:
the IR images are processed using image masks in MATLAB (a) Unedited IR image of IGBT A during dissipation at 140A
to remove the undesired pixels. This process is depicted in (b) Cropped IR image to the active area of the die
Fig. 9. (c) IR image of bondwires with die surface removed via a MATLAB image
mask
A noteworthy observation from this procedure is that the (d) IR image of die surface with bondwires removed via a MATLAB image
bondwires experience a wider temperature distribution than mask. This image is used to calculate the mean junction temperature.
the die. From Fig. 9, where IGBT A is conducting 140A, it
B. Location of RGint
can be seen that the bondwires have both a lesser minimum
and a higher maximum temperature. The maximum The IR camera was used to perform a preliminary
temperature of the bondwires is close to 3°C higher than the assessment on the location of the internal gate resistor for each
IEEE Transactions on Power Electronics 6

RGint Calibration - All IGBTs RGint Calibration - Single IGBTs

4.6 4.6
4.4 IGBT A - T1
4.5 IGBT A - T2
4.2
IGBT B - T1
4.0 IGBT B - T2
3.8 4.4
RGint (Ω)

RGint (Ω)
3.6 IGBT A - T1
IGBT A - T2 4.3
3.4
IGBT B - T1
3.2 IGBT B - T2 4.2
3.0 IGBT A - T1+T2
2.8 4.1
2.6
2.4 4.0
30 50 70 90 110 130 150 170 30 50 70 90 110 130 150 170
Temperature (°C) Temperature (°C)
Fig. 11: RGint vs. Temperature from calibration data for IGBT A and B (IGPeak used to calculate RGint)
IGBT. To do this, IGBTs were shorted between the collector On the other hand, RGint has significant variation between
and emitter, and switched using a gate driver at a frequency of IGBTs in spite of each chip having a specified datasheet value
30kHz. Fig. 10 displays thermal images of the IGBTs during of 3.5Ω. Within chips from the same module, sensitivity was
this procedure. Clear heating in the gate pad of around 3°C fairly uniform: 3.2mΩ/°C for IGBT A and 2.9mΩ/°C for
can be seen on both IGBTs, which is assumed to be the result IGBT B. However, an offset of approximately 20-30mΩ is
of the self-heating of RGint. present between T1 and T2 for both IGBT types. Furthermore,
As a result, image masks were created in MATLAB to there is a discrepancy of around 50mΩ between IGBT A and
extract both the mean surface temperature of the emitter B. This offset could be due to manufacturing tolerances in the
metallisation on the IGBT die (IRMean), as well as the mean production of RGint. For the paralleled chips of IGBT A, the
temperature of the gate pad (IRGate). sensitivity was halved to 1.6mΩ/°C.
VCE(low) Calibration - All IGBTs
0.6

0.5

0.4
VCE (V)

0.3
IGBT A - T1
0.2 IGBT A - T2
IGBT B - T1
0.1 IGBT B - T2
(a) (b) IGBT A - T1+T2
0.0
Fig. 10. Self-heating of RGint: (a) IGBT A. (b) IGBT B. 30 50 70
90 110 130 150 170
Temperature (°C)
C. Calibration
Fig. 12: VCE(low) vs. Temperature from calibration data for IGBT A and B
Two IGBTs are characterised from each module. In
addition, the layout of the FS200R12PT4 module allowed D. Dissipation Results – Single IGBTs
IGBT A to be calibrated with two IGBTs in parallel. In this Temperature measurements during dissipation were
case, the sensing current for VCE(low) was accordingly doubled conducted at a range of current values from 40-160A. The
from 100mA to 200mA, while the gate driver remained heating current was limited to below the 200A rating of each
unchanged. IGBT in order to maintain a safe maximum junction
Calibration curves for the two TSEP measurement methods temperature of below 200°C. The input fluid to the heatsink
are shown in Figs. 11 and 12. IGPeak is used in conjunction with was maintained at 40°C during all tests.
the gate voltage swing to calculate RGint, as specified in (3). Fig. 13 displays the temperature measurement results during
Although both RGint and VCE(low) display a near linear dissipation on a single IGBT of both Type A and B.
relationship with temperature, a 2nd order polynomial fit is in Temperature measurements via IGPeak and VCE(low) are
fact used to calculate their respective relationships for when displayed, along with IR measurements regarding the mean
the TSEPs are used during dissipation. surface temperature of the die (IRMean) and gate pad (IRGate).
For the traditional VCE(low), the calibration reveals very little For IGBT A (square, gate pad centre), all temperature
variance between the chips. The temperature sensitivity is measurements appear to match closely. On the other hand, the
approximately -2.4mV/°C, with only a small offset between 4 temperature measurement methods show clear divergence on
IGBT A and B of around 6mV. Furthermore, the two IGBT B – particularly at high current levels. In IGBT B, I GPeak
paralleled chips of IGBT A displayed precisely the same clearly underestimates the mean surface temperature and
VCE(low) as when they were calibrated individually.
IEEE Transactions on Power Electronics 7

provides a temperature that is lower than measured via comparable to those obtained via VCE(low). Conversely, for
VCE(low). IGBT B, IGPeak always delivered a temperature lower than
IRMean. At lower current levels, this underestimation was not
IGBT Type A severe at around -2°C. However, this increased to -7.6°C and -
190
10.9°C at higher current (and temperature) levels.
170
IGPeak Error vs. IRMean
12
Temperature (°C)

150 10 IGBT A
8 IGBT B

Temp. Error (°C)

130 6
4
110 2
0
90 -2
Igpeak -4
Vce(low) -6
70 IR Gate -8
IR Mean -10
50 -12
20 40 60 80 100 120 140 160 40 80 100 120 140 160
Current (A) Current (A)
(a)
(a)
VCE(low) Error vs. IRMean
IGBT Type B 12
190 10 IGBT A
8 IGBT B

Temp. Error (°C)

170 6
4
2
Temperature (°C)

150 0
-2
130 -4
-6
110 -8
-10
90 -12
Igpeak 40
100 80
120 140 160
Vce(low) Current (A)
70 IR Gate
IR Mean (b)
50 Fig. 13: Measurement error vs. mean surface temperature for (a) IGPeak and (b)
20 40 60 80 100 120 140 160 VCE(low).
Current (A)
These trends could perhaps be anticipated due to the
(b)
respective locations of the gate pad. In fact, Fig. 15 shows the
Fig. 13: Temperature measurement results during dissipation from 40A to
correlation of temperature measurement via IGPeak to the
160A. (a) IGBT A. (b) IGBT B.
temperature of the gate pad measured via IR camera. In almost
To demonstrate these trends more precisely, Fig. 14 all cases on both chip types, IGPeak provided a temperature
compares both TSEP measurements in relation to IRMean for within +1°C and +3°C of the gate pad.
each IGBT. It can be observed that in all cases, V CE(low)
IGPeak Error vs. IRGate
provides a temperature that slightly overestimates the mean 4
IGBT A
surface temperature of the die. The difference between the 3
IGBT B
Temp. Error (°C)

VCElow and IRMean remains strictly lower than +2°C. These 2

results are in accordance with several previous studies 1
[18][21]. 0
The slight overestimation of the mean temperature may be a -1
consequence of the temperature gradient across the chip -2
during dissipation, which is a contrast to the homogenous -3
-4
temperature during calibration. Due to the negative 40 100 80 120 140
temperature coefficient of VCE(low), the central and hotter parts Current (A)
of the chip experience an increased current density compared Fig. 15: Temperature measurement via IGPeak: error vs. gate pad temperature.
to the colder outer parts of the chip. As the entire current in A gate pad at the side experiences a comparatively lower
the chip must equal the total sense current of 100mA, these temperature than one in the centre due to the temperature
hotter areas subsequently contribute a larger weighting in the gradient across the chip during dissipation. These temperature
composition of VCE(low). gradients generally become more significant at higher mean
Meanwhile, IGPeak provided a temperature that differed in temperatures. This is shown in Fig. 16, which displays the
comparison to IRMean depending on the chip type. For IGBT A, temperature profile across IGBT B at all investigated current
with a centrally located gate pad, Fig. 14 shows that I GPeak levels. This is therefore an explanation for why IGPeak still
obtained a temperature that was higher than the mean surface delivered a reasonable approximation of IRMean (within -2°C)
temperature by between 1 and 4°C. These results are on IGBT B up to 100A dissipation current, while severely
IEEE Transactions on Power Electronics 8

IGBT B: Temperature Distribution

205
190
175

Temperature (°C)
160 160A
145
140A
130
115 120A

100 100A
85 60A
70
55 40A
0 20 40 60 80 100 120 140 160
Gate Pixels
Pad
Fig. 16: Temperature profile across IGBT B from 40A to 160A. Temperature is plotted along the dotted line

underestimating IRMean as the current and temperature Healthy IGBT Degraded IGBT
increased.
These results infer that use of IGPeak for junction temperature
measurement on single IGBTs would require consideration of
the gate pad position, as well as the expected operating
temperatures and temperature distribution throughout the chip.
The fact that the IGPeak method consistently measures a
slight overestimation of the gate pad temperature could
indicate a systematic error in the experiment. This may be due IGBT A: Degraded vs. Healthy
205
to a suboptimal design of the peak detector circuit, or a Degraded
systematic error in the measurement principle. For example, 195 Healthy
the gate connection in the IGBTs studied is not a kelvin
Temperature (°C)

connection. Therefore, the collector current and the gate 185

current must share the same path (including bondwires), which
175
could produce a discrepancy between the calibration
conditions with 0A load current, and the dissipation conditions 165
with a high heating current.
155
E. Dissipation Results: Degraded Single IGBT with Partial
Bondwire Removal 145
0
60 75 90 105 12015 30 45
To begin an assessment on the robustness of the I GPeak
Pixels
method, temperature measurements were performed on a
Fig. 17: Comparison of IGBT A temperature profile at 140A before and after
degraded IGBT suffering bondwire lift-off. The bondwire lift- bondwire removal. Temperature is displayed along diagonal lines
off mechanism was selected for two reasons. Firstly, it is one
of the most common degradation mechanisms written about in IGBT Type A - Degraded
190
academic literature, and secondly it is easy to emulate without
requiring removal of the power modules from the test setup. In 170
this manner, the IGPeak method can be assessed in precisely the
Temperature (°C)

150
same conditions for both the healthy and degraded states.
130
To achieve the degraded condition, 3 bondwires on IGBT A
were cut with wire clippers, resulting in the complete 110
disconnection of a central emitter pad on the IGBT. An IR
90 Igpeak
image of this condition at 140A is displayed in Fig. 17, from Vce(low)
which, clear distortion of the temperature distribution can be 70 IR Gate
IR Mean
seen in comparison to the healthy IGBT. Mean and maximum 50
temperatures of the IGBT are around 5-10°C higher after 20 40 60 80 100 120 140 160
bondwire removal. Current (A)
Temperature measurements on the degraded IGBT A are Fig. 18: Temperature measurement results during dissipation on IGBT A with
shown in Fig. 18. The results appear similar to the findings of bondwires removed.
IGBT A in a healthy condition (Fig. 13) – all temperature For further analysis, Fig. 19 is presented and displays a
measurements match closely. comparison of IGPeak in relation to IRMean and IRGate, both
before and after degradation. The correlation between I GPeak
IEEE Transactions on Power Electronics 9

and IRGate remains almost unchanged between healthy and inductance is mainly comprised of the terminal leads and
degraded conditions. However, a non-negligible shift can be packaging, the lift-off of just a few bondwires cannot
seen when comparing IGPeak to IRMean. In a healthy state, IGPeak significantly change the total inductance in the circuit [31].
typically delivered a temperature between 2-3°C larger than It must also be noted that merely cutting three bondwires on
the mean junction temperature. After bondwire removal, this an IGBT is not a realistic representation of a degraded
overestimation reduced by 1°C to 2°C. In fact, a -0.4°C condition. In practical applications an IGBT can be subject to
underestimation of IRMean was observed at the highest heating a wide variety of failure mechanisms, some of which may be
current of 140A. Although this adjustment may seem small, it far more pertinent in influencing the IGPeak method. To provide
is in clear contrast to VCE(low), whose correlation with IRMean more thorough assessment on the robustness of I GPeak, an
altered less than ±0.2°C in all cases, as shown in Fig. 20. investigation on IGBTs with a degraded gate oxide or gate
capacitance would be relevant, especially as there is data to
IGBT A - IGPeak Error vs. IRGate
4 suggest that IGBT gate capacitances can vary through aging
Healthy
3 Degraded [101][102].
Temp. Error (°C)

2
1
F. Dissipation Results: Paralleled IGBTs
0 The module structure for IGBT A allowed investigation of
-1 two IGBTs in parallel. For paralleled IGBTs, the heating
-2 current ranged from 120A to 240A, and the sense current for
-3 VCE(low) was accordingly doubled from 100mA to 200mA. The
-4 gate driver and peak detector were unchanged from previous
40 80 100 120 140
Current (A) investigations, with a single gate driver being used to drive
(a) both IGBTs.
IGBT A- IGPeak Error vs. IRMean First of all, the paralleled IGBTs were assessed without
4 inducing a temperature imbalance. In this condition, the
Healthy
3 Degraded temperature difference between the mean surface temperatures
Temp. Error (°C)

2
of each IGBT was a maximum of 2°C. Temperature
1
measurements in this paralleled state are displayed in Fig. 21.
0
Since the temperature difference between the two IGBTs is
-1
minimal, single IR measurements are displayed which is the
-2
-3 cumulative mean of both IGBTs (i.e.
-4 ).
40 100 80 120 140
Current (A)
(b) IGBT Type A - Paralleled
180
Fig. 19: Temperature measurement via IGPeak in degraded and healthy
conditions: (a) Error vs. gate pad temperature. (b) Error vs. mean surface
temperature. 160
Temperature (°C)

IGBT A - VCE(low) Error vs. IRMean

4 140
Healthy
3 Degraded
Temp. Error (°C)

2 120
1 Igpeak
0 100 Vcelow
IR Gate
-1
IR Mean
-2 80
-3 100 120 140 160 180 200 220 240 260
-4 Current (A)
40 10080 120 140
Current (A) Fig. 21: Temperature measurement results during dissipation for 2 paralleled
IGBTs (IGBT A) from 120A – 240A.
Fig. 20: Temperature measurement via VCE(low): error vs. mean surface
temperature in healthy and degraded condition The results on IGBT A in a paralleled configuration follow
These results again infer that IGPeak is primarily influenced the same trends as with single IGBTs. Fig. 22 shows that IGPeak
by local conditions in the vicinity of the gate pad, rather than delivers a temperature within +2°C of the gate pad
the overall active area of the die as is the case with the temperature. This leads to an overestimation of IRMean by
traditional VCE(low). between +1°C and +3°C. Additionally, VCE(low) again provides
It is perhaps logical that IGPeak was found to be largely a temperature closely correlated with the mean surface
unaffected by bondwire lift-off, since the emitter bondwires temperature, with measurements at all current levels showing
may contribute a total resistance of just a few mΩ, as opposed a difference of less than +1°C.
to the 3.5Ω of RGint. Additionally, since the parasitic gate
IEEE Transactions on Power Electronics 10

IGPeak Error vs. IRGate (Paralleled) IGPeak Error vs. Mean-IRGate (Paralleled)
4 4
Temp. Error (°C) 3 3

Temp. Error (°C)

2 2
1 1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
120 160 200 240 160 120 200
Current (A) Current (A)
(a) Fig. 24: IGPeak on 2 paralleled IGBTs (IGBT A) with a temperature
VCE(low) and IGPeak Error vs. IRMean disequilibrium: error vs. cumulative mean of gate pad temperature.
4
IGPeak delivers a temperature within +2°C of the cumulative
3
mean temperature of the gate pad, as shown in Fig. 24.
Temp. Error (°C)

2
1
The temperature profile of the two IGBTs with a 200A
0
heating current is shown in Fig. 25. Here, the I GPeak and
-1 VCE(low) measurements are within 1°C of each other and appear
-2 to correspond closely with the combined mean temperature
Igpeak profile of the two IGBTs. In fact, both TSEP measurements
-3 Vcelow
-4 overestimate the cumulative mean surface temperature by
120 160 200 240 between +1°C and +3°C, as shown in Fig. 26.
Current (A)
(b) IGBT 1 IGBT 2
Fig. 22: Temperature measurement error for 2 paralleled IGBTs (IGBT A), (a)
IGPeak error vs. gate pad temperature. (b) IGPeak and VCE(low) errors vs. mean
surface temperature.

G. Dissipation Results: Paralleled IGBTs with Temperature

Disequilibrium
A more interesting scenario is to examine the TSEP
methods on paralleled IGBTs that have a large temperature 2 Paralleled IGBTs at 200A
imbalance. To achieve this, the connection from the heatsink 170
to the baseplate was loosened on one side of the power module 165
so that one IGBT suffered a deteriorated thermal contact. The 160 IGPeak
Temperature (°C)

IGBTs were then examined with a heating current of up to 155

200A, where the temperature disequilibrium between the two 150 VCE(low)
IGBTs reached close to 20°C. 145
Fig. 23 displays the temperature measurement results with 140
T1
this thermal imbalance. In this figure, the mean surface 135 T2
temperature measured via IR camera is included for both 130 Mean T1||T2
Igpeak
IGBTs. It can be seen that both IGPeak and VCE(low) provide a 125 Vce(low)
temperature in between the IRMean of IGBT 1 and IGBT 2. 120
0 15
60 75 90 105 120 30 45
IGBT Type A - Paralleled Pixels
165
Fig. 25: Temperature profile of 2 paralleled IGBTs (IGBT A) with 200A
heating current. Temperature is plotted along diagonal lines.
145
Temperature (°C)

VCE(low) and IGPeak Error vs. IRMean

4
3
Temp. Error (°C)

125 2
1
Igpeak 0
105 Vce(low)
-1
IR Mean T1
IR Mean T2 -2
Igpeak
85 -3 Vce(low)
100 120 140 160 180 200 220 -4
Current (A) 120 160 200
Current (A)
Fig. 23: Temperature measurements during dissipation on 2 paralleled IGBTs
(IGBT A) with a temperature disequilibrium. Fig. 26: IGPeak and VCE(low) on 2 paralleled IGBTs (IGBT A): error vs.
cumulative mean surface temperature.
IEEE Transactions on Power Electronics 11

These results suggest that IGPeak can provide an adequate tracking fast dynamic changes in temperature should also be a
assessment of the mean temperature of IGBT chips in a priority. Finally, an evaluation of robustness towards gate
paralleled condition, at the least in line with results provided oxide degradation introducing non-negligible gate leakage
by the traditionally used VCE(low). This is providing that the currents should also be carried out.
IGBTs contain a centrally located gate pad.
For a more detailed assessment on the performance of I GPeak VI. APPENDIX A
with paralleled chips, a number of additional studies could be Complete table of temperature measurement results from
carried out. Clearly, immediate steps would be to assess I GPeak experiments performed.
on a greater number than two IGBTs in parallel, as well as on
IGBT A - Healthy
paralleled IGBTs with the gate pad at the edge of the die.
Other relevant studies would be to investigate the impact Current IGPeak VCE(low) IRGate IRMean IRMax
(A) (°C) (°C) (°C) (°C) (°C)
different paralleling layout techniques such as grouping 0 42.1 42.0 41.7 41.8 42.1
IGBTs into ‘cells’ [32]. 40 63.9 63.0 63.3 63.1 65.3
80 98.7 97.6 97.4 96.8 102.1
V. CONCLUSION 100 122.3 120.5 120.1 119.4 126.7
120 150.1 148.0 147.2 146.5 156.5
This paper uses infra-red measurements to experimentally 140 179.2 178.2 177.5 176.9 190.5
evaluate the accuracy of the Peak Gate Current (I GPeak) method
for IGBT junction temperature measurement. The accuracy of IGBT A - Degraded
IGPeak is compared to a traditional electrical temperature Current IGPeak VCE(low) IRGate IRMean IRMax
measurement method, the voltage drop at low current (A) (°C) (°C) (°C) (°C) (°C)
(VCE(low)). The investigation is performed with IGBTs 0 40.9 40.5 40.8 40.9 41.3
40 63.1 62.7 62.9 63.0 65.8
operating under constant current injection and temperature
80 99.6 98.6 97.7 98.0 105.1
measurements are taken while the IGBT is in a thermal 100 123.9 122.9 121.3 121.8 132.2
steady-state. 120 152.5 152.1 149.6 150.6 165.3
The IGPeak method is found to correlate closely with the 140 182.1 184.0 180.7 182.5 203.1
temperature conditions in the vicinity of the gate pad. This is
in contrast to the VCE(low), which is influenced by the entire IGBT B
area of the die. As a result, IGPeak provided a slight Current IGPeak VCE(low) IRGate IRMean IRMax
overestimation of the mean surface temperature of the die in (A) (°C) (°C) (°C) (°C) (°C)
0 41.8 41.6 41.5 41.6 41.8
IGBTs with a centrally located gate pad, while 40 60.6 62.4 60.9 62.2 64.3
underestimating the mean surface temperature in IGBTs with 80 90.8 93.5 89.2 92.7 97.6
a gate pad located at the side. These trends became more 100 109.5 112.7 106.6 111.7 118.4
pronounced as the overall temperature of the dies increased, as 120 127.4 133.2 124.9 132.1 140.7
140 147.6 156.4 144.9 155.3 166.5
a result of more pronounced temperature gradients. 160 175.0 186.5 171.3 186.0 201.5
The IGPeak method is found to be largely unaffected by
partial bondwire lift-off, which is a common degradation
IGBT A - 2x Paralleled without Temperature Disequilibrium
mechanism in IGBTs. In this respect, the IGPeak method
Current IGPeak VCE(low) IRGate IRGate IRMean IRMean
continued to provide a temperature associated with the gate (A) (°C) (°C) T1 (°C) T2 (°C) T1 (°C) T2 (°C)
pad temperature when the IGBT was in a degraded condition. 120 92.2 90.6 90.7 90.8 90.3 90.4
However, since the temperature distribution in the die was 160 113.7 111.6 110.5 112.6 110.0 111.9
modified due to this degradation, the correlation with the 200 140.3 138.1 136.7 139.5 135.7 138.6
240 173.9 171.7 171.0 172.6 170.1 172.2
mean surface temperature was slightly altered.
In paralleled IGBTs where the gate pad is centrally located,
IGBT A - 2x Paralleled with Temperature Disequilibrium
IGPeak was found to have similar averaging properties as the
traditional VCE(low) method, and provided a temperature Current IGPeak VCE(low) IRGate IRGate IRMean IRMean
(A) (°C) (°C) T1 (°C) T2 (°C) T1 (°C) T2 (°C)
slightly overestimating the cumulative mean temperature 120 96.2 94.1 89.2 98.6 88.4 98.1
when a large temperature imbalance is present between the 160 122.0 121.1 113.1 127.1 112.2 126.3
IGBTs. 200 153.1 152.3 142.5 160.5 141.4 159.4
As a general conclusion, using and interpreting
measurement results provided by IGPeak requires a good VII. REFERENCES
knowledge of the gate pad position, as well as likely operating [1] H. Wang, M. Liserre, F. Blaabjerg, "Toward Reliable Power Electronics:
temperatures and the temperature gradient in the chip. Challenges, Design Tools, and Opportunities," IEEE Ind. Electron.
Mag., vol.7, no.2, pp.17-26, June 2013.
Future work should primarily involve extending the [2] D.-L. Blackburn, “Temperature measurements of semiconductor
validation to real functional conditions that are not devices—A review,” in Proc. 20th Annu. Semicond. Therm. Meas.
experienced during constant current injection, and to a Manage. Symp., San Jose, CA, Mar. 11–24, 2004,
statistically significant number of IGBTs with differing power
ratings and manufacturer. An assessment of the I GPeak method
IEEE Transactions on Power Electronics 12

[3] D.L. Blackburn, “A review of thermal characterization of power [23] Y. Lembeye, J. L. Schanen, and J. P. Keradec, “Experimental
transistors,” in Proc. 4th Annu. IEEE Semicond. Therm. Temp. Meas. characterization of insulated gate power components: Capacitive
Symp., San Diego, CA, Feb. 10–12, 1988. aspects,” in Proc. 32nd IAS Annu. Meeting Ind. Appl. Conf., vol. 2, pp.
[4] Y. Avenas, L. Dupont, Z. Khatir, "Temperature Measurement of Power 983–988, Oct. 5–9, 1997.
Semiconductor Devices by Thermo-Sensitive Electrical Parameters—A [24] Infineon Application Note, “Industrial IGBT modules explanation of
Review", IEEE Trans. Power Electron., vol.27, no.6, pp.3081-3092, technical information,” AN 2011-05, V1.1, May 2013.
June 2012. [25] F.F. Oettinger, D.L. Blackburn, S. Rubin, "Thermal characterization of
[5] N. Baker, M. Liserre, L. Dupont, Y. Avenas, "Improved Reliability of power transistors," IEEE Transactions on Electron Devices, vol.23, no.8,
Power Modules: A Review of Online Junction Temperature pp.831-838, Aug 1976.
Measurement Methods," IEEE Industrial Electronics Magazine, vol.8, [26] V. Smet, F. Forest, J. Huselstein, A. Rashed, F. Richardeau, "Evaluation
no.3, pp.17-27, Sept. 2014. of VCE Monitoring as a Real-Time Method to Estimate Aging of Bond
[6] P.Ghimire, A.R. deVega, S. Beczkowski, B. Rannestad, S.Munk- Wire-IGBT Modules Stressed by Power Cycling," IEEE Trans. on
Nielsen, and P. Thogersen, “Improving power converter reliability: Industrial Electronics, vol.60, no.7, pp.2760-2770, July 2013.
Online monitoring of high-power IGBT modules,” IEEE Ind. Electron. [27] F. Forest, A. Rashed, J.-J. Huselstein, T. Martiré, P. Enrici, “Fast power
Mag., vol. 8, no. 3, pp. 40–50, Sep. 2014. cycling protocols implemented in an automated test bench dedicated to
[7] L. Dupont and Y. Avenas, “Evaluation of thermo-sensitive electrical IGBT module ageing”, Microelectron. Reliabil., Vol. 55, Issue 1, Pages
parameters based on the forward voltage for on-line chip temperature 81-92, Jan. 2015.
measurements of IGBT devices,” in Proc. IEEE Energy Convers. Congr. [28] Infineon Technologies, “IGC189T120T8RL” Edition 1.1, 20th June
Expo., Sep. 14–18, 2014, pp. 4028–4035. 2013.
[8] V. Sundaramoorthy, E. Bianda, R. Bloch, and F. Zurfluh, “Simultaneous [29] Infineon Technologies, “IGC193T120T8RM” Edition 1.2, 20th June
online estimation of junction temperature and current of IGBTs using 2013.
emitter-auxiliary emitter parasitic inductance,” in Proc. PCIM Eur., May [30] http://www.igbt-driver.com/products/scale-2-plug-and-play-
20–22, 2014, pp. 1–8. drivers/2sp0320
[9] V. Sundaramoorthy, E. Bianda, R. Bloch, I. Nistor, G. Knapp, and A. [31] Shengqi Zhou; Luowei Zhou; Pengju Sun, "Monitoring Potential
Heinemann, “Online estimation of IGBT junction temperature (Tj) using Defects in an IGBT Module Based on Dynamic Changes of the Gate
gate-emitter voltage (Vge) at turn-off,” in Proc. 15th Eur. Conf. Power Current," IEEE Transactions on Power Electronics, vol.28, no.3,
Electron. Appl., Sept. 2–6, 2013, pp. 1–10. pp.1479-1487, March 2013.
[10] H. Luo, W. Li, and X. He, “Online high-power p-i-n diode chip [32] Kouichi Mochizuki, Yoshifumi Tomomatsu, “IGBT Module”, Patent US
temperature extraction and prediction method with maximum recovery 20050194660 A1, Sept 2005
current di/dt,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2395– [33] L. Boyer. Analyse des propri´t´s de l’oxyde de grille des composants
2404, May 2015. semi-conducteurs de puissance soumis à des contraintes
[11] N. Baker, S. Munk-Nielsen, F. Iannuzzo, M. Liserre, "IGBT Junction électrothermiques cycliques : vers la définition de marqueurs de
Temperature Measurement via Peak Gate Current," in IEEE veillissement. PhD thesis, Thèse de l’Université Montpellier 2, 2010.
Transactions on Power Electronics, vol.31, no.5, pp. 3784-3793, May [34] Boyer, L.; Notingher, P.; Agnel, S., "Characterization of a Trench-Gated
2016. IGBT using the split C-V Method," in Applied Power Electronics
[12] N. Baker, L. Dupont, S. Munk-Nielsen, F. Iannuzzo, M. Liserre, Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual
"Experimental evaluation of IGBT junction temperature measurement IEEE , vol., no., pp.2055-2060, 15-19 Feb. 2009
via peak gate current," in 17th European Conference on Power
Electronics and Applications (EPE'15 ECCE-Europe), pp. 1-11, 8-10
Sept. 2015.
Nick Baker received the M.Eng. degree in
[13] C. Butron, J. Alexander, B. Strauss, G. Mitic, and A. Lindemann, Electrical & Electronic Engineering from
“Investigation of temperature sensitive electrical parameters for power Loughborough University, UK, in 2011. In
semiconductors (IGBT) in real-time applications,” in Proc. PCIM Eur., 2013 he began a PhD at Aalborg
May 20–22, 2014, pp. 1–9.
[14] Z.Xu, F.Wang, and P.Ning, “Junction temperature measurement of
University, Denmark in Temperature
IGBTs using short circuit current,” in Proc. Energy Convers. Congr. Measurements of Power Semiconductor
Expo., Sep. 15–20, 2012, pp. 91–96. Devices using Electrical Parameters. He
[15] M. Denk and M. Bakran, “An IGBT driver concept with integrated real was awarded with the European Power
time junction temperature measurement,” in Proc. PCIM Eur.,May 20–
22, 2014, pp. 1–8.
Electronics Association Young Member
[16] H.R. Plumlee, D.A. Peterman, "Accuracy of junction temperature Award in 2015.
measurement in silicon power transistor", International Electron Devices
Meeting, vol.12, no., pp.86, 1966. Laurent Dupont received his electrical
[17] X. Perpina, J. F. Serviere, J. Saiz, D. Barlini, M. Mermet-Guyennet, and
J. Millan, “Temperature measurement on series resistance and devices in
engineering degree in 2002 and his Ph.D.
power packs based on on-state voltage drop monitoring at high current,” degree in electrical engineering from the
Microelectron. Rel., vol. 46, pp. 1834–1839, Sept.–Nov. 2006. École Normale Supérieure de Cachan,
[18] L. Dupont, Y. Avenas, and P. O. Jeannin, “Comparison of junction France, in 2006. After ten years of
temperature evaluations in a power IGBT module using an IR camera
and three thermo-sensitive electrical parameters,” IEEE Trans. Ind.
experience in industry, he works as
Appl., vol. 49, no. 4, pp. 1599–1608, Jul./Aug. 2013. research scientist in the Systèmes et
[19] Y. Avenas and L. Dupont, “Evaluation of IGBT thermo-sensitive Applications des Technologies de
electrical parameters under different dissipation conditions— l'Information et de l'Energie (SATIE)
Comparison with infrared measurements,” Microelectron. Rel., vol. 52,
pp. 2617–2626, Nov.2012.
Laboratory in the Institut français des sciences et technologies
[20] D.L. Blackburn and D.W Berning, "Power MOSFET Temperature des transports, de l'aménagement et des réseaux (IFSTTAR),
Measurements", in Proc. I982 IEEE Power Electron. Specialists Versailles, France, since 2007. His research interest is the
Conference, 400-407, 1982. robustness evaluation of power semiconductor modules. In the
[21] R. Schmidt, U. Scheuermann, "Using the chip as a temperature sensor
— The influence of steep lateral temperature gradients on the Vce(T)-
French project MEMPHIS, supported by the National
measurement," 13th European Conference on Power Electronics and Research Agency, his research activities are focused on the
Applications 2009, pp.1-9, 8-10 Sept. 2009. evaluation of functional and aging indicators usable to monitor
[22] J. Baliga, “Power Semiconductor Devices”, International Thomson the health status of power components.
Publishing, Boston, 1996
IEEE Transactions on Power Electronics 13

Stig Munk-Nielsen (S’92–M’97) received IEEE Transactions on Industrial Electronics, Transactions on

the M.Sc. and Ph.D. degrees from Aalborg Industrial Informatics and Transactions on Power Electronics.
University, Aalborg, Denmark, in 1991
and 1997, respectively. He is currently Marco Liserre (S'00-M'02-SM'07-F´13)
Professor at the Department of Energy received the MSc and PhD degree in
Technology, Aalborg University. His Electrical Engineering from the Bari
research interests include LV and MV Polytechnic, respectively in 1998 and 2002.
inverters, power module packaging, He has been Associate Professor at Bari
permanent magnet biased inductors, accelerated lifetime test Polytechnic and Professor in reliable power
and power module on-state voltage and temperature electronics at Aalborg University
monitoring. In the last ten years, he has been involved or has (Denmark). He is currently Full Professor
managed 12 research projects. and he holds the Chair of Power Electronics at Christian-
Albrechts-University of Kiel (Germany). He has published
Francesco Iannuzzo (M ’04, SM ’12) over 200 technical papers (more than 60 of them in
earned his M.Sc. (laurea) degree cum international peer-reviewed journals), 4 chapters of a book and
laude in 1997 and his Ph.D. degree in a book (Grid Converters for Photovoltaic and Wind Power
Electronics and Information Engineering Systems, ISBN-10: 0-470-05751-3 – IEEE-Wiley, second
from the University of Naples, Italy, in reprint, also translated in Chinese). These works have received
2001, with a study on the reliability of more than 12000 citations. Marco Liserre is listed in ISI
power MOSFETs during diode operations. Thomson report “The world’s most influential scientific
He is primarily specialized in the field of minds”, 2014.
power device modelling. He has been Researcher since 2000 He has been recently awarded with an ERC Consolidator
with University of Cassino, Italy, where he became Aggregate Grant for an overall budget of 2 MEuro for the project “The
professor in 2006 and he is currently Associate professor since Highly Efficient And Reliable smart Transformer (HEART), a
2012. new Heart for the Electric Distribution System”.
In 2014 he got a contract as professor in Reliable Power He is member of IAS, PELS, PES and IES. He is Associate
Electronics at the Aalborg University, Denmark, where he is Editor of the IEEE Transactions on Industrial Electronics,
also part of CORPE (Center Of Reliable Power Electronics, IEEE Industrial Electronics Magazine, IEEE Transactions on
http://www.corpe.et.aau.dk). He is author or co-author of more Industrial Informatics, where he is currently Co-Eic, IEEE
than 90 publications on journals and international conferences, Transactions on power electronics and IEEE Journal of
and one pending patent on an innovative inverter topology for Emerging and Selected Topics in Power Electronics. He has
very compact, galvanic-isolated auxiliary power supply for been Founder and Editor-in-Chief of the IEEE Industrial
heavy trains. His research interests are in the field of reliability Electronics Magazine, Founder and the Chairman of the
of power devices, including against cosmic rays, power device Technical Committee on Renewable Energy Systems, Co-
failure modelling and testing of power modules up to MW- Chairman of the International Symposium on Industrial
scale under extreme conditions, like overvoltage, overcurrent Electronics (ISIE 2010), IES Vice-President responsible of the
and overtemperature. publications. He has received the IES 2009 Early Career
Prof. Iannuzzo was the Technical Programme Committee Award, the IES 2011 Anthony J. Hornfeck Service Award, the
co-Chair in two editions of ESREF, the European Symposium 2014 Dr. Bimal Bose Energy Systems Award, the 2011
on REliability and Failure analysis. He is a senior member of Industrial Electronics Magazine best paper award and the
the IEEE (Reliability Society, Industrial Electronic Society Third Prize paper award by the Industrial Power Converter
and recently Industrial Application Society) and of AEIT Committee at ECCE 2012, 2012. He is senior member of IES
(Italian Electric, Electronic and Telecommunication AdCom. In 2013 he has been elevated to the IEEE fellow
Association). He permanently serves as expert and peer grade with the following citation “for contributions to grid
reviewer for several conferences and journals in the field, like: connection of renewable energy systems and industrial
APEC, ECCE, ESREF, IECON, Microelectronics Reliability, drives”.