13/11/2013

DC Biasing–BJTs
Pertemuan 9
Elektronika I

www.themegallery.com
LOGO

Biasing

Biasing: The DC voltages applied to a transistor in

order to turn it on so that it can amplify the AC signal.

LOGO

1
 13/11/2013

Operating Point

The DC input
establishes an
operating or
quiescent point
called the Q-point.

LOGO

The Three States of Operation

• Active or Linear Region Operation

Base–Emitter junction is forward biased
Base–Collector junction is reverse biased

• Cutoff Region Operation

Base–Emitter junction is reverse biased

• Saturation Region Operation

Base–Emitterjunction is forward biased
Base–Collector junction is forward biased

LOGO

2
 13/11/2013

DC Biasing Circuits

• Fixed-bias circuit
• Emitter-stabilized bias circuit
• Collector
Collector-emitter loop
• Voltage divider bias circuit
• DC bias with voltage feedback

LOGO

Fixed Bias

LOGO

3
 13/11/2013

The Base-Emitter Loop

From Kirchhoff ’s voltage

law:
+V
VCC – IBRB – VBE = 00

Solving for base current:

V CC − V BE
BE
IB =
RB

LOGO

Collector-Emitter Loop

Collector current:
I C = βI B

From Kirchhoff ’s voltage law:

VCE = VCC − I C R C

LOGO

4
 13/11/2013

Saturation

When the transistor is operating in saturation, current

through the transistor is at its maximum possible value.

V CC
I Csat =
RC

VCE ≅ 0 V

LOGO

Load Line Analysis

The end points of the load line are:

ICsat
IC = VCC / RC
VCE = 0 V
VCEcutoff
VCE = VCC
IC = 0 mA

The Q-point is the operating point:

• where the value of RB sets the value of
IB
• that sets the values of VCE and IC

LOGO

5
 13/11/2013

Circuit Values Affect the Q-Point

more …

LOGO

Circuit Values Affect the Q-Point

more …

LOGO

6
 13/11/2013

Circuit Values Affect the Q-Point

LOGO

Emitter-Stabilized Bias Circuit

Adding a resistor
(RE) to the emitter
circuit stabilizes
the bias circuit.

LOGO

7
 13/11/2013

Base-Emitter Loop

From Kirchhoff ’s voltage law:

+ VCC - I E R E - VBE - I E R = 0
E
Since IE = (β + 1)IB:

VCC - I B R B - (β + 1)I B R = 0
E
Solving for IB:
VCC - VBE
IB =
R B + (β + 1)R E

LOGO

Collector-Emitter Loop
From Kirchhoff ’s voltage law:
I R +V +I R −V =0
E E CE C C CC

Since IE ≅ IC:
VCE V C (R C + REE )
CE = CC – IC

Also:
VE = I E R E
VC = VCE + VE = VCC - I C R C
VB = VCC – I R R B = VBE + VE

LOGO

8
 13/11/2013

Improved Biased Stability

Stability refers to a circuit condition in which the currents and voltages

will remain fairly constant over a wide range of temperatures and
transistor Beta (β) values.

Adding RE to the emitter improves the stability of a transistor.

LOGO

Saturation Level

The endpoints can be determined from the load line.

VCEcutoff: ICsat:
VCE = VCC VCE = 0 V
I C = 0 mA VCC
IC =
RC + RE

LOGO

9
 13/11/2013

Voltage Divider Bias

This is a very stable

bias circuit.

Th currents
The t andd
voltages are nearly
independent of any
variations in β.

LOGO

Approximate Analysis
Where IB << I1 and I1 ≅ I2 :
R 2 VCC
VB =
R1 + R 2

Where βRE > 10R2:

I E = VE
RE
VE = VB − VBE

From Kirchhoff ’s voltage law:

VCE = VCC − IC R C − I E R E
IE ≅ IC
VCE = VCC −I C (RC + R E )

LOGO

10
 13/11/2013

Voltage Divider Bias Analysis

Transistor Saturation Level

I Csat = I Cmax = V CC
RC + R E

Load Line Analysis

Cutoff: Saturation:
VCC
VCE = VCC IC =
RC + RE
I C = 0mA
VCE = 0V

LOGO

DC Bias with Voltage Feedback

Another way to
improve the stability
of a bias circuit is to
add a feedback path
from collector to
base.

In this bias circuit

the Q-point is only
slightly dependent on
the transistor beta, β.

LOGO

11
 13/11/2013

Base-Emitter Loop
From Kirchhoff ’s voltage law:
VCC – I′C R C – I B R B – VBE – I E R E = 0

Where IB << IC:

I' = I + I ≅ I
C C B C

Knowing IC = βIB and IE ≅ IC, the loop

equation becomes:
VCC – βI B RCC − I B RBB − VBE − βI BB R E = 0

Solving for IB:

VCC −V VBE
IB =
R B + β(R C + R E )

LOGO

Collector-Emitter Loop

Applying Kirchoff ’s voltage law:

IE + VCE + I’CRC – VCC = 0

Since I C ≅ IC and IC = βIB:

IC(RC + RE) + VCE – VCC =0

Solving for VCE

C:E
CE

VCE = VCC – IC(RC + RE)

LOGO

12
 13/11/2013

Base-Emitter Bias Analysis

Transistor Saturation Level

I Csat = I Cmax = V CC
RC + RE

Load Line Analysis

Cutoff: Saturation:
V
VCE = VCC I = CC
C R +R
IC = 0 mA C E
VCE = 0 V

LOGO

Transistor Switching Networks

Transistors with only the DC source applied can be used

as electronic switches.

LOGO

13
 13/11/2013

Switching Circuit Calculations

Saturation current:
VCC
I Csat =
RC

To ensure saturation:
I Csat
IB >
β dc

Emitter-collector resistance
at saturation and cutoff:

VCEsat
R sat =
I Csat

VCC
R cutoff =
I CEO

LOGO

Switching Time

Transistor switching times:

t on = t r + t d

t off = t s + t f

LOGO

14
 13/11/2013

Troubleshooting Hints
• Approximate voltages
– VBE ≅ .7 V for silicon transistors
– VCE ≅ 25% to 75% of VCC
• Test for opens and shorts with an ohmmeter.
• Test the solder joints.
• Test the tran tor with a transistor tester or a curve tracer.
• Note that the load or the next stage affects the transistor operation.

LOGO

PNPTransistors

The analysis for pnp transistor biasing circuits is the same

as that for npn transistor circuits. The only difference is that
h currents are fl
the i iin the
flowing h oppositei di i
direction.

LOGO

15