Reference Guide

CPU12RG/D
Rev. 2, 11/2001
CPU12 Reference Guide
(for HCS12 and original
M68HC12)

0 7

15

8-BIT ACCUMULATORS A AND B

OR
16-BIT DOUBLE ACCUMULATOR D

15

INDEX REGISTER X

15

INDEX REGISTER Y

15

SP

STACK POINTER

15

PC

PROGRAM COUNTER

S X H I N Z V C

CONDITION CODE REGISTER

CARRY
OVERFLOW
ZERO
NEGATIVE
MASK (DISABLE) IRQ INTERRUPTS
HALF-CARRY
(USED IN BCD ARITHMETIC)
MASK (DISABLE) XIRQ INTERRUPTS
RESET OR XIRQ SET X,
INSTRUCTIONS MAY CLEAR X
BUT CANNOT SET X
STOP DISABLE (IGNORE STOP OPCODES)
RESET DEFAULT IS 1

Figure 1. Programming Model

Motorola, Inc., 2001

CPU12RG/D

Stack and Memory Layout

HIGHER ADDRESSES

SP BEFORE
INTERRUPT
RTNLO
RTNHI
YLO
YHI
XLO
XHI
A
B
SP AFTER
INTERRUPT

CCR
LOWER ADDRESSES

STACK UPON ENTRY TO SERVICE ROUTINE

IF SP WAS ODD BEFORE INTERRUPT
SP +8

RTNLO

SP +6

YLO

SP +4
SP +2
SP

STACK UPON ENTRY TO SERVICE ROUTINE

IF SP WAS EVEN BEFORE INTERRUPT

SP +9

SP +9

RTNHI

SP +7

SP +7

RTNHI

RTN LO

SP +8

XLO

YHI

SP +5

SP +5

YHI

YLO

SP +6

XHI

SP +3

SP +4

XHI

XLO

SP +4

CCR

SP +1

SP +1

SP +2

SP 1

SP 1

CCR

SP

SP 2

SP +10

Interrupt Vector Locations

$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFC0$FFF1

Power-On (POR) or External Reset

Clock Monitor Reset
Computer Operating Properly (COP Watchdog Reset
Unimplemented Opcode Trap
Software Interrupt Instruction (SWI)
XIRQ
IRQ
Device-Specific Interrupt Sources

Notation Used in Instruction Set Summary

CPU Register Notation
Accumulator A A or a
Accumulator B B or b
Accumulator D D or d
Index Register X X or x

Index Register Y Y or y
Stack Pointer SP, sp, or s
Program Counter PC, pc, or p
Condition Code Register CCR or c

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Explanation of Italic Expressions in Source Form Column

abc A or B or CCR
abcdxys A or B or CCR or D or X or Y or SP. Some assemblers also allow T2 or T3.
abd A or B or D
abdxys A or B or D or X or Y or SP
dxys D or X or Y or SP
msk8 8-bit mask, some assemblers require # symbol before value
opr8i 8-bit immediate value
opr16i 16-bit immediate value
opr8a 8-bit address used with direct address mode
opr16a 16-bit address value
oprx0_xysp Indexed addressing postbyte code:
oprx3,xys Predecrement X or Y or SP by 1 . . . 8
oprx3,+xys Preincrement X or Y or SP by 1 . . . 8
oprx3,xys Postdecrement X or Y or SP by 1 . . . 8
oprx3,xys+ Postincrement X or Y or SP by 1 . . . 8
oprx5,xysp 5-bit constant offset from X or Y or SP or PC
abd,xysp Accumulator A or B or D offset from X or Y or SP or PC
oprx3 Any positive integer 1 . . . 8 for pre/post increment/decrement
oprx5 Any integer in the range 16 . . . +15
oprx9 Any integer in the range 256 . . . +255
oprx16 Any integer in the range 32,768 . . . 65,535
page 8-bit value for PPAGE, some assemblers require # symbol before this value
rel8 Label of branch destination within 256 to +255 locations
rel9 Label of branch destination within 512 to +511 locations
rel16 Any label within 64K memory space
trapnum Any 8-bit integer in the range $30-$39 or $40-$FF
xys X or Y or SP
xysp X or Y or SP or PC
Operators
+ Addition

Subtraction

Logical AND

Logical OR (inclusive)

Logical exclusive OR

Multiplication

Division

Negation. Ones complement (invert each bit of M)

Concatenate
Example: A : B means the 16-bit value formed by concatenating 8-bit accumulator A
with 8-bit accumulator B.
A is in the high-order position.
Continued on next page

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

CPU12RG/D

Operators (continued)
Transfer
Example: (A) M means the content of accumulator A is transferred to memory
location M.
Exchange
Example: D X means exchange the contents of D with those of X.
Address Mode Notation
INH Inherent; no operands in object code
IMM Immediate; operand in object code
DIR Direct; operand is the lower byte of an address from $0000 to $00FF
EXT Operand is a 16-bit address
REL Twos complement relative offset; for branch instructions
IDX Indexed (no extension bytes); includes:
5-bit constant offset from X, Y, SP, or PC
Pre/post increment/decrement by 1 . . . 8
Accumulator A, B, or D offset
IDX1 9-bit signed offset from X, Y, SP, or PC; 1 extension byte
IDX2 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes
[IDX2] Indexed-indirect; 16-bit offset from X, Y, SP, or PC
[D, IDX] Indexed-indirect; accumulator D offset from X, Y, SP, or PC

Machine Coding
dd 8-bit direct address $0000 to $00FF. (High byte assumed to be $00).
ee High-order byte of a 16-bit constant offset for indexed addressing.
eb Exchange/Transfer post-byte. See Table 3 on page 22.
ff Low-order eight bits of a 9-bit signed constant offset for indexed addressing,
or low-order byte of a 16-bit constant offset for indexed addressing.
hh High-order byte of a 16-bit extended address.
ii 8-bit immediate data value.
jj High-order byte of a 16-bit immediate data value.
kk Low-order byte of a 16-bit immediate data value.
lb Loop primitive (DBNE) post-byte. See Table 4 on page 23.
ll Low-order byte of a 16-bit extended address.
mm 8-bit immediate mask value for bit manipulation instructions.
Set bits indicate bits to be affected.
pg Program page (bank) number used in CALL instruction.
qq High-order byte of a 16-bit relative offset for long branches.
tn Trap number $30$39 or $40$FF.
rr Signed relative offset $80 (128) to $7F (+127).
Offset relative to the byte following the relative offset byte, or
low-order byte of a 16-bit relative offset for long branches.
xb Indexed addressing post-byte. See Table 1 on page 20
and Table 2 on page 21.

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Access Detail

Each code letter except (,), and comma equals one CPU cycle.
Uppercase = 16-bit operation and lowercase = 8-bit operation. For
complex sequences see the CPU12 Reference Manual
(CPU12RM/AD) for more detailed information.
f
g
I
i
n
O

P
r
R
s
S
w
W
u
U
V
t
T
x
()
,

Free cycle, CPU doesnt use bus

Read PPAGE internally
Read indirect pointer (indexed indirect)
Read indirect PPAGE value (CALL indirect only)
Write PPAGE internally
Optional program word fetch (P) if instruction is misaligned and has
an odd number of bytes of object code otherwise, appears as
a free cycle (f); Page 2 prebyte treated as a separate 1-byte instruction
Program word fetch (always an aligned-word read)
8-bit data read
16-bit data read
8-bit stack write
16-bit stack write
8-bit data write
16-bit data write
8-bit stack read
16-bit stack read
16-bit vector fetch (always an aligned-word read)
8-bit conditional read (or free cycle)
16-bit conditional read (or free cycle)
8-bit conditional write (or free cycle)
Indicate a microcode loop
Indicates where an interrupt could be honored
Special Cases

PPP/P Short branch, PPP if branch taken, P if not

OPPP/OPO Long branch, OPPP if branch taken, OPO if not
Condition Codes Columns
Status bit not affected by operation.
0 Status bit cleared by operation.
1 Status bit set by operation.
Status bit affected by operation.
? Status bit may be cleared or remain set, but is not set by operation.
Status bit may be set or remain cleared, but is not cleared by operation.
? Status bit may be changed by operation but the final state is not defined.
! Status bit used for a special purpose.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

CPU12RG/D

Instruction Set Summary (Sheet 1 of 14)

Source Form

Operation

Addr.
Mode

Machine
Coding (hex)

Access Detail
HCS12

HC12

SXHI

NZVC

ABA

(A) + (B) A
Add Accumulators A and B

INH

18 06

OO

ABX

(B) + (X) X
Translates to LEAX B,X

IDX

1A E5

Pf

PP1

ABY

(B) + (Y) Y
Translates to LEAY B,Y

IDX

19 ED

Pf

PP1

ADCA #opr8i
ADCA opr8a
ADCA opr16a
ADCA oprx0_xysp
ADCA oprx9,xysp
ADCA oprx16,xysp
ADCA [D,xysp]
ADCA [oprx16,xysp]

(A) + (M) + C A
Add with Carry to A

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

89
99
B9
A9
A9
A9
A9
A9

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
flPrfP
fIPrfP

ADCB #opr8i
ADCB opr8a
ADCB opr16a
ADCB oprx0_xysp
ADCB oprx9,xysp
ADCB oprx16,xysp
ADCB [D,xysp]
ADCB [oprx16,xysp]

(B) + (M) + C B
Add with Carry to B

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C9
D9
F9
E9
E9
E9
E9
E9

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

ADDA #opr8i
ADDA opr8a
ADDA opr16a
ADDA oprx0_xysp
ADDA oprx9,xysp
ADDA oprx16,xysp
ADDA [D,xysp]
ADDA [oprx16,xysp]

(A) + (M) A
Add without Carry to A

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

8B
9B
BB
AB
AB
AB
AB
AB

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

ADDB #opr8i
ADDB opr8a
ADDB opr16a
ADDB oprx0_xysp
ADDB oprx9,xysp
ADDB oprx16,xysp
ADDB [D,xysp]
ADDB [oprx16,xysp]

(B) + (M) B
Add without Carry to B

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

CB
DB
FB
EB
EB
EB
EB
EB

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

ADDD #opr16i
ADDD opr8a
ADDD opr16a
ADDD oprx0_xysp
ADDD oprx9,xysp
ADDD oprx16,xysp
ADDD [D,xysp]
ADDD [oprx16,xysp]

(A:B) + (M:M+1) A:B

Add 16-Bit to D (A:B)

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C3
D3
F3
E3
E3
E3
E3
E3

jj
dd
hh
xb
xb
xb
xb
xb

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

ANDA #opr8i
ANDA opr8a
ANDA opr16a
ANDA oprx0_xysp
ANDA oprx9,xysp
ANDA oprx16,xysp
ANDA [D,xysp]
ANDA [oprx16,xysp]

(A) (M) A
Logical AND A with Memory

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

84
94
B4
A4
A4
A4
A4
A4

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

ANDB #opr8i
ANDB opr8a
ANDB opr16a
ANDB oprx0_xysp
ANDB oprx9,xysp
ANDB oprx16,xysp
ANDB [D,xysp]
ANDB [oprx16,xysp]

(B) (M) B
Logical AND B with Memory

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C4
D4
F4
E4
E4
E4
E4
E4

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

ANDCC #opr8i

(CCR) (M) CCR

Logical AND CCR with Memory

IMM

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff
kk
ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

10 ii

OO

Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 2 of 14)

Source Form
ASL opr16a
ASL oprx0_xysp
ASL oprx9,xysp
ASL oprx16,xysp
ASL [D,xysp]
ASL [oprx16,xysp]
ASLA
ASLB

Addr.
Mode

Operation

0
b7
C
Arithmetic Shift Left

b0

Arithmetic Shift Left Accumulator A

Arithmetic Shift Left Accumulator B

ASLD

Machine
Coding (hex)

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

78
68
68
68
68
68
48
58

INH

59

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

77
67
67
67
67
67
47
57

hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

Access Detail

SXHI

NZVC

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

PPP/P1

PPP/P1

rPwO
rPwP
rPwO
rPwP
frPwPO

rPOw
rPPw
rPOw
rPwP
frPwOP

HCS12
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O

HC12

0
C
b7 A b0 b7
Arithmetic Shift Left Double

b0

ASR opr16a
ASR oprx0_xysp
ASR oprx9,xysp
ASR oprx16,xysp
ASR [D,xysp]
ASR [oprx16,xysp]
ASRA
ASRB

b7
Arithmetic Shift Right

BCC rel8

Branch if Carry Clear (if C = 0)

REL

24 rr

(M) (mm) M
Clear Bit(s) in Memory

DIR
EXT
IDX
IDX1
IDX2

4D
1D
0D
0D
0D

BCLR opr8a, msk8

BCLR opr16a, msk8
BCLR oprx0_xysp, msk8
BCLR oprx9,xysp, msk8
BCLR oprx16,xysp, msk8

b0

Arithmetic Shift Right Accumulator A

Arithmetic Shift Right Accumulator B

hh
xb
xb
xb
xb
xb

dd
hh
xb
xb
xb

ll
ff
ee ff
ee ff

mm
ll mm
mm
ff mm
ee ff mm

BCS rel8

Branch if Carry Set (if C = 1)

REL

25 rr

PPP/P1

PPP/P1

BEQ rel8

Branch if Equal (if Z = 1)

REL

27 rr

PPP/P1

PPP/P1

BGE rel8

Branch if Greater Than or Equal

(if N V = 0) (signed)

REL

2C rr

PPP/P1

PPP/P1

BGND

Place CPU in Background Mode

see CPU12 Reference Manual

INH

00

VfPPP

VfPPP

BGT rel8

Branch if Greater Than

(if Z + (N V) = 0) (signed)

REL

2E rr

PPP/P1

PPP/P1

BHI rel8

Branch if Higher
(if C + Z = 0) (unsigned)

REL

22 rr

PPP/P1

PPP/P1

BHS rel8

Branch if Higher or Same

(if C = 0) (unsigned)
same function as BCC

REL

24 rr

PPP/P1

PPP/P1

BITA #opr8i
BITA opr8a
BITA opr16a
BITA oprx0_xysp
BITA oprx9,xysp
BITA oprx16,xysp
BITA [D,xysp]
BITA [oprx16,xysp]

(A) (M)
Logical AND A with Memory
Does not change Accumulator or Memory

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

85
95
B5
A5
A5
A5
A5
A5

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

BITB #opr8i
BITB opr8a
BITB opr16a
BITB oprx0_xysp
BITB oprx9,xysp
BITB oprx16,xysp
BITB [D,xysp]
BITB [oprx16,xysp]

(B) (M)
Logical AND B with Memory
Does not change Accumulator or Memory

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C5
D5
F5
E5
E5
E5
E5
E5

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

BLE rel8

Branch if Less Than or Equal

(if Z + (N V) = 1) (signed)

REL

2F rr

PPP/P1

PPP/P1

BLO rel8

Branch if Lower
(if C = 1) (unsigned)
same function as BCS

REL

25 rr

PPP/P1

PPP/P1

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

CPU12RG/D

Instruction Set Summary (Sheet 3 of 14)

Source Form

Operation

Addr.
Mode

Machine
Coding (hex)

Access Detail
HCS12

SXHI

NZVC

HC12
1

BLS rel8

Branch if Lower or Same

(if C + Z = 1) (unsigned)

REL

23 rr

PPP/P

PPP/P

BLT rel8

Branch if Less Than

(if N V = 1) (signed)

REL

2D rr

PPP/P1

PPP/P1

BMI rel8

Branch if Minus (if N = 1)

REL

2B rr

PPP/P1

PPP/P1

BNE rel8

Branch if Not Equal (if Z = 0)

REL

26 rr

PPP/P

PPP/P1

BPL rel8

Branch if Plus (if N = 0)

REL

2A rr

PPP/P1

PPP/P1

BRA rel8

Branch Always (if 1 = 1)

REL

20 rr

PPP

PPP

BRCLR opr8a, msk8, rel8

Branch if (M) (mm) = 0
BRCLR opr16a, msk8, rel8
(if All Selected Bit(s) Clear)
BRCLR oprx0_xysp, msk8, rel8
BRCLR oprx9,xysp, msk8, rel8
BRCLR oprx16,xysp, msk8, rel8

DIR
EXT
IDX
IDX1
IDX2

4F
1F
0F
0F
0F

rPPP
rfPPP
rPPP
rffPPP
frPffPPP

BRN rel8

REL

21 rr

DIR
EXT
IDX
IDX1
IDX2

4E
1E
0E
0E
0E

dd
hh
xb
xb
xb

DIR
EXT
IDX
IDX1
IDX2

4C
1C
0C
0C
0C

dd mm
hh ll mm
xb mm
xb ff mm
xb ee ff mm

Branch Never (if 1 = 0)

BRSET opr8, msk8, rel8

Branch if (M) (mm) = 0
BRSET opr16a, msk8, rel8
(if All Selected Bit(s) Set)
BRSET oprx0_xysp, msk8, rel8
BRSET oprx9,xysp, msk8, rel8
BRSET oprx16,xysp, msk8, rel8
BSET opr8, msk8
BSET opr16a, msk8
BSET oprx0_xysp, msk8
BSET oprx9,xysp, msk8
BSET oprx16,xysp, msk8

(M) + (mm) M
Set Bit(s) in Memory

dd
hh
xb
xb
xb

mm
ll
mm
ff
ee

rr
mm rr
rr
mm rr
ff mm rr

rPPP
rfPPP
rPPP
rfPPP
PrfPPP

mm
ll
mm
ff
ee

rr
mm rr
rr
mm rr
ff mm rr

rPPP
rfPPP
rPPP
rfPPP
PrfPPP

rPPP
rfPPP
rPPP
rffPPP
frPffPPP

rPwO
rPwP
rPwO
rPwP
frPwPO

rPOw
rPPw
rPOw
rPwP
frPwOP

PPPS

BSR rel8

(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1)

Subroutine address PC
Branch to Subroutine

REL

07 rr

SPPP

BVC rel8

Branch if Overflow Bit Clear (if V = 0)

REL

28 rr

PPP/P1

PPP/P1

BVS rel8

Branch if Overflow Bit Set (if V = 1)

REL

29 rr

PPP/P1

PPP/P1

CALL opr16a, page

CALL oprx0_xysp, page
CALL oprx9,xysp, page
CALL oprx16,xysp, page
CALL [D,xysp]
CALL [oprx16, xysp]

(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1)

(SP) 1 SP; (PPG) M(SP);
pg PPAGE register; Program address PC

gnfSsPPP
gnfSsPPP
gnfSsPPP
fgnfSsPPP
fIignSsPPP
fIignSsPPP

OO

Call subroutine in extended memory

(Program may be located on another
expansion memory page.)

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

4A
4B
4B
4B
4B
4B

hh
xb
xb
xb
xb
xb

ll pg
pg
ff pg
ee ff pg
ee ff

gnSsPPP
gnSsPPP
gnSsPPP
fgnSsPPP
fIignSsPPP
fIignSsPPP

Indirect modes get program address

and new pg value based on pointer.
CBA

(A) (B)
Compare 8-Bit Accumulators

INH

18 17

OO

CLC

0C
Translates to ANDCC #$FE

IMM

10 FE

CLI

0I
Translates to ANDCC #$EF
(enables I-bit interrupts)

IMM

10 EF

P 0

CLR opr16a
CLR oprx0_xysp
CLR oprx9,xysp
CLR oprx16,xysp
CLR [D,xysp]
CLR [oprx16,xysp]
CLRA
CLRB

0M

wOP
Pw
PwO
PwP
PIfPw
PIPPw
O
O

0100

CLV

0V
Translates to ANDCC #$FD

0A
0B

Clear Memory Location

Clear Accumulator A
Clear Accumulator B

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
IMM

79
69
69
69
69
69
87
C7

hh
xb
xb
xb
xb
xb

10 FD

ll
ff
ee ff
ee ff

PwO
Pw
PwO
PwP
PIfw
PIPw
O
O
P

Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 4 of 14)

Source Form

Operation

CMPA #opr8i
CMPA opr8a
CMPA opr16a
CMPA oprx0_xysp
CMPA oprx9,xysp
CMPA oprx16,xysp
CMPA [D,xysp]
CMPA [oprx16,xysp]

(A) (M)
Compare Accumulator A with Memory

CMPB #opr8i
CMPB opr8a
CMPB opr16a
CMPB oprx0_xysp
CMPB oprx9,xysp
CMPB oprx16,xysp
CMPB [D,xysp]
CMPB [oprx16,xysp]

(B) (M)
Compare Accumulator B with Memory

COM opr16a
COM oprx0_xysp
COM oprx9,xysp
COM oprx16,xysp
COM [D,xysp]
COM [oprx16,xysp]
COMA
COMB

(M) M equivalent to $FF (M) M

1s Complement Memory Location

(A) A

Complement Accumulator A

(B) B

Complement Accumulator B

CPD #opr16i
CPD opr8a
CPD opr16a
CPD oprx0_xysp
CPD oprx9,xysp
CPD oprx16,xysp
CPD [D,xysp]
CPD [oprx16,xysp]

(A:B) (M:M+1)
Compare D to Memory (16-Bit)

CPS #opr16i
CPS opr8a
CPS opr16a
CPS oprx0_xysp
CPS oprx9,xysp
CPS oprx16,xysp
CPS [D,xysp]
CPS [oprx16,xysp]

(SP) (M:M+1)
Compare SP to Memory (16-Bit)

CPX #opr16i
CPX opr8a
CPX opr16a
CPX oprx0_xysp
CPX oprx9,xysp
CPX oprx16,xysp
CPX [D,xysp]
CPX [oprx16,xysp]

(X) (M:M+1)
Compare X to Memory (16-Bit)

CPY #opr16i
CPY opr8a
CPY opr16a
CPY oprx0_xysp
CPY oprx9,xysp
CPY oprx16,xysp
CPY [D,xysp]
CPY [oprx16,xysp]

(Y) (M:M+1)
Compare Y to Memory (16-Bit)

DAA

Adjust Sum to BCD

Decimal Adjust Accumulator A

DBEQ abdxys, rel9

(cntr) 1 cntr
if (cntr) = 0, then Branch
else Continue to next instruction

Addr.
Mode

Machine
Coding (hex)

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

81
91
B1
A1
A1
A1
A1
A1

ii
dd
hh
xb
xb
xb
xb
xb

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C1
D1
F1
E1
E1
E1
E1
E1

ii
dd
hh
xb
xb
xb
xb
xb

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

71
61
61
61
61
61
41
51

hh
xb
xb
xb
xb
xb

ll

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

8C
9C
BC
AC
AC
AC
AC
AC

jj
dd
hh
xb
xb
xb
xb
xb

kk

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

8F
9F
BF
AF
AF
AF
AF
AF

jj
dd
hh
xb
xb
xb
xb
xb

kk

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

8E
9E
BE
AE
AE
AE
AE
AE

jj
dd
hh
xb
xb
xb
xb
xb

kk

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

8D
9D
BD
AD
AD
AD
AD
AD

jj
dd
hh
xb
xb
xb
xb
xb

kk

INH
REL
(9-bit)

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

Access Detail

SXHI

NZVC

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

01

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

HCS12

HC12

18 07

OfO

OfO

04 lb rr

PPP (branch)
PPO (no branch)

PPP

Decrement Counter and Branch if = 0

(cntr = A, B, D, X, Y, or SP)

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

CPU12RG/D

Instruction Set Summary (Sheet 5 of 14)

Source Form
DBNE abdxys, rel9

Operation
(cntr) 1 cntr
If (cntr) not = 0, then Branch;
else Continue to next instruction

Addr.
Mode

Machine
Coding (hex)

Access Detail
HCS12

REL
(9-bit)

04 lb rr

PPP (branch)
PPO (no branch)

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

73
63
63
63
63
63
43
53

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

HC12
PPP

SXHI

NZVC

Decrement Counter and Branch if 0

(cntr = A, B, D, X, Y, or SP)

DEC opr16a
DEC oprx0_xysp
DEC oprx9,xysp
DEC oprx16,xysp
DEC [D,xysp]
DEC [oprx16,xysp]
DECA
DECB

(M) $01 M
Decrement Memory Location

DES

(SP) $0001 SP
Translates to LEAS 1,SP

IDX

1B 9F

Pf

DEX

(X) $0001 X
Decrement Index Register X

INH

09

DEY

(Y) $0001 Y
Decrement Index Register Y

INH

03

EDIV

(Y:D) (X) Y Remainder D

32 by 16 Bit 16 Bit Divide (unsigned)

INH

11

ffffffffffO

ffffffffffO

EDIVS

(Y:D) (X) Y Remainder D

32 by 16 Bit 16 Bit Divide (signed)

INH

18 14

OffffffffffO

OffffffffffO

EMACS opr16a 2

(M(X):M(X+1)) (M(Y):M(Y+1)) + (M~M+3) M~M+3

Special

18 12 hh ll

ORROfffRRfWWP

ORROfffRRfWWP

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

1A
1A
1A
1A
1A

xb
xb ff
xb ee ff
xb
xb ee ff

ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf

ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

1E
1E
1E
1E
1E

xb
xb ff
xb ee ff
xb
xb ee ff

ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW

ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

1B
1B
1B
1B
1B

xb
xb ff
xb ee ff
xb
xb ee ff

ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf

ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

1F
1F
1F
1F
1F

xb
xb ff
xb ee ff
xb
xb ee ff

ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW

ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW

(A) $01 A
(B) $01 B

Decrement A
Decrement B

hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
PP1

16 by 16 Bit 32 Bit
Multiply and Accumulate (signed)
EMAXD oprx0_xysp
EMAXD oprx9,xysp
EMAXD oprx16,xysp
EMAXD [D,xysp]
EMAXD [oprx16,xysp]

MAX((D), (M:M+1)) D
MAX of 2 Unsigned 16-Bit Values

EMAXM oprx0_xysp
EMAXM oprx9,xysp
EMAXM oprx16,xysp
EMAXM [D,xysp]
EMAXM [oprx16,xysp]

MAX((D), (M:M+1)) M:M+1

MAX of 2 Unsigned 16-Bit Values

EMIND oprx0_xysp
EMIND oprx9,xysp
EMIND oprx16,xysp
EMIND [D,xysp]
EMIND [oprx16,xysp]

MIN((D), (M:M+1)) D
MIN of 2 Unsigned 16-Bit Values

EMINM oprx0_xysp
EMINM oprx9,xysp
EMINM oprx16,xysp
EMINM [D,xysp]
EMINM [oprx16,xysp]

MIN((D), (M:M+1)) M:M+1

MIN of 2 Unsigned 16-Bit Values

EMUL

(D) (Y) Y:D

16 by 16 Bit Multiply (unsigned)

INH

13

ffO

ffO

EMULS

(D) (Y) Y:D

16 by 16 Bit Multiply (signed)

INH

18 13

OfO

OfO

(A) (M) A
Exclusive-OR A with Memory

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

EORA #opr8i
EORA opr8a
EORA opr16a
EORA oprx0_xysp
EORA oprx9,xysp
EORA oprx16,xysp
EORA [D,xysp]
EORA [oprx16,xysp]

N, Z, V and C status bits reflect result of

internal compare ((D) (M:M+1))

N, Z, V and C status bits reflect result of

internal compare ((D) (M:M+1))

N, Z, V and C status bits reflect result of

internal compare ((D) (M:M+1))

N, Z, V and C status bits reflect result of

internal compare ((D) (M:M+1))

(if followed by page 2 instruction)

OffO
OfO
88
98
B8
A8
A8
A8
A8
A8

ii
dd
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

Notes:
1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
2. opr16a is an extended address specification. Both X and Y point to source operands.

10

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 6 of 14)

Source Form

Operation

EORB #opr8i
EORB opr8a
EORB opr16a
EORB oprx0_xysp
EORB oprx9,xysp
EORB oprx16,xysp
EORB [D,xysp]
EORB [oprx16,xysp]

(B) (M) B
Exclusive-OR B with Memory

ETBL oprx0_xysp

(M:M+1)+ [(B)((M+2:M+3) (M:M+1))] D

16-Bit Table Lookup and Interpolate

Addr.
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IDX

Machine
Coding (hex)
C8
D8
F8
E8
E8
E8
E8
E8

ii
dd
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

18 3F xb

Access Detail
HCS12
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
ORRffffffP

SXHI

NZVC

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

HC12

ORRffffffP

C Bit is undefined
in HC12

Initialize B, and index before ETBL.

<ea> points at first table entry (M:M+1)
and B is fractional part of lookup value
(no indirect addr. modes or extensions allowed)
EXG abcdxys,abcdxys

(r1) (r2) (if r1 and r2 same size) or

$00:(r1) r2 (if r1=8-bit; r2=16-bit) or
(r1low) (r2) (if r1=16-bit; r2=8-bit)

INH

B7 eb

18 11

OffffffffffO

OffffffffffO

r1 and r2 may be
A, B, CCR, D, X, Y, or SP
FDIV

(D) (X) X; Remainder D

16 by 16 Bit Fractional Divide

INH

IBEQ abdxys, rel9

(cntr) + 1 cntr
If (cntr) = 0, then Branch
else Continue to next instruction

REL
(9-bit)

04 lb rr

PPP (branch)
PPO (no branch)

PPP

REL
(9-bit)

04 lb rr

PPP (branch)
PPO (no branch)

PPP

Increment Counter and Branch if = 0

(cntr = A, B, D, X, Y, or SP)
IBNE abdxys, rel9

(cntr) + 1 cntr
if (cntr) not = 0, then Branch;
else Continue to next instruction
Increment Counter and Branch if 0
(cntr = A, B, D, X, Y, or SP)

IDIV

(D) (X) X; Remainder D

16 by 16 Bit Integer Divide (unsigned)

INH

18 10

OffffffffffO

OffffffffffO

IDIVS

(D) (X) X; Remainder D

16 by 16 Bit Integer Divide (signed)

INH

18 15

OffffffffffO

OffffffffffO

INC opr16a
INC oprx0_xysp
INC oprx9,xysp
INC oprx16,xysp
INC [D,xysp]
INC [oprx16,xysp]
INCA
INCB

(M) + $01 M
Increment Memory Byte

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

INS

(SP) + $0001 SP
Translates to LEAS 1,SP

IDX

1B 81

Pf

INX

(X) + $0001 X
Increment Index Register X

INH

08

INY

(Y) + $0001 Y
Increment Index Register Y

INH

02

JMP opr16a
JMP oprx0_xysp
JMP oprx9,xysp
JMP oprx16,xysp
JMP [D,xysp]
JMP [oprx16,xysp]

Routine address PC

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

06
05
05
05
05
05

(A) + $01 A
(B) + $01 B

Jump

Increment Acc. A
Increment Acc. B

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

72
62
62
62
62
62
42
52

hh
xb
xb
xb
xb
xb

hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

PP1

PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP

PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP

Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

11

CPU12RG/D

Instruction Set Summary (Sheet 7 of 14)

Source Form

Operation

JSR opr8a
JSR opr16a
JSR oprx0_xysp
JSR oprx9,xysp
JSR oprx16,xysp
JSR [D,xysp]
JSR [oprx16,xysp]

(SP) 2 SP;
RTNH:RTNL M(SP):M(SP+1);
Subroutine address PC

LBCC rel16

Long Branch if Carry Clear (if C = 0)

Jump to Subroutine

Addr.
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
REL

Machine
Coding (hex)
17
16
15
15
15
15
15

dd
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

Access Detail
HCS12

SXHI

NZVC

PPPS
PPPS
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS

HC12

SPPP
SPPP
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS

18 24 qq rr

OPPP/OPO1

OPPP/OPO1

LBCS rel16

Long Branch if Carry Set (if C = 1)

REL

18 25 qq rr

OPPP/OPO

OPPP/OPO1

LBEQ rel16

Long Branch if Equal (if Z = 1)

REL

18 27 qq rr

OPPP/OPO1

OPPP/OPO1

LBGE rel16

Long Branch Greater Than or Equal

(if N V = 0) (signed)

REL

18 2C qq rr

OPPP/OPO1

OPPP/OPO1

LBGT rel16

Long Branch if Greater Than

(if Z + (N V) = 0) (signed)

REL

18 2E qq rr

OPPP/OPO1

OPPP/OPO1

LBHI rel16

Long Branch if Higher

(if C + Z = 0) (unsigned)

REL

18 22 qq rr

OPPP/OPO1

OPPP/OPO1

LBHS rel16

Long Branch if Higher or Same

(if C = 0) (unsigned)
same function as LBCC

REL

18 24 qq rr

OPPP/OPO1

OPPP/OPO1

LBLE rel16

Long Branch if Less Than or Equal

(if Z + (N V) = 1) (signed)

REL

18 2F qq rr

OPPP/OPO1

OPPP/OPO1

LBLO rel16

Long Branch if Lower

(if C = 1) (unsigned)
same function as LBCS

REL

18 25 qq rr

OPPP/OPO1

OPPP/OPO1

LBLS rel16

Long Branch if Lower or Same

(if C + Z = 1) (unsigned)

REL

18 23 qq rr

OPPP/OPO1

OPPP/OPO1

LBLT rel16

Long Branch if Less Than

(if N V = 1) (signed)

REL

18 2D qq rr

OPPP/OPO1

OPPP/OPO1

LBMI rel16

Long Branch if Minus (if N = 1)

REL

18 2B qq rr

OPPP/OPO1

OPPP/OPO1

LBNE rel16

Long Branch if Not Equal (if Z = 0)

REL

18 26 qq rr

OPPP/OPO1

OPPP/OPO1

LBPL rel16

Long Branch if Plus (if N = 0)

REL

18 2A qq rr

OPPP/OPO1

OPPP/OPO1

LBRA rel16

Long Branch Always (if 1=1)

REL

18 20 qq rr

OPPP

OPPP

LBRN rel16

Long Branch Never (if 1 = 0)

REL

18 21 qq rr

OPO

OPO

LBVC rel16

Long Branch if Overflow Bit Clear (if V=0)

REL

18 28 qq rr

OPPP/OPO1

OPPP/OPO1

LBVS rel16

Long Branch if Overflow Bit Set (if V = 1)

REL

18 29 qq rr

OPPP/OPO1

OPPP/OPO1

LDAA #opr8i
LDAA opr8a
LDAA opr16a
LDAA oprx0_xysp
LDAA oprx9,xysp
LDAA oprx16,xysp
LDAA [D,xysp]
LDAA [oprx16,xysp]

(M) A
Load Accumulator A

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

86
96
B6
A6
A6
A6
A6
A6

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

LDAB #opr8i
LDAB opr8a
LDAB opr16a
LDAB oprx0_xysp
LDAB oprx9,xysp
LDAB oprx16,xysp
LDAB [D,xysp]
LDAB [oprx16,xysp]

(M) B
Load Accumulator B

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C6
D6
F6
E6
E6
E6
E6
E6

ii
dd
hh
xb
xb
xb
xb
xb

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

LDD #opr16i
LDD opr8a
LDD opr16a
LDD oprx0_xysp
LDD oprx9,xysp
LDD oprx16,xysp
LDD [D,xysp]
LDD [oprx16,xysp]

(M:M+1) A:B
Load Double Accumulator D (A:B)

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

CC
DC
FC
EC
EC
EC
EC
EC

jj
dd
hh
xb
xb
xb
xb
xb

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff
kk
ll
ff
ee ff
ee ff

Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.

12

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 8 of 14)

Source Form

Addr.
Mode

Operation

Machine
Coding (hex)

Access Detail

SXHI

NZVC

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

HCS12

HC12

LDS #opr16i
LDS opr8a
LDS opr16a
LDS oprx0_xysp
LDS oprx9,xysp
LDS oprx16,xysp
LDS [D,xysp]
LDS [oprx16,xysp]

(M:M+1) SP
Load Stack Pointer

LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]

(M:M+1) X
Load Index Register X

LDY #opr16i
LDY opr8a
LDY opr16a
LDY oprx0_xysp
LDY oprx9,xysp
LDY oprx16,xysp
LDY [D,xysp]
LDY [oprx16,xysp]

(M:M+1) Y
Load Index Register Y

LEAS oprx0_xysp
LEAS oprx9,xysp
LEAS oprx16,xysp

Effective Address SP
Load Effective Address into SP

IDX
IDX1
IDX2

1B xb
1B xb ff
1B xb ee ff

Pf
PO
PP

PP1
PO
PP

LEAX oprx0_xysp
LEAX oprx9,xysp
LEAX oprx16,xysp

Effective Address X
Load Effective Address into X

IDX
IDX1
IDX2

1A xb
1A xb ff
1A xb ee ff

Pf
PO
PP

PP1
PO
PP

LEAY oprx0_xysp
LEAY oprx9,xysp
LEAY oprx16,xysp

Effective Address Y
Load Effective Address into Y

IDX
IDX1
IDX2

19 xb
19 xb ff
19 xb ee ff

Pf
PO
PP

PP1
PO
PP

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

78
68
68
68
68
68
48
58

rPwO
rPw
rPwO
frPPw
fIfrPw
fIPrPw
O
O

INH

59

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

74
64
64
64
64
64
44
54

INH

49

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

LSL opr16a
LSL oprx0_xysp
LSL oprx9,xysp
LSL oprx16,xysp
LSL [D,xysp]
LSL [oprx16,xysp]
LSLA
LSLB

0
b7
C
Logical Shift Left
same function as ASL

b0

Logical Shift Accumulator A to Left

Logical Shift Accumulator B to Left

LSLD

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

CF
DF
FF
EF
EF
EF
EF
EF

jj
dd
hh
xb
xb
xb
xb
xb

kk

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

CE
DE
FE
EE
EE
EE
EE
EE

jj
dd
hh
xb
xb
xb
xb
xb

kk

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

CD
DD
FD
ED
ED
ED
ED
ED

jj
dd
hh
xb
xb
xb
xb
xb

kk

hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP

0
b0
b7 A
b7
B
C
Logical Shift Left D Accumulator
same function as ASLD
LSR opr16a
LSR oprx0_xysp
LSR oprx9,xysp
LSR oprx16,xysp
LSR [D,xysp]
LSR [oprx16,xysp]
LSRA
LSRB

b0

0
b7
Logical Shift Right

b0

Logical Shift Accumulator A to Right

Logical Shift Accumulator B to Right

LSRD

hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O

0
b0
b7
A
b7
B
Logical Shift Right D Accumulator
MAXA oprx0_xysp
MAXA oprx9,xysp
MAXA oprx16,xysp
MAXA [D,xysp]
MAXA [oprx16,xysp]

MAX((A), (M)) A
MAX of 2 Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) (M)).

b0

C
18
18
18
18
18

xb
xb ff
xb ee ff
xb
xb ee ff

OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf

Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

13

CPU12RG/D

Instruction Set Summary (Sheet 9 of 14)

Source Form

Operation

MAXM oprx0_xysp
MAXM oprx9,xysp
MAXM oprx16,xysp
MAXM [D,xysp]
MAXM [oprx16,xysp]

MAX((A), (M)) M
MAX of 2 Unsigned 8-Bit Values

MEM

(grade) M(Y);
(X) + 4 X; (Y) + 1 Y; A unchanged

Addr.
Mode

Machine
Coding (hex)

Access Detail
HCS12

SXHI

NZVC

OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw

HC12

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

Special

01

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

19
19
19
19
19

xb
xb ff
xb ee ff
xb
xb ee ff

OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf

OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP

IDX
IDX1
IDX2
[D,IDX]
[IDX2]

18
18
18
18
18

1D
1D
1D
1D
1D

xb
xb ff
xb ee ff
xb
xb ee ff

OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw

OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw

MOVB #opr8, opr16a1

(M1) M2
MOVB #opr8i, oprx0_xysp1
Memory to Memory Byte-Move (8-Bit)
1
MOVB opr16a, opr16a
1
MOVB opr16a, oprx0_xysp
MOVB oprx0_xysp, opr16a1
MOVB oprx0_xysp, oprx0_xysp1

IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX

18
18
18
18
18
18

0B
08
0C
09
0D
0A

ii
xb
hh
xb
xb
xb

hh
ii
ll
hh
hh
xb

ll

OPwP
OPwO
hh ll OrPwPO
ll
OPrPw
ll
OrPwP
OrPwO

OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO

MOVW #oprx16, opr16a1

(M:M+11) M:M+12
MOVW #opr16i, oprx0_xysp1
Memory to Memory Word-Move (16-Bit)
MOVW opr16a, opr16a1
MOVW opr16a, oprx0_xysp1
MOVW oprx0_xysp, opr16a1
MOVW oprx0_xysp, oprx0_xysp1

IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX

18
18
18
18
18
18

03
00
04
01
05
02

jj
xb
hh
xb
xb
xb

kk
jj
ll
hh
hh
xb

hh ll OPWPO
kk
OPPW
hh ll ORPWPO
ll
OPRPW
ll
ORPWP
ORPWO

OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO

INH

12

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH

70
60
60
60
60
60
40

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O

INH

50

INH

A7

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

8A
9A
BA
AA
AA
AA
AA
AA

N, Z, V and C status bits reflect result of

internal compare ((A) (M)).

1C
1C
1C
1C
1C

xb
xb ff
xb ee ff
xb
xb ee ff

OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
RRfOw

RRfOw

????

if (A) < P1 or (A) > P2 then = 0, else

= MIN[((A) P1)S1, (P2 (A))S2, $FF]
where:
A = current crisp input value;
X points at 4-byte data structure that describes a trapezoidal
membership function (P1, P2, S1, S2);
Y points at fuzzy input (RAM location).
See CPU12 Reference Manual for special cases.
MINA oprx0_xysp
MINA oprx9,xysp
MINA oprx16,xysp
MINA [D,xysp]
MINA [oprx16,xysp]

MIN((A), (M)) A
MIN of 2 Unsigned 8-Bit Values

MINM oprx0_xysp
MINM oprx9,xysp
MINM oprx16,xysp
MINM [D,xysp]
MINM [oprx16,xysp]

MIN((A), (M)) M
MIN of 2 Unsigned 8-Bit Values

N, Z, V and C status bits reflect result of

internal compare ((A) (M)).

N, Z, V and C status bits reflect result of

internal compare ((A) (M)).

MUL

(A) (B) A:B

8 by 8 Unsigned Multiply

NEG opr16a
NEG oprx0_xysp
NEG oprx9,xysp
NEG oprx16,xysp
NEG [D,xysp]
NEG [oprx16,xysp]
NEGA

0 (M) M equivalent to (M) + 1 M

Twos Complement Negate

NEGB
NOP
ORAA #opr8i
ORAA opr8a
ORAA opr16a
ORAA oprx0_xysp
ORAA oprx9,xysp
ORAA oprx16,xysp
ORAA [D,xysp]
ORAA [oprx16,xysp]

0 (A) A equivalent to (A) + 1 A

Negate Accumulator A
0 (B) B equivalent to (B) + 1 B
Negate Accumulator B
No Operation

(A) + (M) A
Logical OR A with Memory

O
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

O
ii
dd
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

ffO

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

Note 1. The first operand in the source code statement specifies the source for the move.

14

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 10 of 14)

Source Form
ORAB #opr8i
ORAB opr8a
ORAB opr16a
ORAB oprx0_xysp
ORAB oprx9,xysp
ORAB oprx16,xysp
ORAB [D,xysp]
ORAB [oprx16,xysp]

Operation
(B) + (M) B
Logical OR B with Memory

Addr.
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

Machine
Coding (hex)
CA
DA
FA
EA
EA
EA
EA
EA

ii
dd
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

Access Detail
HCS12
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

SXHI

NZVC

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

HC12

ORCC #opr8i

(CCR) + M CCR
Logical OR CCR with Memory

IMM

14 ii

PSHA

(SP) 1 SP; (A) M(SP)

Push Accumulator A onto Stack

INH

36

Os

Os

PSHB

(SP) 1 SP; (B) M(SP)

Push Accumulator B onto Stack

INH

37

Os

Os

PSHC

(SP) 1 SP; (CCR) M (SP)

Push CCR onto Stack

INH

39

Os

Os

PSHD

(SP) 2 SP; (A:B) M(SP):M(SP+1)

Push D Accumulator onto Stack

INH

3B

OS

OS

PSHX

(SP) 2 SP; (XH:XL) M(SP):M(SP+1)

Push Index Register X onto Stack

INH

34

OS

OS

PSHY

(SP) 2 SP; (YH:YL) M(SP):M(SP+1)

Push Index Register Y onto Stack

INH

35

OS

OS

PULA

(M(SP)) A; (SP) + 1 SP
Pull Accumulator A from Stack

INH

32

ufO

ufO

PULB

(M(SP)) B; (SP) + 1 SP
Pull Accumulator B from Stack

INH

33

ufO

ufO

PULC

(M(SP)) CCR; (SP) + 1 SP

Pull CCR from Stack

INH

38

ufO

ufO

PULD

(M(SP):M(SP+1)) A:B; (SP) + 2 SP

Pull D from Stack

INH

3A

UfO

UfO

PULX

(M(SP):M(SP+1)) XH:XL; (SP) + 2 SP

Pull Index Register X from Stack

INH

30

UfO

UfO

PULY

(M(SP):M(SP+1)) YH:YL; (SP) + 2 SP

Pull Index Register Y from Stack

INH

31

UfO

UfO

REV

MIN-MAX rule evaluation

Find smallest rule input (MIN).
Store to rule outputs unless fuzzy output is already larger
(MAX).

18 3A

Orf(t,tx)O

Orf(t,tx)O

???

??!

Special

(exit + re-entry replaces comma

above if interrupted)
ff + Orf(t,

ff + Orf(t,

ORf(t,Tx)O

ORf(t,Tx)O

For rule weights see REVW.

Each rule input is an 8-bit offset from the base address in Y.
Each rule output is an 8-bit offset from the base address in Y.
$FE separates rule inputs from rule outputs. $FF terminates
the rule list.
REV may be interrupted.
REVW

MIN-MAX rule evaluation

Find smallest rule input (MIN),
Store to rule outputs unless fuzzy output is already larger
(MAX).
Rule weights supported, optional.
Each rule input is the 16-bit address of a fuzzy input. Each rule
output is the 16-bit address of a fuzzy output. The value $FFFE
separates rule inputs from rule outputs. $FFFF terminates the
rule list.

Special

18 3B

(loop to read weight if enabled)

(r,RfRf)

(r,RfRf)

(exit + re-entry replaces comma

above if interrupted)
ffff + ORf(t,

fff + ORf(t,

REVW may be interrupted.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

15

CPU12RG/D

Instruction Set Summary (Sheet 11 of 14)

Source Form
ROL opr16a
ROL oprx0_xysp
ROL oprx9,xysp
ROL oprx16,xysp
ROL [D,xysp]
ROL [oprx16,xysp]
ROLA
ROLB
ROR opr16a
ROR oprx0_xysp
ROR oprx9,xysp
ROR oprx16,xysp
ROR [D,xysp]
ROR [oprx16,xysp]
RORA
RORB

Addr.
Mode

Operation

b7
C
Rotate Memory Left through Carry

b0

Rotate A Left through Carry

Rotate B Left through Carry

b7
b0
C
Rotate Memory Right through Carry

Rotate A Right through Carry

Rotate B Right through Carry

Machine
Coding (hex)

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

75
65
65
65
65
65
45
55

hh
xb
xb
xb
xb
xb

ll

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

76
66
66
66
66
66
46
56

hh
xb
xb
xb
xb
xb

ll

ff
ee ff
ee ff

ff
ee ff
ee ff

Access Detail

SXHI

NZVC

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O

rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O

uUnPPP

HCS12

HC12

RTC

(M(SP)) PPAGE; (SP) + 1 SP;

(M(SP):M(SP+1)) PCH:PCL;
(SP) + 2 SP
Return from Call

INH

0A

uUnfPPP

RTI

(M(SP)) CCR; (SP) + 1 SP

(M(SP):M(SP+1)) B:A; (SP) + 2 SP
(M(SP):M(SP+1)) XH:XL; (SP) + 4 SP
(M(SP):M(SP+1)) PCH:PCL; (SP) 2 SP
(M(SP):M(SP+1)) YH:YL; (SP) + 4 SP
Return from Interrupt

INH

0B

uUUUUPPP

RTS

(M(SP):M(SP+1)) PCH:PCL;
(SP) + 2 SP
Return from Subroutine

INH

3D

UfPPP

SBA

(A) (B) A
Subtract B from A

INH

18 16

OO

SBCA #opr8i
SBCA opr8a
SBCA opr16a
SBCA oprx0_xysp
SBCA oprx9,xysp
SBCA oprx16,xysp
SBCA [D,xysp]
SBCA [oprx16,xysp]

(A) (M) C A
Subtract with Borrow from A

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

82
92
B2
A2
A2
A2
A2
A2

ii
dd
hh
xb
xb
xb
xb
xb

SBCB #opr8i
SBCB opr8a
SBCB opr16a
SBCB oprx0_xysp
SBCB oprx9,xysp
SBCB oprx16,xysp
SBCB [D,xysp]
SBCB [oprx16,xysp]

(B) (M) C B
Subtract with Borrow from B

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C2
D2
F2
E2
E2
E2
E2
E2

ii
dd
hh
xb
xb
xb
xb
xb

SEC

1C
Translates to ORCC #$01

IMM

14 01

SEI

1 I; (inhibit I interrupts)
Translates to ORCC #$10

IMM

14 10

P 1

SEV

1V
Translates to ORCC #$02

IMM

14 02

SEX abc,dxys

$00:(r1) r2 if r1, bit 7 is 0 or

$FF:(r1) r2 if r1, bit 7 is 1

INH

B7 eb

uUUUUPPP

(with interrupt pending)

uUUUUVfPPP

ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

uUUUUfVfPPP

UfPPP

OO

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

Sign Extend 8-bit r1 to 16-bit r2

r1 may be A, B, or CCR
r2 may be D, X, Y, or SP
Alternate mnemonic for TFR r1, r2

16

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 12 of 14)

Source Form

Operation

STAA opr8a
STAA opr16a
STAA oprx0_xysp
STAA oprx9,xysp
STAA oprx16,xysp
STAA [D,xysp]
STAA [oprx16,xysp]

(A) M
Store Accumulator A to Memory

STAB opr8a
STAB opr16a
STAB oprx0_xysp
STAB oprx9,xysp
STAB oprx16,xysp
STAB [D,xysp]
STAB [oprx16,xysp]

(B) M
Store Accumulator B to Memory

STD opr8a
STD opr16a
STD oprx0_xysp
STD oprx9,xysp
STD oprx16,xysp
STD [D,xysp]
STD [oprx16,xysp]

(A) M, (B) M+1

Store Double Accumulator

STOP

(SP) 2 SP;
RTNH:RTNL M(SP):M(SP+1);
(SP) 2 SP; (YH:YL) M(SP):M(SP+1);
(SP) 2 SP; (XH:XL) M(SP):M(SP+1);
(SP) 2 SP; (B:A) M(SP):M(SP+1);
(SP) 1 SP; (CCR) M (SP);
STOP All Clocks

Addr.
Mode

Machine
Coding (hex)

DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

5A
7A
6A
6A
6A
6A
6A

dd
hh
xb
xb
xb
xb
xb

DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

5B
7B
6B
6B
6B
6B
6B

dd
hh
xb
xb
xb
xb
xb

DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

5C
7C
6C
6C
6C
6C
6C

dd
hh
xb
xb
xb
xb
xb

INH

ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff

Access Detail
HCS12

HC12

SXHI

NZVC

Pw
PwO
Pw
PwO
PwP
PIfw
PIPw

Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw

Pw
PwO
Pw
PwO
PwP
PIfw
PIPw

Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw

PW
PWO
PW
PWO
PWP
PIfW
PIPW

PW
WOP
PW
PWO
PWP
PIfPW
PIPPW

(entering STOP)

18 3E

OOSSSSsf

OOSSSfSs
(exiting STOP)

fVfPPP

fVfPPP
(continue)

ff

fO

Registers stacked to allow quicker recovery by interrupt.

(if STOP disabled)

If S control bit = 1, the STOP instruction is disabled and acts

like a two-cycle NOP.
STS opr8a
STS opr16a
STS oprx0_xysp
STS oprx9,xysp
STS oprx16,xysp
STS [D,xysp]
STS [oprx16,xysp]

(SPH:SPL) M:M+1
Store Stack Pointer

STX opr8a
STX opr16a
STX oprx0_xysp
STX oprx9,xysp
STX oprx16,xysp
STX [D,xysp]
STX [oprx16,xysp]

(XH:X L) M:M+1
Store Index Register X

STY opr8a
STY opr16a
STY oprx0_xysp
STY oprx9,xysp
STY oprx16,xysp
STY [D,xysp]
STY [oprx16,xysp]

(YH:Y L) M:M+1
Store Index Register Y

SUBA #opr8i
SUBA opr8a
SUBA opr16a
SUBA oprx0_xysp
SUBA oprx9,xysp
SUBA oprx16,xysp
SUBA [D,xysp]
SUBA [oprx16,xysp]

(A) (M) A
Subtract Memory from Accumulator A

MOTOROLA

OO

DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

5F
7F
6F
6F
6F
6F
6F

dd
hh
xb
xb
xb
xb
xb

DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

5E
7E
6E
6E
6E
6E
6E

dd
hh
xb
xb
xb
xb
xb

DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

5D
7D
6D
6D
6D
6D
6D

dd
hh
xb
xb
xb
xb
xb

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

80
90
B0
A0
A0
A0
A0
A0

ii
dd
hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff

ll
ff
ee ff
ee ff

OO

PW
PWO
PW
PWO
PWP
PIfW
PIPW

PW
WOP
PW
PWO
PWP
PIfPW
PIPPW

PW
PWO
PW
PWO
PWP
PIfW
PIPW

PW
WOP
PW
PWO
PWP
PIfPW
PIPPW

PW
PWO
PW
PWO
PWP
PIfW
PIPW

PW
WOP
PW
PWO
PWP
PIfPW
PIPPW

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

CPU12 Reference Guide (for HCS12 and original M68HC12)

17

CPU12RG/D

Instruction Set Summary (Sheet 13 of 14)

Source Form

Operation

SUBB #opr8i
SUBB opr8a
SUBB opr16a
SUBB oprx0_xysp
SUBB oprx9,xysp
SUBB oprx16,xysp
SUBB [D,xysp]
SUBB [oprx16,xysp]

(B) (M) B
Subtract Memory from Accumulator B

SUBD #opr16i
SUBD opr8a
SUBD opr16a
SUBD oprx0_xysp
SUBD oprx9,xysp
SUBD oprx16,xysp
SUBD [D,xysp]
SUBD [oprx16,xysp]

(D) (M:M+1) D
Subtract Memory from D (A:B)

SWI

(SP) 2 SP;
RTNH:RTNL M(SP):M(SP+1);
(SP) 2 SP; (YH:YL) M(SP):M(SP+1);
(SP) 2 SP; (XH:XL) M(SP):M(SP+1);
(SP) 2 SP; (B:A) M(SP):M(SP+1);
(SP) 1 SP; (CCR) M (SP)
1 I; (SWI Vector) PC
Software Interrupt

Addr.
Mode

Machine
Coding (hex)

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

C0
D0
F0
E0
E0
E0
E0
E0

ii
dd
hh
xb
xb
xb
xb
xb

IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]

83
93
B3
A3
A3
A3
A3
A3

jj
dd
hh
xb
xb
xb
xb
xb

INH

3F

ll
ff
ee ff
ee ff
kk
ll
ff
ee ff
ee ff

Access Detail

SXHI

NZVC

P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf

P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP

PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf

OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP

HCS12

HC12

VSPSSPSsP*

VfPPP

111

OO

VSPSSPSsP*

(for Reset)
VfPPP

*The CPU also uses the SWI microcode sequence for hardware interrupts and unimplemented opcode traps. Reset uses the VfPPP variation of this sequence.
TAB

(A) B
Transfer A to B

INH

18 0E

OO

TAP

(A) CCR
Translates to TFR A , CCR

INH

B7 02

TBA

(B) A
Transfer B to A

INH

18 0F

OO

TBEQ abdxys,rel9

If (cntr) = 0, then Branch;

else Continue to next instruction

REL
(9-bit)

04 lb rr

PPP (branch)
PPO (no branch)

IDX

18 3D xb

ORfffP

P
OO

PPP

OrrffffP

Test Counter and Branch if Zero

(cntr = A, B, D, X,Y, or SP)
TBL oprx0_xysp

(M) + [(B) ((M+1) (M))] A

8-Bit Table Lookup and Interpolate

C Bit is undefined
in HC12

Initialize B, and index before TBL.

<ea> points at first 8-bit table entry (M) and B is fractional part
of lookup value.
(no indirect addressing modes or extensions allowed)
TBNE abdxys,rel9

If (cntr) not = 0, then Branch;

else Continue to next instruction

REL
(9-bit)

04 lb rr

PPP (branch)
PPO (no branch)

B7 eb

PPP

Test Counter and Branch if Not Zero

(cntr = A, B, D, X,Y, or SP)
TFR abcdxys,abcdxys

(r1) r2 or
$00:(r1) r2 or
(r1[7:0]) r2

INH

or

Transfer Register to Register

r1 and r2 may be A, B, CCR, D, X, Y, or SP
TPA

18

(CCR) A
Translates to TFR CCR ,A

INH

B7 20

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Instruction Set Summary (Sheet 14 of 14)

Source Form
TRAP trapnum

Addr.
Mode

Operation
(SP) 2 SP;
RTNH:RTNL M(SP):M(SP+1);
(SP) 2 SP; (YH:YL) M(SP):M(SP+1);
(SP) 2 SP; (XH:XL) M(SP):M(SP+1);
(SP) 2 SP; (B:A) M(SP):M(SP+1);
(SP) 1 SP; (CCR) M (SP)
1 I; (TRAP Vector) PC

INH

Machine
Coding (hex)

Access Detail
HCS12

SXHI

NZVC

rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
O
O

00

HC12

18 tn
tn = $30$39
or
$40$FF

OVSPSSPSsP

F7
E7
E7
E7
E7
E7
97
D7

rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
O
O

OfVSPSSPSsP

Unimplemented opcode trap

TST opr16a
TST oprx0_xysp
TST oprx9,xysp
TST oprx16,xysp
TST [D,xysp]
TST [oprx16,xysp]
TSTA
TSTB

(M) 0
Test Memory for Zero or Minus

(A) 0
(B) 0

EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH

Test A for Zero or Minus

Test B for Zero or Minus

hh
xb
xb
xb
xb
xb

ll
ff
ee ff
ee ff

TSX

(SP) X
Translates to TFR SP,X

INH

B7 75

TSY

(SP) Y
Translates to TFR SP,Y

INH

B7 76

TXS

(X) SP
Translates to TFR X,SP

INH

B7 57

TYS

(Y) SP
Translates to TFR Y,SP

INH

B7 67

WAI

(SP) 2 SP;
RTNH:RTNL M(SP):M(SP+1);
(SP) 2 SP; (YH:YL) M(SP):M(SP+1);
(SP) 2 SP; (XH:XL) M(SP):M(SP+1);
(SP) 2 SP; (B:A) M(SP):M(SP+1);
(SP) 1 SP; (CCR) M (SP);
WAIT for interrupt

INH

3E

OSSSSsf

WAV

SiFi Y:D

and

i=1

OSSSfSsf

fVfPPP

or

(after interrupt)
VfPPP

or

Special

18 3C

Fi X

Of(frr,ffff)O
Off(frr,fffff)O

11

???

???

(add if interrupt)

i=1

SSS + UUUrr,

SSSf + UUUrr

UUUrr,ffff
(frr,ffff)O

UUUrrfffff
(frr,fffff)O

Calculate Sum of Products and Sum of Weights for Weighted

Average Calculation
Initialize B, X, and Y before WAV. B specifies number of elements. X points at first element in Si list. Y points at first element in Fi list.
All Si and Fi elements are 8-bits.
If interrupted, six extra bytes of stack used for
intermediate values
wavr

see WAV

pseudoinstruction

Resume executing an interrupted WAV instruction (recover intermediate results from stack rather than initializing them to
zero)

XGDX

(D) (X)
Translates to EXG D, X

INH

B7 C5

XGDY

(D) (Y)
Translates to EXG D, Y

INH

B7 C6

Special

3C

(exit + re-entry replaces comma

above if interrupted)
SSS + UUUrr,

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

SSSf + UUUrr

19

20

Table 1. Indexed Addressing Mode Postbyte Encoding (xb)

10

20

30

40

50

60

70

80

0,X
5b const
01
1,X
5b const
02
2,X
5b const
03
3,X
5b const
04
4,X
5b const
05
5,X
5b const
06
6,X
5b const
07
7,X
5b const
08
8,X
5b const
09
9,X
5b const
0A
10,X
5b const
0B
11,X
5b const
0C
12,X
5b const
0D
13,X
5b const
0E
14,X
5b const
0F
15,X
5b const

16,X
5b const
11
15,X
5b const
12
14,X
5b const
13
13,X
5b const
14
12,X
5b const
15
11,X
5b const
16
10,X
5b const
17
9,X
5b const
18
8,X
5b const
19
7,X
5b const
1A
6,X
5b const
1B
5,X
5b const
1C
4,X
5b const
1D
3,X
5b const
1E
2,X
5b const
1F
1,X
5b const

1,+X
pre-inc
21
2,+X
pre-inc
22
3,+X
pre-inc
23
4,+X
pre-inc
24
5,+X
pre-inc
25
6,+X
pre-inc
26
7,+X
pre-inc
27
8,+X
pre-inc
28
8,X
pre-dec
29
7,X
pre-dec
2A
6,X
pre-dec
2B
5,X
pre-dec
2C
4,X
pre-dec
2D
3,X
pre-dec
2E
2,X
pre-dec
2F
1,X
pre-dec

1,X+
post-inc
31
2,X+
post-inc
32
3,X+
post-inc
33
4,X+
post-inc
34
5,X+
post-inc
35
6,X+
post-inc
36
7,X+
post-inc
37
8,X+
post-inc
38
8,X
post-dec
39
7,X
post-dec
3A
6,X
post-dec
3B
5,X
post-dec
3C
4,X
post-dec
3D
3,X
post-dec
3E
2,X
post-dec
3F
1,X
post-dec

0,Y
5b const
41
1,Y
5b const
42
2,Y
5b const
43
3,Y
5b const
44
4,Y
5b const
45
5,Y
5b const
46
6,Y
5b const
47
7,Y
5b const
48
8,Y
5b const
49
9,Y
5b const
4A
10,Y
5b const
4B
11,Y
5b const
4C
12,Y
5b const
4D
13,Y
5b const
4E
14,Y
5b const
4F
15,Y
5b const

16,Y
5b const
51
15,Y
5b const
52
14,Y
5b const
53
13,Y
5b const
54
12,Y
5b const
55
11,Y
5b const
56
10,Y
5b const
57
9,Y
5b const
58
8,Y
5b const
59
7,Y
5b const
5A
6,Y
5b const
5B
5,Y
5b const
5C
4,Y
5b const
5D
3,Y
5b const
5E
2,Y
5b const
5F
1,Y
5b const

1,+Y
pre-inc
61
2,+Y
pre-inc
62
3,+Y
pre-inc
63
4,+Y
pre-inc
64
5,+Y
pre-inc
65
6,+Y
pre-inc
66
7,+Y
pre-inc
67
8,+Y
pre-inc
68
8,Y
pre-dec
69
7,Y
pre-dec
6A
6,Y
pre-dec
6B
5,Y
pre-dec
6C
4,Y
pre-dec
6D
3,Y
pre-dec
6E
2,Y
pre-dec
6F
1,Y
pre-dec

1,Y+
post-inc
71
2,Y+
post-inc
72
3,Y+
post-inc
73
4,Y+
post-inc
74
5,Y+
post-inc
75
6,Y+
post-inc
76
7,Y+
post-inc
77
8,Y+
post-inc
78
8,Y
post-dec
79
7,Y
post-dec
7A
6,Y
post-dec
7B
5,Y
post-dec
7C
4,Y
post-dec
7D
3,Y
post-dec
7E
2,Y
post-dec
7F
1,Y
post-dec

0,SP
5b const
81
1,SP
5b const
82
2,SP
5b const
83
3,SP
5b const
84
4,SP
5b const
85
5,SP
5b const
86
6,SP
5b const
87
7,SP
5b const
88
8,SP
5b const
89
9,SP
5b const
8A
10,SP
5b const
8B
11,SP
5b const
8C
12,SP
5b const
8D
13,SP
5b const
8E
14,SP
5b const
8F
15,SP
5b const

90
16,SP
5b const
91
15,SP
5b const
92
14,SP
5b const
93
13,SP
5b const
94
12,SP
5b const
95
11,SP
5b const
96
10,SP
5b const
97
9,SP
5b const
98
8,SP
5b const
99
7,SP
5b const
9A
6,SP
5b const
9B
5,SP
5b const
9C
4,SP
5b const
9D
3,SP
5b const
9E
2,SP
5b const
9F
1,SP
5b const

A0
1,+SP
pre-inc
A1
2,+SP
pre-inc
A2
3,+SP
pre-inc
A3
4,+SP
pre-inc
A4
5,+SP
pre-inc
A5
6,+SP
pre-inc
A6
7,+SP
pre-inc
A7
8,+SP
pre-inc
A8
8,SP
pre-dec
A9
7,SP
pre-dec
AA
6,SP
pre-dec
AB
5,SP
pre-dec
AC
4,SP
pre-dec
AD
3,SP
pre-dec
AE
2,SP
pre-dec
AF
1,SP
pre-dec

B0
1,SP+
post-inc
B1
2,SP+
post-inc
B2
3,SP+
post-inc
B3
4,SP+
post-inc
B4
5,SP+
post-inc
B5
6,SP+
post-inc
B6
7,SP+
post-inc
B7
8,SP+
post-inc
B8
8,SP
post-dec
B9
7,SP
post-dec
BA
6,SP
post-dec
BB
5,SP
post-dec
BC
4,SP
post-dec
BD
3,SP
post-dec
BE
2,SP
post-dec
BF
1,SP
post-dec

Key to Table 1

MOTOROLA

postbyte (hex)
B0

#,REG
type

type offset used

source code syntax

C0
0,PC
5b const
C1
1,PC
5b const
C2
2,PC
5b const
C3
3,PC
5b const
C4
4,PC
5b const
C5
5,PC
5b const
C6
6,PC
5b const
C7
7,PC
5b const
C8
8,PC
5b const
C9
9,PC
5b const
CA
10,PC
5b const
CB
11,PC
5b const
CC
12,PC
5b const
CD
13,PC
5b const
CE
14,PC
5b const
CF
15,PC
5b const

D0
16,PC
5b const
D1
15,PC
5b const
D2
14,PC
5b const
D3
13,PC
5b const
D4
12,PC
5b const
D5
11,PC
5b const
D6
10,PC
5b const
D7
9,PC
5b const
D8
8,PC
5b const
D9
7,PC
5b const
DA
6,PC
5b const
DB
5,PC
5b const
DC
4,PC
5b const
DD
3,PC
5b const
DE
2,PC
5b const
DF
1,PC
5b const

E0

F0

n,X
9b const
E1
n,X
9b const
E2
n,X
16b const
E3
[n,X]
16b indr
E4
A,X
A offset
E5
B,X
B offset
E6
D,X
D offset
E7
[D,X]
D indirect
E8
n,Y
9b const
E9
n,Y
9b const
EA
n,Y
16b const
EB
[n,Y]
16b indr
EC
A,Y
A offset
ED
B,Y
B offset
EE
D,Y
D offset
EF
[D,Y]
D indirect

n,SP
9b const
F1
n,SP
9b const
F2
n,SP
16b const
F3
[n,SP]
16b indr
F4
A,SP
A offset
F5
B,SP
B offset
F6
D,SP
D offset
F7
[D,SP]
D indirect
F8
n,PC
9b const
F9
n,PC
9b const
FA
n,PC
16b const
FB
[n,PC]
16b indr
FC
A,PC
A offset
FD
B,PC
B offset
FE
D,PC
D offset
FF
[D,PC]
D indirect

CPU12RG/D

CPU12 Reference Guide (for HCS12 and original M68HC12)

00

CPU12RG/D

Table 2. Indexed Addressing Mode Summary

Postbyte
Code (xb)

Operand
Syntax

Comments

rr0nnnnn

,r
n,r
n,r

5-bit constant offset

n = 16 to +15
rr can specify X, Y, SP, or PC

111rr0zs

n,r
n,r

Constant offset (9- or 16-bit signed)

z- 0 = 9-bit with sign in LSB of postbyte (s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC

rr1pnnnn

n,r
n,+r
n,r
n,r+

Auto predecrement, preincrement, postdecrement, or postincrement;

p = pre-(0) or post-(1), n = 8 to 1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)

111rr1aa

A,r
B,r
D,r

Accumulator offset (unsigned 8-bit or 16-bit)

aa - 00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC

111rr011

[n,r]

16-bit offset indexed-indirect

rr can specify X, Y, SP, or PC

111rr111

[D,r]

Accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

21

22
TRANSFERS
LS

MS

CPU12 Reference Guide (for HCS12 and original M68HC12)

AA

BA

CCR A

TMP3L A

BA

XL A

YL A

SPL A

AB

BB

CCR B

TMP3L B

BB

XL B

YL B

SPL B

A CCR

B CCR

CCR CCR

TMP3L CCR

B CCR

XL CCR

YL CCR

SPL CCR

TMP3 TMP2

D TMP2

X TMP2

Y TMP2

SP TMP2

sex:A TMP2 sex:B TMP2 sex:CCR TMP2

3
4

sex:A D
SEX A,D

sex:B D
SEX B,D

sex:CCR D
SEX CCR,D

TMP3 D

DD

XD

YD

SP D

sex:A X
SEX A,X

sex:B X
SEX B,X

sex:CCR X
SEX CCR,X

TMP3 X

DX

XX

YX

SP X

sex:A Y
SEX A,Y

sex:B Y
SEX B,Y

sex:CCR Y
SEX CCR,Y

TMP3 Y

DY

XY

YY

SP Y

sex:A SP
SEX A,SP

sex:B SP
SEX B,SP

sex:CCR SP
SEX CCR,SP

TMP3 SP

D SP

X SP

Y SP

SP SP

EXCHANGES
LS

MS

BA
AB

XL A
$00:A X

YL A
$00:A Y

SPL A
$00:A SP

BB
$FF A

XL B
$FF:B X

YL B
$FF:B Y

SPL B
$FF:B SP

AA

BA

CCR A

TMP3L A
$00:A TMP3

AB

BB

CCR B

TMP3L B
$FF:B TMP3

A CCR

B CCR

CCR CCR

$00:A TMP2 $00:B TMP2 $00:CCR TMP2

TMP2L A
TMP2L B
TMP2L CCR

TMP3L CCR
B CCR
XL CCR
YL CCR
SPL CCR
$FF:CCR TMP3 $FF:CCR D $FF:CCR X $FF:CCR Y $FF:CCR SP
TMP3 TMP2

D TMP2

X TMP2

Y TMP2

SP TMP2

MOTOROLA

$00:A D

$00:B D

$00:CCR D
B CCR

TMP3 D

DD

XD

YD

SP D

$00:A X
XL A

$00:B X
XL B

$00:CCR X
XL CCR

TMP3 X

DX

XX

YX

SP X

$00:A Y
YL A

$00:B Y
YL B

$00:CCR Y
YL CCR

TMP3 Y

DY

XY

YY

SP Y

$00:A SP
SPL A

$00:B SP
SPL B

$00:CCR SP
SPL CCR

TMP3 SP

D SP

X SP

Y SP

SP SP

TMP2 and TMP3 registers are for factory use only.

CPU12RG/D

Table 3. Transfer and Exchange Postbyte Encoding

CPU12RG/D

Table 4. Loop Primitive Postbyte Encoding (lb)

A 10

00

DBEQ

A 20

DBEQ

(+)

()

01
(+)

()

02

(+)

12

03

04

DBEQ

14

DBEQ

(+)

24

()

05

44

54

64

(+)

74

84

TBNE

TBNE

94

IBEQ

X B5

IBNE

IBNE

(+)

Y 96

IBNE
()

X A5
()

Y 86

D B4

IBNE
(+)

X 95
(+)

Y 76

D A4

IBEQ

IBEQ

B3

()

X 85
()

Y 66

IBEQ

A3

(+)

X 75
(+)

Y 56

TBNE

B2

93

()

X 65
()

Y 46

TBNE

TBEQ

83

(+)

X 55

TBEQ

()
Y 36

TBEQ
()

X 45

DBNE

(+)
Y 26

TBEQ
(+)

X 35

DBNE

()
Y 16

DBNE
()

X 25

DBEQ

(+)
06

34

(+)

X 15

DBEQ

DBNE

73

()

A2

IBNE

(+)

92

B B1

IBNE

()

82

63

(+)

72

53

()

62

43

(+)

52

33

()

42

23

(+)

32

13

()

22

()

B A1

IBEQ

IBNE

(+)

B 91

IBEQ

A B0

IBNE

()

B 81

TBNE

A A0

IBEQ

(+)

B 71

TBNE

A 90

IBEQ

()

B 61

TBEQ

A 80

TBNE

(+)

B 51

TBEQ

A 70

TBNE

()

B 41

DBNE

A 60

TBEQ

(+)

B 31

DBNE

A 50

TBEQ

()

B 21

DBEQ

A 40

DBNE

(+)

B 11

DBEQ

A 30

DBNE

()

Y A6

Y B6

DBEQ

DBEQ

DBNE

DBNE

TBEQ

TBEQ

TBNE

TBNE

IBEQ

IBEQ

IBNE

IBNE

(+)

()

(+)

()

(+)

()

(+)

()

(+)

()

(+)

()

07

SP 17

SP 27

SP 37

SP 47

SP 57

SP 67

SP 77

SP 87

SP 97

SP A7

SP B7

SP

DBEQ

DBEQ

DBNE

DBNE

TBEQ

TBEQ

TBNE

TBNE

IBEQ

IBEQ

IBNE

IBNE

(+)

()

(+)

()

(+)

()

(+)

()

(+)

()

(+)

()

Key to Table 4
postbyte (hex)
(bit 3 is dont care)

counter used
B0

_BEQ
()

branch condition

sign of 9-bit relative branch offset

(lower eight bits are an extension byte
following postbyte)

Table 5. Branch/Complementary Branch

Branch
Test
Mnemonic
Opcode
Boolean
Test
r>m
BGT
2E
Z + (N V) = 0
rm
rm
BGE
2C
NV=0
r<m
r=m
BEQ
27
Z=1
rm
rm
BLE
2F
Z + (N V) = 1
r>m
r<m
BLT
2D
NV=1
rm
r>m
BHI
22
C+Z=0
rm
rm
BHS/BCC
24
C=0
r<m
r=m
BEQ
27
Z=1
rm
rm
BLS
23
C+Z=1
r>m
r<m
BLO/BCS
25
C=1
rm
Carry
BCS
25
C=1
No Carry
Negative
BMI
2B
N=1
Plus
Overflow
BVS
29
V=1
No Overflow
r=0
BEQ
27
Z=1
r0
Always
BRA
20

Never
For 16-bit offset long branches preceed opcode with a $18 page prebyte.

MOTOROLA

Complementary Branch
Mnemonic
Opcode
BLE
2F
BLT
2D
BNE
26
BGT
2E
BGE
2C
BLS
23
BLO/BCS
25
BNE
26
BHI
22
BHS/BCC
24
BCC
24
BPL
2A
BVC
28
BNE
26
BRN
21

CPU12 Reference Guide (for HCS12 and original M68HC12)

Comment
Signed
Signed
Signed
Signed
Signed
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Simple
Simple
Simple
Simple
Unconditional

23

CPU12RG/D

Memory Expansion
There are three basic memory expansion configurations in the
M68HC12 and HCS12 MCU Families.
1. Basic 64 Kbyte memory map with no additional expanded memory
support
2. >5 megabyte expanded memory support with 8-bit PPAGE,
DPAGE, and EPAGE registers (MC68HC812A4 only)
3. >1 megabyte expanded memory support with 6-bit PPAGE
register only This configuration applies to all currently available
HC12 and HCS12 devices with >60 Kbytes of on-chip FLASH
memory.
Memory precedence
Highest
On-chip registers (usually $0000 or $1000)
BDM ROM (only when BDM active)
On-chip RAM
On-chip EEPROM
On-chip program memory (FLASH or ROM)
Expansion windows (on MCUs with expanded memory)
Other external memory
Lowest
CPU sees 64 Kbytes of address space (CPU_ADDR [15:0])
PPAGE 8-bit register to select 1 of 256 16 Kbyte program pages
or 6-bit register to select 1 of 64 16 Kbyte program pages
DPAGE 8-bit register to select 1 of 256 4 Kbyte data pages
EPAGE 8-bit register to select 1 of 256 1 Kbyte extra pages
Extended address is up to 22 bits (EXT_ADDR [21:0])
Program expansion window works with CALL and RTC instructions to
simplify program access to extended memory space. Data and extra
expansion windows (when present) use traditional banked expansion
memory techniques.

24

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

Program window
If
CPU_ADDR [15:0] = $8000BFFF and PWEN = 1
Then
EXT_ADDR [21:0] = PPAGE [7:0]:CPU_ADDR [13:0]
or EXT_ADDR [19:0] = PPAGE [5:0]:CPU_ADDR [13:0]
Program window works with CALL/RTC to automate bank switching.
256 pages (banks) of 16 Kbytes each = 4 megabytes or
64 pages (banks) of 16 Kbytes each = 1 megabyte
Data window (when present)
If
CPU_ADDR [15:0] = $70007FFF and DWEN = 1
Then
EXT_ADDR [21:0] = 1:1:DPAGE [7:0]:CPU_ADDR [11:0]
User program controls DPAGE value
Extra window (when present)
If
CPU_ADDR [15:0] = $000003FF and EWDIR = 1
and EWEN = 1
or CPU_ADDR [15:0] = $040007FF and EWDIR = 0
and EWEN = 1
Then
EXT_ADDR [21:0] = 1:1:1:1:EPAGE [7:0]:CPU_ADDR
[9:0]
User program controls EPAGE value
CPU address not in any enabled window
EXT_ADDR [21:0] = 1:1:1:1:1:1:CPU_ADDR [15:0] (4 megabyte
map)
or (for 1 megabyte map)
If
CPU_ADDR [15:0] = $00003FFF
Then
EXT_ADDR [19:0] = 1:1:1:1:0:1:CPU_ADDR [13:0]
This causes the FLASH at PPAGE $3D to also appear
as unpaged memory at CPU addresses $00003FFF.
If
CPU_ADDR [15:0] = $40007FFF
Then
EXT_ADDR [19:0] = 1:1:1:1:1:0:CPU_ADDR [13:0]
This causes the FLASH at PPAGE $3E to also appear
as unpaged memory at CPU addresses $40007FFF.
If
CPU_ADDR [15:0] = $C000FFFF
Then
EXT_ADDR [19:0] = 1:1:1:1:1:1:CPU_ADDR [13:0]
This causes the FLASH at PPAGE $3F to also appear
as unpaged memory at CPU addresses $C000FFFF.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

25

CPU12RG/D

64 PAGES OF 16 KBYTES EACH VIEWED THROUGH P-WINDOW

0 0000
3 0000
C 0000
0000
0400
07FF

PPAGE
($3D)
image

E FFFF
F 0000

PPAGE
($3C)
60

1FFF
2000

3FFF
4000

PPAGE
($3E)
image

PPAGE
($3D)
61

5FFF
6000
6FFF
7000
7FFF
8000

F 8000
F 0000

PPAGE
($3E)
62

9FFF
A000

P WINDOW

BFFF
C000

PPAGE
($3F)
image

F BFFF
F C000

PPAGE
($3F)
63

DFFF
E000

FFFF
CPU_ADDR

F FFFF
EXT_ADR

Figure 2. Memory Mapping in 1-Megabyte Map

26

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOTOROLA

CPU12RG/D

256 pages of 16 Kbytes each viewed through P-window (4 M)

00 0000
256 pages of 4 Kbytes each viewed through D-window (1 M)

30 0000
3C 0000

E window
(EWDIR = 1)
0000
0400
07FF

3E FFFF
3F 0000

.
.
.

E window
(EWDIR = 0)
PPAGE
($FC)
252

1FFF
2000

3FFF
4000

PPAGE
($FD)
253

5FFF
6000
6FFF
7000
D window
7FFF
8000

P window

3F 7FFF
3F 8000

PPAGE
($FE)
254

9FFF
A000

BFFF
C000

3F BFFF
3F C000

PPAGE
($FF)
255

DFFF
E000

FFFF
CPU_ADDR

3F FFFF

.
.
.
DPAGE
($F0)
240
DPAGE
($F1)
241
DPAGE
($F2)
242
DPAGE
($F3)
243
DPAGE
($F4)
244
DPAGE
($F5)
245
DPAGE
($F6)
246
DPAGE
($F7)
247
DPAGE
($F8)
248
DPAGE
($F9)
249
DPAGE
($FA)
250
DPAGE
($FB)
251
DPAGE
($FC)
252
DPAGE
($FD)
253
DPAGE
($FE)
254
DPAGE
($FF)
255

256 pages of 1 Kbyte each viewed

.
through E-window (256 K)
.
.
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255

EXT_ADDR

Figure 3. Memory Mapping in 4-Megabyte Map

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

27

28

Table 6. CPU12 Opcode Map (Sheet 1 of 2)

BGND
IH
01

1 IM
5 11

MEM
IH
02

EDIV

INY

CPU12 Reference Guide (for HCS12 and original M68HC12)

DEY
loop

EMUL

JMP
JMP

3 EX
4 17

BSR
2 DI
1 18

INX
DEX
RTC

BVS
BPL

BCLR

BRCLR

BRCLR

MOTOROLA

4-6 EX

wavr
RTS

2 IH
3/1 3E

WAI
SWI
2 IH

BCLR

ROR

BRCLR
4 DI

ROR

2-4 EX
3-6 77

ASR
1 ID
1 68

ASR

2-4 EX
3-6 78

ASL
1 ID
1 69

ASL

2-4 EX
2-4 79

CLR
1 ID
2 6A

CLR

2-4 EX
2-4 7A

STAA
2 ID
2 6B

STAA

2-4 EX
2-4 7B

STAB
2 ID
2 6C

STAB

2-4 EX
2-4 7C

STD
2 ID
2 6D

STD

2-4 EX
2-4 7D

STY
2 ID
2 6E

STX

4 DI
4 5F

ROL

2-4 EX
3-6 76

1 ID
1 67

STY
3 DI
4 5E

BRSET

1 DI

ROL

STD
3 DI
4 5D

LSR

2-4 EX
3-6 75

1 ID
1 66

STAB

2-5 DI
4 5C

BSET

1 DI
9 4F

LSR

STAA

CALL

DEC

2-4 EX
3-6 74

1 ID
1 65

ASLD

1 IH
7 5A

CALL

1 DI
7 4E

2 IH
3/1 3F

BLE

5 RL

LSRD

1 DI
5 4D

DEC

ASLB
1 IH
1 59

INC
2-4 EX
3-6 73

1 ID
1 64

ASRB
1 IH
1 58

ASLA

1 ID
+5 4C

2 SP
3/1 3D

BGT

5 RL
5 2F

ASRA

1 EX
4 DI
2 4B 7-10 5B

PSHD

INC

RORB
1 IH
1 57

COM

2-4 EX
3-6 72

1 ID
1 63

ROLB
1 IH
1 56

RORA

1 IH
3 4A

PULD

BLT
4 RL
5 2E

ROLA

1 IH
2 49

PSHC

BGE

BRSET

4-6 EX
4-6 1F

PULC

COM

LSRB
1 IH
1 55

1 IH
3 48

2 IH
3/1 3C

4 RL
4 2D

BCLR

3-5 EX
4-6 1E

BRSET

BMI

BSET

PSHB

2 IH
3/1 3B

2-4 RL
4 2C

LSRA

STY

2-4 EX
2-4 7E

STX
2 ID
2 6F

STS

STX

2-4 EX
2-4 7F

STS
2 ID

4 80

NEG

2-4 EX
3-6 71

1 ID
1 62

DECB
1 IH
1 54

1 IH
2 47

2 IH
3/1 3A

2-4 RL
2 2B

3-5 EX
4-6 1D

PSHA

2 IH
3/1 39

2-4 RL
2 2A

LEAS
1 ID
4-6 1C

BSET

ID

BVC

DECA

1 IH
2 46

2 IH
3/1 38

- RL
2 29

LEAX
1 ID
8 1B

RTI

ID
0F

BEQ

LEAY
1 ID
7 1A

PSHY

1 ID
1 61

INCB
1 IH
1 53

1 IH
2 45

2 IH
3/1 37

2 RL
- 28

1 1 19

IH
0A

ID
0E

BNE

page 2

IH
09

PSHX

2 IH
3/1 36

3 RL
4 27

JSR

RL
08

ID
0D

BCS

INCA

3-6 70

NEG

COMB
1 IH
1 52

1 IH
2 44

2 IH
3/1 35

2-4 RL
4 26

JSR

EX
07

IH
0B

BCC

JSR

2-4 ID
3 16

PULB

2 IH
3/1 34

2 RL
4-7 25

COMA

1 IH
3 43

1 60

NEGB
1 IH
1 51

1 IH
3 42

PULA

BLS

ORCC

PULY

2 IH
3/1 33

1 RL
1 24

3 IM
3-6 15

ID
06

BHI

1 50

NEGA
1 IH
3 41

2 IH
3/1 32

1 RL
3 23

1 IH
3 14

RL
05

BRN

MUL

3 40

PULX
2 IH
1 31

1 RL
1 22

1 IH
1 13

IH
04

3 30

BRA

2 RL
11 21

1 IH
1 12

IH
03

IH
0C

1 20

ANDCC

STS

2-4 EX

SUBA
3 IM
4 81

CMPA
3 IM
4 82

SBCA
3 IM
4 83

SUBD
3 IM
4 84

ANDA
3 IM
4 85

BITA
3 IM
4 86

LDAA
3 IM
4 87

CLRA
3 IH
4 88

EORA
3 IM
3 89

ADCA
3 IM
3 8A

ORAA
3 IM
3 8B

ADDA
3 IM
3 8C

1 90

SUBA
2 DI
1 91

CMPA
2 DI
1 92

SBCA
2 DI
2 93

SUBD
3 DI
1 94

ANDA
2 DI
1 95

LDAA
2 DI
1 97

TSTA
1 IH
1 98

EORA
2 DI
1 99

ADCA
2 DI
1 9A

ORAA
2 DI
1 9B

ADDA
2 DI
2 9C

CPY
3 IM
3 8E

CPX
3 DI
2 9F

CPS
3 IM

CPS
3 DI

CPX

2-4 EX
3-6 BF

CPS
2 ID

CPY

2-4 EX
3-6 BE

CPX
2 ID
3 AF

CPD

2-4 EX
3-6 BD

CPY
2 ID
3 AE

ADDA

2-4 EX
3-6 BC

CPD
2 ID
3 AD

ORAA

2-4 EX
3-6 BB

ADDA
2 ID
3 AC

ADCA

2-4 EX
3-6 BA

ORAA
2 ID
3 AB

EORA

2-4 EX
3-6 B9

ADCA
2 ID
3 AA

BITB
3 IM
3 C6

LDAB
3 IM
1 C7

TFR/EXG

1 IH
3-6 B8

EORA
2 ID
3 A9

ANDB
3 IM
3 C5

LDAA

2-4 EX
1 B7

NOP
1 IH
3 A8

ADDD
3 IM
3 C4

BITA

2-4 EX
3-6 B6

LDAA
2 ID
1 A7

SBCB
3 IM
3 C3

ANDA

2-4 EX
3-6 B5

BITA
2 ID
3 A6

CMPB
3 IM
3 C2

SUBD

2-4 EX
3-6 B4

ANDA
2 ID
3 A5

3 IM
3 C1

SBCA

2-4 EX
3-6 B3

SUBD
2 ID
3 A4

SUBB

CMPA

2-4 EX
3-6 B2

SBCA
2 ID
3 A3

3 C0

SUBA

2-4 EX
3-6 B1

CMPA
2 ID
3 A2

CPY
3 DI
2 9E

CPX
3 IM
3 8F

2 ID
3 A1

CPD
3 DI
2 9D

3-6 B0

SUBA

BITA
2 DI
1 96

CPD
3 IM
3 8D

3 A0

CPS

2-4 EX

CLRB

2 IH
3 C8

EORB
3 IM
3 C9

ADCB
3 IM
3 CA

ORAB
3 IM
3 CB

ADDB
3 IM
3 CC

1 D0

SUBB
2 DI
1 D1

CMPB
2 DI
1 D2

SBCB
2 DI
2 D3

ADDD
3 DI
1 D4

ANDB
2 DI
1 D5

BITB
2 DI
1 D6

LDAB
2 DI
1 D7

EORB
2 DI
1 D9

ADCB
2 DI
1 DA

ORAB
2 DI
1 DB

ADDB
2 DI
2 DC

LDY
3 IM
3 CE

LDX
3 DI
2 DF

LDS
3 IM

LDS
3 DI

Key to Table 6:
Opcode
Mnemonic
Address Mode

00

Number of HCS12 cycles ( indicates HC12 different)

Number of bytes

BGND
IH

3
3

LDX

2-4 EX
3-6 FF

LDS
2 ID

3
3

LDY

2-4 EX
3-6 FE

LDX
2 ID
3 EF

3
3

LDD

2-4 EX
3-6 FD

LDY
2 ID
3 EE

3
3

ADDB

2-4 EX
3-6 FC

LDD
2 ID
3 ED

3
3

ORAB

2-4 EX
3-6 FB

ADDB
2 ID
3 EC

3
3

ADCB

2-4 EX
3-6 FA

ORAB
2 ID
3 EB

3
3

EORB

2-4 EX
3-6 F9

ADCB
2 ID
3 EA

3
3

TST

2-4 EX
3-6 F8

EORB
2 ID
3 E9

3
3

LDAB

2-4 EX
3-6 F7

TST
1 ID
3 E8

3
3

BITB

2-4 EX
3-6 F6

LDAB
2 ID
1 E7

3
3

ANDB

2-4 EX
3-6 F5

BITB
2 ID
3 E6

3
3

ADDD

2-4 EX
3-6 F4

ANDB
2 ID
3 E5

3
3

SBCB

2-4 EX
3-6 F3

ADDD
2 ID
3 E4

3
3

CMPB

2-4 EX
3-6 F2

SBCB
2 ID
3 E3

SUBB

2-4 EX
3-6 F1

CMPB
2 ID
3 E2

LDY
3 DI
2 DE

LDX
3 IM
3 CF

2 ID
3 E1

LDD
3 DI
2 DD

3-6 F0

SUBB

TSTB
1 IH
1 D8

LDD
3 IM
3 CD

3 E0

3
3

LDS

2-4 EX

CPU12RG/D

5 10

00

MOTOROLA

Table 6. CPU12 Opcode Map (Sheet 2 of 2)

4 10

00

MOVW
IM-ID
01

MOVW

12 20

IDIV
5 IH
5 11

4 30

LBRA
2 RL
12 21

FDIV

4 IH
3 31

LBRN

EX-ID
02

MOVW

CPU12 Reference Guide (for HCS12 and original M68HC12)

MOVW
EX-EX
05

MOVW
ID-EX
06

EMULS
6 IH
6 14

EDIVS
6 IH
5 15

IDIVS
SBA
2 IH
3 17

DAA
IH
08

MOVB
IM-ID
09

MOVB
EX-ID
0A

MOVB
ID-ID
0B

MOVB
IM-EX
0C

MOVB
EX-EX
0D

MOVB
ID-EX
0E

TAB
IH
0F

MINA
5 ID
5 1A

EMAXD
4 ID
4 1B

MAXM
6 ID
5 1

EMAXM

REVW
WAV

4 SP
4/3 3D

TBL

4 ID
4/3 3E

ETBL
4 ID

TRAP
3 IH

TRAP
2 IH

TRAP
2 IH

TRAP
2 IH

TRAP
2 IH

TRAP
2 IH

TRAP

2 IH
10 AF

TRAP
2 IH

TRAP

2 IH
10 CF

TRAP
2 IH

2
10

TRAP
2 IH

29

CPU12RG/D

* The opcode $04 (on sheet 1 of 2) corresponds to one of the loop primitive instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE.
Refer to instruction summary for more information.
Refer to instruction summary for different HC12 cycle count.

2
10

TRAP

2 IH
10 FF

TRAP
2 IH

2
10

TRAP

2 IH
10 FE

TRAP

2 IH
10 EF

2
10

TRAP

2 IH
10 FD

TRAP

2 IH
10 EE

TRAP

2 IH
10 DF

TRAP
2 IH

TRAP

2 IH
10 DE

2
10

TRAP

2 IH
10 FC

TRAP

2 IH
10 ED

2
10

TRAP

2 IH
10 FB

TRAP

2 IH
10 EC

TRAP

2 IH
10 DD

TRAP

2 IH
10 CE

TRAP

2 IH
10 BF

TRAP
2 IH

TRAP

2 IH
10 BE

TRAP

2 IH
10 CD

TRAP

2 IH
10 DC

2
10

TRAP

2 IH
10 FA

TRAP

2 IH
10 EB

2
10

TRAP

2 IH
10 F9

TRAP

2 IH
10 EA

TRAP

2 IH
10 DB

TRAP

2 IH
10 CC

TRAP

2 IH
10 BD

TRAP

2 IH
10 AE

TRAP

2 IH
10 9F

TRAP

2 IH
10 AD

TRAP

2 IH
10 9E

TRAP

2 IH
10 8F

TRAP

2 IH
10 9D

TRAP

2 IH
10 8E

TRAP

2 IH
10 7F

TRAP

2 IH
10 8D

TRAP

2 IH
10 7E

TRAP

2 IH
10 6F

TRAP

2 IH
10 7D

TRAP

2 IH
10 6E

TRAP

2 IH
10 5F

TRAP

2 IH
10 6D

TRAP

2 IH
10 5E

TRAP

2 IH
10 4F

TRAP

2 IH
10 5D

TRAP
3 IH
8 4E

STOP

4 IH
4/3 3F

LBLE

3-5 RL

TRAP

TRAP

2 IH
10 BC

TRAP

2 IH
10 CB

TRAP

2 IH
10 DA

2
10

TRAP

2 IH
10 F8

TRAP

2 IH
10 E9

2
10

TRAP

2 IH
10 F7

TRAP

2 IH
10 E8

TRAP

2 IH
10 D9

TRAP

2 IH
10 CA

TRAP

2 IH
10 BB

TRAP

2 IH
10 AC

TRAP

2 IH
10 BA

TRAP

2 IH
10 AB

TRAP

2 IH
10 9C

TRAP

2 IH
10 AA

TRAP

2 IH
10 9B

TRAP

2 IH
10 8C

TRAP

2 IH
10 9A

TRAP

2 IH
10 8B

TRAP

2 IH
10 7C

TRAP

2 IH
10 8A

TRAP

2 IH
10 7B

TRAP

2 IH
10 6C

TRAP

2 IH
10 7A

TRAP

2 IH
10 6B

TRAP

2 IH
10 5C

TRAP

2 IH
10 6A

TRAP

2 IH
10 5B

TRAP

2 IH
6 4D

TRAP

2 IH
10 5A

TRAP

4 SP
2 IH
4/3 3C 7B 4C

LBGT

3-5 RL
4-7 2F

EMINM
2 ID

REV

4 SP
2 IH
4/3 3B 5n/3n 4B

LBLT

3-5 RL
4-7 2E

TRAP

2 IH
3n 4A

TRAP

2 IH
10 C9

TRAP

2 IH
10 D8

2
10

TRAP

2 IH
10 F6

TRAP

2 IH
10 E7

2
10

TRAP

2 IH
10 F5

TRAP

2 IH
10 E6

TRAP

2 IH
10 D7

TRAP

2 IH
10 C8

TRAP

2 IH
10 B9

TRAP

2 IH
10 C7

TRAP

2 IH
10 B8

TRAP

2 IH
10 A9

TRAP

2 IH
10 B7

TRAP

2 IH
10 A8

TRAP

2 IH
10 99

TRAP

2 IH
10 A7

TRAP

2 IH
10 98

TRAP

2 IH
10 89

TRAP

2 IH
10 97

TRAP

2 IH
10 88

TRAP

2 IH
10 79

TRAP

2 IH
10 87

TRAP

2 IH
10 78

TRAP

2 IH
10 69

TRAP

2 IH
10 77

TRAP

2 IH
10 68

TRAP

2 IH
10 59

TRAP

2 IH
10 67

TRAP

2 IH
10 58

TRAP

2 IH
10 49

TRAP

LBGE

3-5 RL
D4-7 2D

MINM
5 ID
2 1E

TRAP

TRAP

2 IH
10 57

TRAP

2 IH
10 48

4 IH
4/3 3A

LBMI

3-5 RL
4-7 2C

TRAP

2 IH
10 47

TRAP

LBPL

3-5 RL
4-7 2B

EMIND
5 ID
6 1C

TRAP

TRAP

2 IH
10 D6

2
10

TRAP

2 IH
10 F4

TRAP

2 IH
10 E5

2
10

TRAP

2 IH
10 F3

TRAP

2 IH
10 E4

TRAP

2 IH
10 D5

TRAP

2 IH
10 C6

TRAP

2 IH
10 D4

TRAP

2 IH
10 C5

TRAP

2 IH
10 B6

TRAP

2 IH
10 C4

TRAP

2 IH
10 B5

TRAP

2 IH
10 A6

TRAP

2 IH
10 B4

TRAP

2 IH
10 A5

TRAP

2 IH
10 96

TRAP

2 IH
10 A4

TRAP

2 IH
10 95

TRAP

2 IH
10 86

TRAP

2 IH
10 94

TRAP

2 IH
10 85

TRAP

2 IH
10 76

TRAP

2 IH
10 84

TRAP

2 IH
10 75

TRAP

2 IH
10 66

TRAP

2 IH
10 74

TRAP

2 IH
10 65

TRAP

2 IH
10 56

TRAP

2 IH
10 64

TRAP

2 IH
10 55

TRAP

2 IH
10 46

4 IH
4/3 39

LBVS

3-5 RL
4-7 2A

TRAP

TRAP

2 IH
10 54

TRAP

2 IH
10 45

4 IH
4/3 38

LBVC

3-5 RL
4-7 29

TRAP

4 IH
4/3 37

LBEQ

2 RL
4-7 28

MAXA
4 ID
5 19

2 ID
2 1F

TBA
IH

CBA
2 IH
4 18

TRAP

2 IH
10 44

4 IH
4/3 36

LBNE
2 RL
2 27

TRAP

2
10

TRAP

2 IH
10 F2

TRAP

2 IH
10 E3

10

TRAP

2 IH
10 F1

TRAP

2 IH
10 E2

TRAP

2 IH
10 D3

10 F0

TRAP

2 IH
10 E1

TRAP

2 IH
10 D2

TRAP

2 IH
10 C3

10 E0

TRAP

2 IH
10 D1

TRAP

2 IH
10 C2

TRAP

2 IH
10 B3

10 D0

TRAP

2 IH
10 C1

TRAP

2 IH
10 B2

TRAP

2 IH
10 A3

10 C0

TRAP

2 IH
10 B1

TRAP

2 IH
10 A2

TRAP

2 IH
10 93

10 B0

TRAP

2 IH
10 A1

TRAP

2 IH
10 92

TRAP

2 IH
10 83

10 A0

TRAP

2 IH
10 91

TRAP

2 IH
10 82

TRAP

2 IH
10 73

10 90

TRAP

2 IH
10 81

TRAP

2 IH
10 72

TRAP

2 IH
10 63

10 80

TRAP

2 IH
10 71

TRAP

2 IH
10 62

TRAP

2 IH
10 53

10 70

TRAP

2 IH
10 61

TRAP

2 IH
10 52

TRAP

2 IH
10 43

4 IH
4/3 35

LBCS
2 RL
2 26

TRAP
IH
33

10 60

TRAP

2 IH
10 51

TRAP

2 IH
10 42

4 IH
4/3 34

LBCC

2 RL
12 25

5 IH
2 16

ABA
IH
07

LBLS

2 RL
12 24

IH
32

10 50

TRAP

2 IH
10 41

TRAP

5 IH
2 RL
4
5 12
13 22
4/3
MOVW EMACS
LBHI
4 RL
ID-ID
4 SP
4
03
5 13
3 23
4/3
IM-EX
04

10 40

TRAP

CPU12RG/D

Table 7. Hexadecimal to ASCII Conversion

30

Hex

ASCII

Hex

ASCII

Hex

ASCII

Hex

$00

NUL

$20

SP space

$40

$60

$01

SOH

$21

$41

$61

$02

STX

$22

quote

$42

$62

$03

ETX

$23

$43

$63

$04

EOT

$24

$44

$64

$05

ENQ

$25

$45

$65

$06

ACK

$26

&

$46

$66

$07

BEL beep

$27

apost.

$47

$67

$08

BS back
sp

$28

$48

$68

$09

HT tab

$29

$49

$69

$0A

LF
linefeed

$2A

$4A

$6A

$0B

VT

$2B

$4B

$6B

$0C

FF

$2C

, comma

$4C

$6C

$0D

CR return

$2D

$4D

$6D

$0E

SO

$2E

- dash
. period

$4E

$6E

$0F

SI

$2F

$4F

$6F

$10

DLE

$30

$50

$70

$11

DC1

$31

$51

$71

$12

DC2

$32

$52

$72

$13

DC3

$33

$53

$73

$14

DC4

$34

$54

$74

$15

NAK

$35

$55

$75

$16

SYN

$36

$56

$76

$17

ETB

$37

$57

$77

$18

CAN

$38

$58

$78

$19

EM

$39

$59

$79

$1A

SUB

$3A

$5A

$7A

$1B

ESCAPE

$3B

$5B

$7B

$1C

FS

$3C

<

$5C

$7C

$1D

GS

$3D

$5D

$7D

$1E

RS

$3E

>

$5E

$7E

$1F

US

$3F

$5F

_ under

$7F

DEL
delete

CPU12 Reference Guide (for HCS12 and original M68HC12)

ASCII

grave

MOTOROLA

CPU12RG/D

Hexadecimal to Decimal Conversion

To convert a hexadecimal number (up to four hexadecimal digits) to
decimal, look up the decimal equivalent of each hexadecimal digit in
Table 8. The decimal equivalent of the original hexadecimal number is
the sum of the weights found in the table for all hexadecimal digits.
Table 8. Hexadecimal to/from Decimal Conversion
15

Bit

15

12

11

4th Hex Digit

Hex

8
3rd Hex Digit

Decimal

Hex

Decimal

Bit
4
2nd Hex Digit

Hex

Decimal

0
1st Hex Digit

Hex

Decimal

4,096

256

16

8,192

512

32

12,288

768

48

16,384

1,024

64

20,480

1,280

80

24,576

1,536

96

28,672

1,792

112

32,768

2,048

128

36,864

2,304

144

40,960

2,560

160

10

45,056

2,816

176

11

49,152

3,072

192

12

53,248

3,328

208

13

57,344

3,484

224

14

61,440

3,840

240

15

Decimal to Hexadecimal Conversion

To convert a decimal number (up to 65,53510) to hexadecimal, find the
largest decimal number in Table 8 that is less than or equal to the
number you are converting. The corresponding hexadecimal digit is the
most significant hexadecimal digit of the result. Subtract the decimal
number found from the original decimal number to get the remaining
decimal value. Repeat the procedure using the remaining decimal value
for each subsequent hexadecimal digit.

MOTOROLA

CPU12 Reference Guide (for HCS12 and original M68HC12)

31

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CPU12RG/D