tn2919 Nand 101
tn2919 Nand 101
tn2919 Nand 101
Technical Note
NAND Flash 101: An Introduction to NAND Flash and How to Design It In to Your Next Product
Introduction
This technical note discusses the basics of NAND Flash and demonstrates its power, density, and cost advantages for embedded systems. It covers data reliability and methods for overcoming common interface design challenges, focusing on the actual hardware and software components necessary to enable designers to build complete and functional subsystems. Embedded systems have traditionally utilized NOR Flash for nonvolatile memory. Many current designs are moving to NAND Flash to take advantage of its higher density and lower cost for high-performance applications. Figure 1 shows how demand for NAND Flash has been driven primarily several major marketssolid state drives, mobile phones, Flash memory cards, USB Flash drives and MP3/PMP players. As the quest has continued for lower-power, lighter, more robust products, NAND Flash has become the leading storage choice for a broad range of applications. It meets the storage requirements of many consumer storage, audio, and video products far better than a hard driveparticularly in lower-capacity applications (8GB or less). Figure 1: Major Markets Driving NAND Flash
70,000 60,000 50,000 Million GB 40,000 30,000 20,000 10,000
Flash Memory Cards Other Solid State Drives Digital Video Camcorders Personal Navigation Devices Digital Still Cameras Mobile Phones MP3/PMP Players USB Flash Drives
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Microns production data sheet specifications. All information discussed herein is provided on an as is basis, without warranties of any kind.
Flash Basics
The NAND Flash device discussed in this technical note is based on a 2Gb asynchronous SLC device and its parameters (unless otherwise noted). Higher density devices and other more advanced NAND devices may have additional features and different parameters. The NAND Flash array is grouped into a series of blocks, which are the smallest erasable entities in a NAND Flash device. A NAND Flash block is 128KB. Erasing a block sets all bits to 1 (and all bytes to FFh). Programming is necessary to change erased bits from 1 to 0. The smallest entity that can be programmed is a byte. Some NOR Flash memory can perform READ-While-WRITE operations. Although NAND FLASH cannot perform READs and WRITEs simultaneously, it is possible to accomplish READ/WRITE operations at the system level using a method called shadowing. Shadowing has been used on personal computers for many years to load the BIOS from the slower ROM into the higher-speed RAM. There is a limit to the number of times NAND Flash blocks can reliably be programmed and erased. Nominally, each NAND block will survive 100,000 PROGRAM/ERASE cycles. A technique known as wear leveling ensures that all physical blocks are exercised uniformly. To maximize the life span of a design, it is critical to implement both wear leveling and bad-block management. Figure 2 shows a comparison of NAND Flash and NOR Flash cells. NAND efficiencies are due in part to the small number of metal contacts in the NAND Flash string. NAND Flash cell size is much smaller than NOR Flash cell size4F2 compared to 10F2because NOR Flash cells require a separate metal contact for each cell.
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
NAND
Contact
NOR
Bit line Contact Word line
Word line
Cell Array
Bit line
Unit Cell
Unit Cell
Source line 2F
Source line 2F
Layout
2F
5F
Cross Section
Cell Size
4F2
10F2
NAND Flash is very similar to a hard-disk drive. It is sector-based (page-based) and well suited for storage of sequential data such as pictures, video, audio, or PC data. Although random access can be accomplished at the system level by shadowing the data to RAM, doing so requires additional RAM storage. Also, like a hard-disk drive, a NAND Flash device may have bad blocks and requires error-correction code (ECC) to maintain data integrity. NAND Flash cells are 60% smaller than NOR Flash cells, providing the higher densities required for todays low-cost consumer devices in a significantly reduced die area. NAND Flash is used in virtually all removable cards, including USB drives, secure digital (SD) cards, memory stick cards, CompactFlash cards, and multimedia cards (MMCs). The NAND Flash multiplexed interface provides a consistent pinout for all recent devices and densities. This pinout allows designers to use lower densities and migrate to higher densities without any hardware changes to the printed circuit board.
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Bit line
Disadvantages
Applications
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Structural Differences
NAND Flash offers several structural advantages over NOR Flash, starting with the pin count. The hardware pin requirements for NAND Flash and NOR Flash interfaces differ markedly. NOR Flash requires approximately 44 I/O pins for a 16-bit device, while NAND Flash requires only 24 pins for a comparable interface (see Table 3). The multiplexed command, address, and data bus reduces the number of required pins by nearly 45%. An added benefit of the multiplexed interface is that higher-density NAND Flash devices can be supported using the same hardware design and printed circuit board (PCB) used for lower densities. The common TSOP-1 package has been in use for many years, and this feature enables customers to migrate to higher-density NAND Flash devices using the same PCB design. Another advantage of NAND Flash is evident in the packaging options. For example, this NAND Flash device offers a monolithic 2Gb die or it can support up to four stacked die, accommodating an 8Gb device in the same package. This makes it possible for a single package and interface to support higher densities in the future. Table 3: Required Hardware Pins
NOR Flash: 44 Pins Random-access interface, typically composed of: CE# WE# OE# D[15:0] A[23:0] WP# Chip enable Write enable Output enable Data bus Address bus Write protect
NAND Flash: 23 Pins (x16) I/O device-type interface, composed of: CE# WE# RE# CLE ALE I/O[7:0] WP# R/B# Chip enable Write enable Read enable Command latch enable Address latch enable Data bus (I/O[15:0} for x16 parts) Write protect Ready/busy
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
TN-29-19: NAND Flash 101 NAND Flash Architecture and Basic SLC Operation
Register
2112 bytes 64
PROGRAM: 220s/page
8-bit byte or 16-bit word Data area: 2048 bytes Spare area (ECC, etc.) 64 bytes
Erasing a block requires approximately 500s. After the data is loaded in the register, programming a page requires approximately 220s. A PAGE READ operation requires approximately 25s, during which the page is accessed from the array and loaded into the 16,896-bit (2112-byte) register. The register is then available for the user to clock out the data. In addition to the I/O bus, the NAND Flash interface consists of six major control signals (see Table 4 on page 7). (Note: The # symbol after a signal indicates that the signal is asserted LOW.)
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
TN-29-19: NAND Flash 101 NAND Flash Architecture and Basic SLC Operation
Table 4: Signal Descriptions
Symbol ALE Signal Address latch enable Description
CE#
CLE
R/B#
RE# WE#
When ALE is HIGH, addresses are latched into the NAND Flash address register on the rising edge of the WE# signal. Chip enable If CE is not asserted, the NAND Flash device remains in standby mode and does not respond to any control signals. Command latch enable When CLE is HIGH, commands are latched into the NAND Flash command register on the rising edge of the WE# signal. Ready/busy# If the NAND Flash device is busy with an ERASE, PROGRAM, or READ operation, the R/B# signal is asserted LOW. The R/B# signal is open drain and requires a pull-up resistor. Read enable RE# enables the output data buffers. Write enable WE# is responsible for clocking data, address, or commands into the NAND Flash device.
Data is shifted into or out of the NAND Flash register 8 or 16 bits at a time. In a PROGRAM operation, the data to be programmed is clocked into the data register on the rising edge of WE#. Special commands are used to randomly access data or move data around within the register to make random access possible; see RANDOM DATA INPUT Operation on page 15 and READ FOR INTERNAL DATA MOVE Operation on page 20. Data is output from the data register in a similar fashion by means of the read enable (RE#) signal, which is responsible for outputting the current data and incrementing to the next location. The WE# and RE# clocks can run as fast as 25ns per transfer. When RE# or chip enable (CE#) are not asserted LOW, the output buffers are tri-stated. This combination of CE# and RE# activates the output buffers, enabling NAND Flash to share the data bus with other types of memory, such as NOR Flash, SRAM, or DRAM. This feature is sometimes referred to as chip enable dont care. The primary purpose of this reference is to differentiate very old NAND Flash devices, which require CE# to be asserted for the entire cycle. All NAND Flash operations are initiated by issuing a command cycle. This is accomplished by placing the command on I/O[7:0], driving CE# LOW and CLE HIGH, then issuing a WE# clock. Commands, addresses, and data are clocked into the NAND Flash device on the rising edge of WE# (see Figure 4 and Table 5 on page 8). Most commands require a number of address cycles followed by a second command cycle. With the exception of the RESET and READ STATUS commands, new commands should not be issued when the device is busy (see Figure 4 and Table 5 on page 8).
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
TN-29-19: NAND Flash 101 NAND Flash Architecture and Basic SLC Operation
Figure 4: Command Cycles for NAND Flash Operations
CLE
CE#
WE#
I/Ox
30h Command cycle 2 tCEA CE# tREA RE# I/Ox DOUT Don't Care
Table 5:
Command READ PAGE READ PAGE CACHE SEQUENTIAL READ PAGE CACHE SEQUENTIAL LAST READ for INTERNAL DATA MOVE RANDOM DATA READ READ ID READ STATUS PROGRAM PAGE PROGRAM PAGE CACHE PROGRAM for INTERNAL DATA MOVE RANDOM DATA INPUT ERASE BLOCK RESET
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1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. The page address and the block address, collectively, constitute the row address. 2. If CA11 = 1, then CA[10:6] must be 0. 3. The most significant address byte is the fifth cycle; the least significant address byte is the first cycle
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I/Ox
READ ID Operation The READ ID (90h) command requires one dummy address cycle (00h), but it does not require a second command cycle (see Table 5 on page 8). After the command and dummy addresses are issued, the ID data can be read out by keeping CLE and ALE LOW and toggling the RE# signal for each byte of ID. Figure 6 shows the timing of the READ ID operation, and Table 7 shows the format of the 5-byte response. Figure 6:
CLE
READ ID Command
CE#
RE# tWHR I/Ox 90h 00h Address, 1 cycle tREA Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
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0 1 0 1
0 0 0 0
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
1. b = binary; h = hexadecimal
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1. h = hexadecimal
READ STATUS Operation READ STATUS (70h) is the second command that can be issued while the NAND Flash device is busy. This command does not require an address or second command cycle. The status of the NAND Flash device can be monitored by issuing the RE# clock signal following the READ STATUS command. If the READ STATUS command is used to monitor the ready state of the device, the command should be issued only one time, and the status can be re-read by re-issuing the RE# clock. Alternatively, the RE# signal can be kept LOW, waiting to receive the appropriate status bit before proceeding. READ STATUS also reports the status of the write-protect signal, and the pass/fail status of previous PROGRAM or ERASE operations. It is mandatory that the pass status be attained on PROGRAM or ERASE operations to ensure proper data integrity. Table 9: READ STATUS Response
PROGRAM PAGE Pass/fail Ready/busy Ready/busy Write protect Notes: PROGRAM PAGE CACHE MODE Pass/fail (N) Pass/fail (N - 1) Ready/busy1 Ready/busy cache2 Write protect PAGE READ PAGE READ CACHE MODE Ready/busy Ready/busy Write protect Ready/busy1 Ready/busy cache2 Write protect BLOCK ERASE Pass/fail
SR Bit 0 1 2 3 4 5 6 7 [15:8]
Definition
0 = Successful PROGRAM/ERASE 1 = Error in PROGRAM/ERASE 0 = Successful PROGRAM/ERASE 1 = Error in PROGRAM/ERASE 0 0 0 Ready/busy 0 = Busy 1 = Ready Ready/busy 0 = Busy 1 = Ready Write 0 = Protected protect 1 = Not protected 0
1. Status register bit 5 is 0 during the actual programming operation. If cache mode is used, this bit will be 1 when all internal operations are complete. 2. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
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ERASE Command
CE#
WE#
RE#
I/Ox
60h
D0h
13
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PROGRAM Command
RE#
I/Ox
80h
SERIAL DATA INPUT command
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
DIN
N
DIN
M
10h
PROGRAM command
70h
READ STATUS command
Status
R/B# x8 device: m = 2112 bytes x16 device: m = 1056 words Dont Care
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CE#
tWC tADL tADL
WE#
tWB tPROG
ALE
RE#
I/Ox
80h
SERIAL DATA INPUT command
Col Col Row Row Row add 1 add 2 add 1 add 2 add 3
DIN N
DIN N+1
85h
Col add 1
Col add 2
DIN N
DIN N+1
10h
PROGRAM command
70h
READ STATUS command
Status
Serial input
Serial input
R/B#
Random data input sequence Dont Care
Partial-Page Programming Due to the large size of NAND Flash pages, partial-page programming is useful for storing smaller amounts of data. Each NAND Flash page can accommodate four PCsized, 512-byte sectors. The spare area of each page provides additional storage for ECC and other software information. While it is advantageous to write all four sectors at once, often this is not possible. For example, when data is appended to a file, the file might start out as 512 bytes, then grow to 1024 bytes. In this situation, a second PROGRAM PAGE operation is required to write the second 512 bytes to the NAND Flash device. The maximum number of times a partial page can be programmed before an ERASE is required is four. Note that for MLC devices, only one partial-page PROGRAM per page is supported between ERASE operations.
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2112 bytes
2048 bytes
64 bytes
Spare areas 1, 2, 3, 4
READ Operation A READ operation starts with the 00h command, followed by five address cycles, then the 30h command to confirm the command sequence (see Figure 11). After the READ transfer time (tR) of approximately 25s has elapsed, the data is loaded into the register and ready for output. Asserting RE# enables the NAND Flash device to output the first byte of data corresponding to the column address specified in the address. Subsequent RE# transitions output data from successive column locations. When the RE# signal is HIGH (not asserted), the I/O lines are tri-stated. Reading past the end of the device (byte 2112 or word 1056) results in invalid data.
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tAR
tWHR
tRC
tREA
Col add 1
Col add 2
Row add1
Row add 2
Row add 3
30h
DOUT N
DOUT N+1
05h
Col add 1
Col add 2
E0h
DOUT M
DOUT M+1
Column address N
Busy
Column address M
RANDOM DATA READ Operation The user can directly access random data by issuing the 05h command, two address cycles, and an E0h confirmation cycle (see Figure 11). When the page has been read from the array, this command provides rapid access to the data. READ PAGE CACHE SEQUENTIAL Operation Only one register in the NAND Flash device has been discussed to this point. The NAND Flash device actually has two registers, a data register and a cache register, as shown in Figure 12. The attributes of these two registers play an important role in the various NAND Flash caching modes. The PAGE READ CACHE MODE command enables the user to pipeline the next sequential access from the array while outputting the previously accessed data. This doublebuffered technique makes it possible to hide the READ transfer time (tR). Data is initially transferred from the NAND Flash array to the data register. If the cache register is available (not busy), the data is quickly moved from the data register to the cache register. After the data has been transferred to the cache register, the data register is available and can start to load the next sequential page from the NAND Flash array. Using the PAGE READ CACHE MODE command delivers a 33% performance improvement over a traditional PAGE READ command on an 8-bit I/O device, with throughput up to 31 MB/s. On 16-bit I/O devices, throughput can be increased to 37 MB/sdelivering as much as a 40% performance improvement over normal PAGE READ operations. See Figure 13 on page 18 for comparison.
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64
64
8-bit byte or 16-bit word Data area: 2048 bytes Spare area (ECC, etc.) 64 bytes
Figure 13:
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64
64
8-bit byte or 16-bit word Data area: 2048 bytes Spare area (ECC, etc.) 64 bytes
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PROGRAM PAGE
80h 80h 80h
10h
10h
10h
tPROG (220s)
80h
15h 80h
15h
80h
15h
80h
15h
600s Commands
READ FOR INTERNAL DATA MOVE Operation The READ FOR INTERNAL DATA MOVE (00h35h) command is also known as copy back. It provides the ability to move data internally from one page to anotherthe data never leaves the NAND Flash device. The READ FOR INTERNAL DATA MOVE operation transfers the data read from the NAND Flash array to the cache register. The data can then be programmed into another page of the device. This is extremely beneficial in cases where the controller needs to move data out of a block before erasing the block. It is also possible to modify the data read before the PROGRAM operation is started. This is useful if the user wants to change the data prior to programming. This feature enables data movement within the NAND Flash device without tying up the processor or the I/O bus.
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TN-29-19: NAND Flash 101 Connecting NAND Flash to a RISC or DSP Processor
NAND Flash register selected Data register Command register Address register Undefined (do not use)
To issue a command, the processor outputs the intended command on the data bus and at output address 0010h. To issue any number of address cycles, the processor simply outputs the intended NAND Flash address sequence to processor address 0020h. With this technique, the user can access commands, addresses, and data directly from the processor without any glue logic. In this scenario, ECC must be handled in the software. Figures 1618, starting on page 22, show the block diagram, low-level pseudo-code, and timing for PROGRAM operations. Many processors have the ability to specify several timing parameters around the processors write signal, which is critical for proper setup and hold timing.
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TN-29-19: NAND Flash 101 Connecting NAND Flash to a RISC or DSP Processor
Figure 16: Glueless NAND Interconnect
VCC
CPU
INTR
NOR/SRAM
CE# WE# OE# Address
NAND Flash
Figure 17:
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TN-29-19: NAND Flash 101 Connecting NAND Flash to a RISC or DSP Processor
Figure 18: PROGRAM Operation Timing
CE#
ALE
CLE
WE#
RE#
I/O[8:0]
80h
Col
Col
Row
Row
Row
D0
D1
D2
D3
D4
D5
D2111
10h
Next command
Processors with a native on-chip NAND Flash controller include the Freescale i.MX21 and i.MX31 processors and several OMAP processors from Texas Instruments. Figure 19 shows the built-in NAND Flash interface on the Freescale i.MX21 processor. The NAND Flash interface is on the right side of the diagram and is connected directly to the NAND Flash. This implementation supports automatic booting from the NAND Flash device, as well as the ECC logic and SRAM buffer. The SRAM port enables code execution directly from the buffer. Figure 19: Built-in NAND Flash Interface on Freescale i.MX21 Processor
NF8BOOT_B NF16BOOT_B NF_16BIT_SEL
Logic
Bootloader
ECC Control
CLE ALE CE
RE WE WP R/B
AHB Bus
Address Control
IDIN IDOUT
Note:
PDF: 09005aef8245f460 / Source: 09005aef8245f3bf tn2919_nand_101.fm - Rev. B 4/10 EN
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TN-29-19: NAND Flash 101 Connecting NAND Flash to a RISC or DSP Processor Multi-Level Cell (MLC)
MLC devices use a special type of cell that stores 2 bits per cell, compared with traditional single-level cell (SLC) devices, which can store only 1 bit per cell. MLC technology offers obvious density advantages. However, MLC lacks the speed and reliability of its SLC counterpart (see Table 11). For this reason, SLC devices are used in the majority of high-performance and high-endurance applications; MLC devices are typically used in consumer and other low-cost products. Table 11: MLC vs. SLC
MLC NAND 3.3V (x8) Symbol
tPROG
SLC NAND 3.3V (x16/x8) Min 100K 1 2008 Typ 220 Max 600 4 25 2048 Units s Cycles s PROGRAM/ ERASE cycles Correctable bits per 512 bytes Blocks
Min 5K 12 1998
Typ 900
Time to transfer contents of data register to the NAND Flash array NOP Number of partial-page programs supported per page before an ERASE is required tR Time to transfer contents of one page in the NAND Flash array to the data register Endurance with ECC and invalid block marking MIN ECC required NVB 16Gb MLC, 4Gb SLC
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TN-29-19: NAND Flash 101 Connecting NAND Flash to a RISC or DSP Processor
Table 12: Number of Bits Required for Various ECC Correction Strengths
Error Correction Level 1 2 3 4 5 6 7 8 9 10 Note: Bits Required in the NAND Flash Spare Area Hamming 13 N/A N/A N/A N/A N/A N/A N/A N/A N/A Reed-Solomon 18 36 54 72 90 108 126 144 162 180 BCH 13 26 39 52 65 78 91 104 117 130
Codes in shaded table cells can fit in the spare area of the example NAND Flash device.
Software
Software is necessary to perform block management in a NAND Flash device. This software manages wear-leveling and logical-to-physical mapping. The software may also provide ECC if the processor does not include ECC. It is important to read the status register after a PROGRAM or ERASE operation to confirm successful completion of the operation. If an operation is not successful, the block should be marked bad and should no longer be used. Previously programmed data should be moved out of the bad block into a new, good block. The specification for a 2Gb SLC NAND Flash device states that it might have up to 40 bad blocks. This maximum number applies to the life of the device (nominally 100,000 PROGRAM/ERASE cycles). Due mostly to their large die size, NAND Flash devices may ship from the factory with a number of bad blocks. The software managing the NAND Flash device maps the bad blocks and replaces them with good blocks. The factory marks these blocks in a specific way so the software can scan all the blocks to determine which are good and which are bad. The bad-block mark is placed at the first location in the spare area (column location 2048). If location 2048 in page 0 is 00h, then the block must be considered bad and mapped out of the system. The initialization software can simply scan through all blocks to determine which blocks are bad and then build a table of these bad blocks for future reference. The user must take special care not to erase the bad-block marks. The factory tests each NAND Flash device over a wide range of temperatures and voltages. Some blocks that are marked bad by the factory may be functional at certain temperatures or voltages but could fail in the future. If the bad-block information is erased, it cannot be recovered.
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Summary
Micron NAND Flash provides the power, density, and cost advantages essential for embedded systems in high-performance applications such as digital cameras and navigational devices, solid state drives, mobile phones, Flash memory cards, and USB Flash drives. As the major markets relying on NAND Flash continue to expand, NAND Flash technology will continue to evolve and claim additional market share, providing the higher densities, lower costs, and added functionality necessary to support these advanced designs.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.