CH 03
CH 03
CH 03
Outline
Background The CMOS Process Flow Latchup Antenna Rules & Layer Density Rules CMOS Process Enhancements Summary
Introduction
An integrated circuit is created by stacking layers of various materials in a pre-specified sequence Both the electrical properties of the material and the geometrical patterns of the layer are important in establishing the characteristics of devices and networks Most layers are created first, and then patterned using lithographic sequence Doped silicon layers are the exception to this rule
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Polycrystal Silicon
wafer
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Surface planarization
poly
substrate
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU
substrate
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Lithography
One of the most critical problems in CMOS fabrication is the technique used to create a pattern
Photolithography
The photolithographic process starts with the desired pattern definition for the layer A mask is a piece of glass that has the pattern defined using a metal such as chromium
Coat photoresist
Liquid photoresist is sprayed onto a spinning wafer
Exposure
Photoresist is sensitive to light, such as ultraviolet (UV)
wafer
The hardened resist layer is used to protect underlying regions from the etching process
Etching
The chemicals are chosen to attack and remove the material layer not shielded by the hardened photoresist
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Dopping
The figure shows the etching process
Hardened resist layer Patterned oxide layer
Substrate
Lateral dopping
Substrate
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N+
N+
Substrate
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Dopping
The conductive characteristics of intrinsic silicon can be changed by introducing impurity atoms into the silicon crystal lattice Impurity elements that use (provide) electrons are called as acceptor (donor) Silicon that contains a majority of donors (acceptor) is known as n-type (p-type) When n-type and p-type materials are merged together, the region where the silicon changes from n-type to p-type is called junction
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MOS Transistor
Basic structure of a NMOS transistor
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n+
n+
Implant of Impurities
Contact Cuts
n+ p-substrate
n+
Polysilicon
Al contacts
Patterning Al layer
n+
n+
p-substrate
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n-well mask
n-well p-substrate
Jin-Fu Li, EE, NCU
Active
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n+ mask
n+
n+ n-well
p-substrate
n+ mask
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poly
oxide
poly
n-
n-
n+
n-
n-
n+
p+ mask
n+
n+
p+ p+ n-well p+ mask
p-substrate
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n+
n+
p-substrate
metal mask
n+
n+
p-substrate
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Vdd
out
Vss
in
out
Vdd
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU
Vss
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p+ n-well
p+
n+
n+
p-substrate
contact cut polysilicon metal gate oxide field oxide
p+ n-well
p+
n+
n+
p-substrate
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Latchup
Latchup is defined as the generation of a lowimpedance path in CMOS chips between power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar transistors These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and virtually short circuit the power rail to ground, thus causing excessive current flows and even permanent device damage
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Rsubstrate
Rwell
2.0mA
Vne
Holding Voltage
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Latchup Triggering
Latchup can be triggered by transient current or voltages that may occur internally to a chip during power-up or externally due to voltages or currents beyond normal operating ranges Two possible triggering mechanisms
Lateral triggering & vertical triggering
npn Rwell
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Latchup Prevention
Reducing the value of resistors and reducing the gain of the parasitic transistors are the basis for eliminating latchup Latchup can be prevented in two basic methods
Latchup resistant CMOS process Layout techniques
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Guard Rings
Guard rings are that p+ diffusions in the psubstrate and n+ diffusions in the n-well to collect injected minority carriers
Vdd
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n+ -
p+ N-well
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Antenna Rules
When a metal wire contacted to a transistor gate is plasma-etched, it can charge up to a voltage sufficient to break down thin gate oxide The metal can be contacted to diffusion to provide a path for the charge to bleed away Antenna rules specify the maximum area of metal that can be connected to a gate without a source or drain to act as a discharge element The design rule normally defines the maximum ratio of metal area to gate area such that charge on the metal will not damage the gate
The ratios can vary from 100:1 to 5000:1 depending on the thickness of the gate oxide (and hence breakdown voltage) of the transistor in question
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L2
Length L2 exceeds allowed limit
Gate may be connected to source/drain at any metal layer in an auto routing situation
metal 4 metal 3
L1
metal 2
metal 1
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Layer density rules are required as a result of the CMP process and the desire to achieve uniform etch rates For example, a metal layer might have to have 30% minimum and 70% maximum fill within a 1mm by 1mm area For digital circuits, layer density levels are normally reached with normal routing Analog & RF circuits are almost sparse
Gate and metal layers may have to be added manually or by a fill program after design has been completed
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<=45nm
Metal/High-k
Metal High-k
D
Silicon Substrate
D
Silicon Substrate
Silicon Substrate
1. Additional poly-depletion capacitor 2. Reaction with high-k dielectric 3. High gate resistance Poly-Si
Poly-depletion capacitor
High-k
D
Silicon Substrate
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Summary
Some of more common CMOS technologies have been covered A representative set of n-well process has been introduced The important condition known as latchup has been introduced with necessary design rules to avoid this condition in CMOS chips Antenna rules & layer density rules should be considered in modern manufacturing process
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