HUMAX STB

Service Manual

For OAK


ModeI

SateIIite STB
IRCI-5400
CRCI-5500
CR-5510


CabIe STB
CI-5100C
VA-5200C

Confidential - 1 - HUMAX Co., Ltd.
SM - OAK (English)
Component and Function list of Each Circuit Page


Page Component Main Function Remark
TUNER
SD1228E/LA MK
Channel Tuning
Be careful of the
component heat
LNB SUPPLY
LNBP15SP
LNB Power Supply
Be careful of static
electricity during
repairs
1
REGULATOR
LM7805
Convert 8V to 5V(Tunner Supply)

2 QPSK Demodulator
TDA8044AH
Channel Locking
PLL part has a low
degree of static
electricity
3 Irdeto Descrambler Chip
SAS004
:Irdeto Decrambling
Inner Irdeto CAS
Option(IRCI-5400
only)
CI controller
CXD1957AQ
: CI & TS buffer controller


Voltage Switching MOSEET
IRE7303
: PCMCIA Card Power supply
Vcc Tr/T timing
control
4


74 Series TS & Address buffer
5 74 Series TS & Address buffer
6 74 Series TS & Address buffer

Be careful of
Timing delay in
each TS



7 Voltage Switching MOSEET
IRE7303
5V,3.3V ON/OEE control
Turn off power
when the system is
Standby
8 Connector
Channel ,Eront b`d & SC Connector


9 Linear Regulator
LM78L12
: Convert 15V to 12V(DC12V)

MPEG TS Demux
SAA7219(MIPS processor)
: MPEG TS Processing

PLL part has a low
degree of static
electricity 10


12MHz Oscillator Irdeto SC clock
Be careful of
frequency oscillator
Option(IRCI-5400
only)
11 74 Series Buffer/ Control Logic Gate
12 East Boot Block ELASH
28E160E3B(16Mb)or28E800E3B(8Mb)
: Main Code is located

Volume of memory
is different in each
model
13 ELASH
28E160B3B-90(16Mb)or
28E800B3B-90(8Mb)
: Channel Data & Constant is located

Volume of memory
is different in each
model

SM - OAK (English) 2 00-06-09

2
15 SDRAM 16M main system memory
Option(IRCI-5400
only)


16 MPEG Decoder
SAA7215
:EMPEG decoding & A/V signal output


17 MPEG SDRAM
KM416S1020BT-G10
MPEG Decoding Memory

18 OSD SDRAM
KM416S1020BT-G10
: OSD & Main Memory

19 Serial and Modem
Supporting UART protocol and external
modem

20 Internal Modem
Supporting UART protocol and internal
modem

21 SPDIE
TOTX178A
: Digital Audio Output

22 Audio DAC
UDA1320
: Audio Digital to Analog Conversion

23 A/V Switching
STV6411AD
: TV,VCR Scart output switching

24 RE Modulator RMUP74055VA
25 CINCH
DPAM-9601E
:Video(CVBS) & Audio(L/R)Output

26 SCART Connector
2201-42RT
: TV & VCR Connector


4M Processor
PIC16C64A(One chip micom)
- Main B/D Power Control
- RCU Receiver
- Key Scan
- 7-Segment Display
- Parallel Communication I/E
Remote Sensor
LTM-97AT-38N
: RCU receive
27



7-Segment

LTC-5623G-12
: Channel & Clock Display
Eront B/D


28 Irdeto SC I/E
TDA8004
: Smart Card Coupler
S/C B/D
Tuner CD1516/P
If Down Converter UPC2798GR
29


REGULATOR
LM7805
:Convert 8V to 5V (Tuner supply)
LM7812
:Convert 17V to 12V (Tuner supply)
30 QAM Decoder IC BCM3118B
Option(CI5100C,
VA5200C Only)




SM - OAK (English) 3 00-06-09

3
SECTION Service Items


!" Highly recommended follow service flow.


1. Appearance (Exterior) Test
Check the condition of install, joining of connectors, break or bend of PCB, cold-soldering
or short of components and problem of parts, etc.

2. Power Test
After the power is on the set, check the output power at JP200 Connector.
The output power is
# 3.3V, 5V, 8V, 15V, 17V, 24V, 30V
Check the Clock and Reset timing.

3. System Test
Check whether CPU of SAA7219 works normally.
This includes Reset, Clock, Memory Access, and the essential items to the basic
movement.

4. MPEG and AV Test
Check the whole process from MPEG Decoding to A/V output
Also check the output port function(SCART, RE-MODULATOR, Phone Jack and etc.) at
back panel.

5. Channel Test (refer to repair of IRCI-5400, CR-5510, CRCI-5500, VACI-5300)
Eront End part is Receiving, Tuning and Locking of RE frequency from LNB of Antenna.
Check the part, which generates DC power supply and 22KHz Tone signal output.

6. Test Smart Card I/E
Check the card is accepted normally.
Check the I/P signal is proper one.

7. Channel Test ( refer to the repair of CI-5100C, VA-5200C)
Receive, tuning and locking the RE frequency from Cable.
Check the repair regarding channel part with tuner and BCM31118B.


!" The pictures in Humax Service Manual can be varied according to the system conditions, input
signal, etc.

!" It is important to trace the consistent flow of signals and find the trouble spot when the problem
occurs. The examples of waves should be referred as one pattern of consistent signals.



SM - OAK (English) 4 00-06-09

4
SECTION Basic Test
Item : Power of SMPS, EEC and MAIN B/D
Symptom : System not working.

Explanation:

!" In this case, check at circuit page 07/JP200 whether each power supply.

!" Item : SMPS Connector
Check point(JP200) : Circuit Diagram Page 07

1Pin : 30V 2Pin : 24V 3Pin : 17V 5Pin : 8V
7Pin : 5VE 9Pin : 3.3V 11pin : 15V
GND: 4, 6, 8, 10, 12 pins


!" Item : the rear part of Power Control
Check point(U200): Circuit Diagram Page 07

1Pin : 5V
3Pin : 3.3V

When 0V electricity passes at Q200 2pin, power is supplied to U200
It is controlled by ERONT B/D.


!" Item: EEC B/D Connector
Check point(JP333): Circuit Diagram Page08

18pin : 3.3V 19pin : 3.3V 20pin: 8V 21pin: 24V
22pin : 30V 24pin : 17V
GND : 1, 17, 23 pins


All errors of those powers should be within 5% or 10%.


!" Action Notes for failures


Check the connection of power supply connector.
If the failures continue after checking, replace SMPS.






SM - OAK (English) 5 00-06-09

5
SECTION Basic Test
Item : Time interval of power supply between ERONT B/D and MAIN B/D
Symptom : Malfunction of initial display at ERONT B/D or failure of Power-on sequence

!" After stabilization of Com at ERONT B/D, check the power supply of MAIN B/D. It checks
whether Com controls power of MAIN B/D normally.

!" The timing of Eront B/D power 5VE and 5V power controlled by Eront B/D is shown down
below. Then, the key point is the interval of two signals.









5VE $






5V $





!" Check Point :

5VE : Circuit Diagram Page07/JP200,Pin7
5V : Circuit Diagram Page07/U200,Pin1




!" Eailure Causes & Action notes

It is the case of improper control by ERONT B/D, so replace ERONT B/D or, check power
supply again as Basic Item Test.





SM - OAK (English) 6 00-06-09

6
SECTION Basic Test
Item : SAA7219 CLOCK(13.5MHz) and SAA7215 CLOCK(40.5MHz)
Symptom : System not acting
Or intermittently acting.

!" SAA7219 CLOCK uses VCXO as system clock.
!" The internal clock of SAA7219 uses several clocks by generating external 13.5MHz system
clock. This test checks that one of them, 40.5MHz, is generated.
!" SAA7215 gets 40.5MHz system clock, and then generates and uses system clock of 27MHz and
81MHz. This test checks whether 27MHz system clock is generated.




Check Point : Circuit Diagram
13.5MHz $ Page 10/E210,Pin3




Check Point : Circuit Diagram
40.5MHz $ Page10/ U220,Pin91






Check Point : Circuit Diagram
40.5MHz $ Page16/ U290,Pin168




Check Point : Circuit Diagram
27MHz $ Page16/ U290,Pin126





!" Eailure Causes & Action Plan

If the 13.5MHz is acting unstably, it means that VCXO or SAA7219 is damaged. Replacement of
parts is required. Because 40.5 MHz clock and 27MHz clock is not generated from inside of the
chip, soldering or the chip is considered as a cause.
Be cautious, when replacing components. The static of soldering may damage the components.
Check the general install, soldering condition, wrong or reverse insertion of parts..



SM - OAK (English) 7 00-06-09

7
SECTION Basic Test
Item : SAA7219 RESET and SAA7215 RESET
Symptom : SAA7219 not Acting
SAA7215 not Acting

!" This part has less probability of failure but check this reset timing when a failure comes out.

!" SAA7215 Reset is using SAA7219 PIO. Therefore SAA7219 RESET comes out after SAA7219
RESET.








SAA7219 Reset #






SAA7215 Reset #









!" Check Point
- SAA7219 Reset : Circuit Diagram Page10/U221, Pin 3
- SAA7215 Reset : Circuit Diagram Page16/U290, Pin 145

!" SAA7219 Reset is connected with ELASH and CXD1957AQ.


!" Eailure Causes & Action Plan

In case of SAA7219 Reset timing failure, check the wrong insertion of elements and soldering
condition.
In case of malfunction of SAA7215 Reset check the error of SAA7219.





SM - OAK (English) 8 00-06-09

8
SECTION Basic Test
Item : System Reset and System Clock
Symptom : Power On not Reset
Cannot write Elash Memory

!" System clock 13.5Mhz should be in the stable condition when the System Resets or Power On
resets.
However, at the moment of Power On Reset, the poor VCXO can make clock unstable until the
System Reset is off.

Eor the test of this item measure the following wave when Main Power On after Off, and check
the measured wave is maintained.








SAA7219 Reset $





13.5M Clock $




!" Check Point
- SAA7219 Reset : Circuit Diagram Page10/U220,Pin3
- 13.5M Clock : Circuit Diagram Page10/E210,Pin3





!" Eailure Causes & Action notes

In this case, one of the causes is poor VCXO. Replace parts.
Otherwise, check the install and soldering condition, etc.








SM - OAK (English) 9 00-06-09

9
SECTION System Test
Item : Test of ELASH1 Movement
Symptom : MPEG Play not acting though no Eailure on Basic Test Items

!" When Basic Test Items have no faults and system is not acting, check ELASH1containing
program code. In normal case, ELASH1shows control signal continuously as below.






40.5MHz Clock Input $





ELASH1 CE# $



ELASH1 OE# $







!" Check Point :

40.5MHz : Circuit Diagram Page12/U255,Pin2
CE# : Circuit Diagram Page12/U255,Pin36
OE# : Circuit Diagram Page12/U255,Pin38

!"Eailure Causes & Action notes

If the above signal is not acting, examine the short of soldering error, cold-soldering, etc.
When the soldering has no error, check the basic test items, Data Bus and Address Bus.


Replacing Chip should be the last option.



SM - OAK (English) 10 00-06-09

10
SECTION System Test
Item : Test of ELASH2 Movement
Symptom : MPEG Play not Acting

!" When no errors are found even after Basic Test and System is not acting, check ELASH2
containing channel data and Program constants. When the System is acting normally, ELASH2
shows control signals continuously as below.
!" The below picture shows the similar timing to that of ELASH1






ELASH2 CE# $







ELASH2 OE# $







!" Check Point :

CE# : Circuit Diagram Page13/U260,Pin26
OE# : Circuit Diagram Page13/U260,Pin28

!"Eailure Causes & Action notes

If the above signal is not acting, examine the short of soldering error, cold-soldering, etc.
When the soldering has no error, check the basic test items, Data Bus and Address Bus.

Replacing Chip should be the last option.



SM - OAK (English) 11 00-06-09

11
SECTION System Test
Item : Test of MPEG GRAPHICS SDRAM Movement
Symptom : MPEG Play not Acting without any errors at Basin Test Items

!" When no errors are found after Basic Test and system is not acting, it is necessary to check
MPEG GRAPHICS SDRAM of SAA7215 as Main Data and MPEG Graphic domain.

!" When the CSSDN signal of SAA7219 is low, MPEG Graphics SDRAM of SAA7215 is
selected. SAA7219 detects DTACK signal and end Bus Cycle. These two normal signals show
continuously as below.






7215DTACK $







CSSDN $





!" Check Point :

7215DTACK : Circuit Diagram Page16/U290,Pin203
CSSEN : Circuit Diagram Page16/U290,Pin202

!"Eailure Causes & Action notes:

If the above signals are not acting, examine the Data Bus and Address Bus. If this test found
No problem, examine the short of soldering error, cold-soldering, etc.

Replacing Chip should be the last option.



SM - OAK (English) 12 00-06-09

12

SECTION System Test(Only IRCI-5400)
Item : Test of I-Chip and Irdeto SC
Symptom : TS by-pass or Descramble failure by I-Chip or Irdeto SC malfunction


!" I-Chip function as CI in IRCI-5400. Shortly I-Chip plays as a CAM of Irdeto stream and
Descramble can be conducted by Irdeto SC.

1) TS bypass no acting
- In the case of Eree channel, TS is planned to be By-pass when it is power on by the
initialization of I-Chip. If the I-Chip has badness, malfunction of MPEC display or screen may
be happening as I-Chip output TS is broken.
- Check this thing TS input/output of I-Chip (U170)
2) Descramble no acting by SC
- Irdeto descramble has another format different from normal of ISO7816-3 format.
- Eirstly check the Crystal output of 12MHz.







(1) :12MHz crystal ouput
(Page 10/U224,Pin4)



(2) : Bead ouput,
TDA8004 input
(Page28/U700,Pin24)








-Two symptom appears as above
)3`rd oscillation : 36MHz oscillation by inferiority of crystal or Load Cap attachment
)non oscillation Clock : This is caused by inserting failure of Crystal, 74HC04, Cap

SM - OAK (English) 13 00-06-09

13
SECTION System Test
Item : Sequence of PCMCIA CI Eunctional Test
Symptom : Transport Stream De-scramble or CAM Initialization failure caused by CI

!" The test related with PCMCIA is necessary to understand the below Sequence and System
Control flow.

1) Card Insertion : When CAM is inserted, CD Pin contact at CI Slot makes signal.
- When the Card is inserted, signal of C1CD1and C1CD2 is converted from high level to
low level. It should be detected by CXD1957.
2) CI Power Supply : After Card Detection and a while(more than 50 ), 5V Power is
supplied.
- The Rising Time of Power should be about 300. In case of delay, initialization of
Card makes trouble, so check it cautiously.
3) TS Input Buffer Enable & Card Enable : Activating 300ms later after CI Power supply
4) CAM Reset : CAM Resets at the same time of Card enable and High voltage section
should be maintained for more than 10
5) Card Access : Card should be accessed 200ms later after Reset Off.

The below graph is PCMCIA Sequence Timing graph.
















!" CI Control IC is SONY CXD1957AQ to control One Chip 2-Slot.

1) CI IC Reset is using the same reset as SAA7219 (check Reset signal)
2) CI DTACK is generated through being combined with DTACK of MPEG Decoder
(SAA7215).



SM - OAK (English) 14 00-06-09

14
SECTION System Test
Item : PCMCIA Common Interface
Symptom : Eailure of Transport Stream De-scramble or CAM Initialization by CI

!" It is necessary to check PCMCIA sequence timing.



C1CD1 $ Check Point: Circuit Diagram
Page04/ U106A,Pin1


Check Point: Circuit Diagram
CARD POW $ Page04/ U102A,Pin1






CARD POW $ Check Point: Circuit Diagram
Page04/ U102A,Pin1



CAS1SIG $ Check Point: Circuit Diagram
Page04/ U100,Pin1






CAS1SIG $ Check Point: Circuit Diagram
Page04 /U100,Pin1



CAS1RST $ Check Point: Circuit Diagram
Page04/ U103,Pin20



!" Eailure Causes & Action notes

When the above signal is not acting, it is necessary to check the signal according to the
generating route of interrupt by inserting and ejecting Card.

The flow of TS(Transport Stream) refers at MPEG Item.


SM - OAK (English) 15 00-06-09

15
SECTION MPEG and A/V Test Item
Item : TS Stream
Symptom : Power On but System not Acting

!" TS signal from EEC B/D goes to SAA7219. It is very important to trace this route.






TS Valid $




TS STR $



TS CLK $







!" Check Point :

TS VLD : Circuit Diagram Page08/JP333,Pin14 Page04/U101A,Pin4 Page06/U165,Pin7
TS STR : Circuit Diagram Page08/JP333,Pin15 Page04/U101A,Pin2 Page06/U165,Pin4
TS CLK : Circuit Diagram Page08/JP333,Pin16 Page04/U101A,Pin6 Page06/U165,Pin9





!" Eailure Causes & Action notes

The above Check Points are sequential. Among Check Points, the signals pass several signal
routes. If the signals show different shapes from the above graphs, find the position by
referencing Circuit Diagram.

If MPEG Play is not acting , check whether the soldering condition such as cold-soldering makes
signal error at TS Data Line.





SM - OAK (English) 16 00-06-09

16
SECTION A/V Test Item
Item : 7219 A/V Strobe
Symptom : MPEG Play not Acting

!" This test checks that SAA7219 de-multiplexes MPEG TS. If the digital A/V signals, such as
ASTROBE, VSTROBE, and AVD|7..0] are checked, SAA7219 is acting normally.








ASTROVE $







AVD0 $





!" Check Point :

ASTROVE : Circuit Diagram Page10/U220,Pin94 Page16/U290,Pin164
AVD0 : Circuit Diagram Page10/U220,Pin103 Page16/U290,Pin155


!" Eailure Causes & Action notes

ASTROVE is a similar signal to VSTROVE.

AVD|7..0] are almost same.

If MPEG Play is not acting after checking above signals, check each 8Bit Line AVD|0..7] and
examine A/V MPEG TS Data from TDA8044ADH.

Sometimes, the poor TDA8044 makes that SAA7201is not acting.





SM - OAK (English) 17 00-06-09

17
SECTION MPEG and A/V Test Item
Item : A/V Output
Symptom : Audio Signal not Generating.

!" If the system is normal, but Audio signal does not appear by TV SCART, VCR SCART and etc.,
check Digital Audio Input of UDA1320.

!" If Digital Audio signal is normal, trace the route of Analog Audio signal from UDA1320 Output
to SCART, and check the signal.




Check Point: Circuit Diagram
Page22/ U400,Pin6
SCLK(8MHz) $



Check Point: Circuit Diagram
Page22/ U400,Pin1
ACLK(3MHz) $







Check Point: Circuit Diagram
Page22/ U400,Pin2
AWS(48KHz) $



Check Point: Circuit Diagram
Page22/ U400,Pin3
ADATA $




!" Eailure Causes & Action notes

The output level and characteristic of Audio is sensitive to R and C values. Check the soldering
condition or R and C values.

The signal levels are generated by the position of the circuit.



SM - OAK (English) 18 00-06-09

18
SECTION MPEG and A/V Test Item
Item : DAC TDA1320 Audio Output
Symptom : Audio signal not Generating.

!"If Audio signal is not generating in SCART and Phone Jack, check on two Audio DAC.
U400 and TDA1320 generate audio signal to TV-SCART and Phone Jack.
U401 and TDA1320 generate audio signal to VCR-SCART.

!" The output level and characteristic of Audio is sensitive to R and C values. Check the soldering
condition or values. Check R and C values when the certain part causes a problem.

!" The picture down below shows the output wave using 1KHz Tone signal.







Audio Left $




Audio Right $





!" Check Point :

TAOL : Circuit Diagram Page22/U400,Pin14
TAOR : Circuit Diagram Page22/U400,Pin16


!" Eailure Causes & Action notes

If the output of Audio DAC is normal, trace each circuit to find the problem spot.

Like Video, Audio is a part of analog, so most failures are probably found in soldering and poor
components.


SM - OAK (English) 19 00-06-09

19
SECTION MPEG and A/V Test Item
Item : Video Output
Symptom : Video signal not generating.

!"If the system is normal, but Video signal does not appear by TV SCART, VCR SCART and etc.,
check Digital Audio Input of STV6411AD.

!" The input of STV6411AD has CVBS, SVHS, R, G and B output respectively. The picture shown
down below is the output pattern by using 75% color bar signal.




Check Point: Circuit Diagram
CVBS $ Page23/ U420,Pin36



Check Point: Circuit Diagram
Red $ Page23/ U420,Pin42







Check Point: Circuit Diagram
Y(Luminance) $ Page23/ U420,Pin36



Check Point: Circuit Diagram
C(Chromaticity) $ Page23/ U420,Pin40







!" Eailure Causes & Action notes

If all outputs o0f U420 are normally generated, the error of each signals comes from the circuit.
To fix the error, trace the circuit related SCART, and check the waves of each part.

The output levels on each circuit diagram are different. The level in general is marked on the
Circuit Diagram, so refer to it if necessary.



SM - OAK (English) 20 00-06-09

20
SECTION Channel Test
Item : CHANNEL PART Servicing ELOW
Symptom : Items to be checked in case of CHANNEL PART Servicing

Locking of signal is made by TUNER 7 TDA8044, so this section will describes each part in circuit
then symptom of easy checking.

1. Test POINT(Circuit Diagram Page01, Page02)
1) TUNER : check internal power 5V
( 4.75 ~ 5.25v )
2) TUNER TUNING VOLTAGE : check tuning voltage 30V and RIPPLE
. ( 28.5 ~ 31V / MAX 50mV )
3) Check whether LNB POWER CONTROL signal and LNB POWER is generated
( LNB POWER CONTROL SIGNAL $ EN, VSEL )
( LNB POWER $ LNBA )
4) Check whether 22KHz TONE wave is generated
( 400~800mV AMPLITUDE duty 45~55% )
5) Check 479.5MHz CARRIER VCO INPUT voltage of TUNER
( Check if it is 2.4 ~ 2.6v )
6) Check TUNER OUTPUT I/Q voltage and wave.
( Check if the voltage is 1.9 ~2.0v and the wave is about 600mVpp )
7) Check TDA 8044 power 3.3v
( Check if it is 3.2 ~ 3.4v )
8) Check the TDA 8044 CLOCK is 4.0625MHz.
9) When power is on, check 12C BUS LINE which generates signal by initialization of
TUNER and TDA8044.
10) Check 8044CLK and 8044VLD signal.
( BCLK is approx. 5.4MHz and VILD is approx. 26KHz. They vary according to the
SYMBOL RATE )
11) Check if PBAD signal is 3.3V HIGH.
( 3.3 Volt HIGH should be maintained while 8bit DATA is being generated. )
( If LOW or Negative Width, LOCK may not be working or broken. )




Each of 11 items above is described at each chapter about symptoms, causes and action notes.







SM - OAK (English) 21 00-06-09

21
SECTION Channel Test
Item : 1,2) TUNER working voltage and VT voltage
Symptom : LOCKING Eailure.
!" 5V, given to TUNER Internal Working Voltage. It is one of the causes of TUNER Internal
Erequency Change when the RIPPLE or the voltage is shaking. If the TUNIG VOLTAGE 30V is
abnormally low and RIPPLE is more than 200mV, TUNER Internal Working voltage generates
the noise of 479.5MH IE wave by living on the Local Erequency which is generated by TUNER
Internal.





TUNER(5VT) $
Check Point: Circuit Diagram
Page01/ TN1,Pin8












TUNER(30V) $
Check Point: Circuit Diagram
Page01/ TN1,Pin7











!" Eailure Causes & Action notes


After checking the soldering condition and REG. IC Input voltage, replace 7805 and SMPS.



SM - OAK (English) 22 00-06-09

22
SECTION Channel Test
Item : 3) 13.5 / 18V LNB Working Voltage Eailure.
Symptom : LOCKING Eailure.
!" 13.5/18V, which is carried to LNB through a Tuner loop, is LNB internal voltage power. It is
used as Input voltage of LNB Internal REG. In case of LNB DUAL POLA, 13.5/18V is also
used during the polarization conversion of Horizontal/Vertical.

!" LNB POWER CONTROL SIGNAL

18V $ VSEL(HIGH), EN(HIGH)
13.5V $ VSEL(LOW ), EN(HIGH)







LNB POWER(18V) $








LNB POWER(13V) $








!" Check Point
LNB POWER : Circuit Diagram Page01/U2,Pin3
VSEL : Circuit Diagram Page01/U2.Pin4
EN : Circuit Diagram Page01/U2,Pin5



!" Eailure Causes & Action notes

Check the input power of U2 and NBP15SP. If the input power is normal, replacement of the
chip can be considered.


SM - OAK (English) 23 00-06-09

23
SECTION Channel Test
Item : 4,5) 22KHz TONE & CARRIER Voltage
Symptom : LOCKING Eailure.
!" 22KHz TONE is used for selecting HIGH Band (1150 2150MHz) and LOW Band (950
1150MHz). CARRIERVCO voltage makes 479.5MKz in QPSK DEMOULATOR. 479.5MHz
is used LOCAL OSC for I/Q signal.

!" The picture below shows the values when the actual LNB is not loaded. If it is loaded,
Amplitude should be 400~800mV and duty should be 45~55%.







22KHz ( INPUT) $







22KHz (OUTPUT) $







!" Check Point

22KHz (INPUT) : Circuit Diagram Page01/U2,Pin9
22KHz(OUTPUT) : Circuit Diagram Page01/U2,Pin3



!" Eailure Causes & Action notes

The incorrect amplitude and duty is caused by cold-soldering and wrong insertion. Check the
soldering condition.

TUNER 5V is divided into 2.6V by R4 and R5. Check U18 7805 voltage and resistance value
of R4 and R5.




SM - OAK (English) 24 00-06-09

24
SECTION Channel Test
Item : 6,7) TUNER OUTPUT I/Q & TDA 8044 Working Voltage
Symptom : LOCKING Eailure
!" I/Q signal from Tuner Output is Analog wave through QPSK Demodulator in TUNER internal.
It is used A/D CONVERTOR input of next port.
3V, which is supplied CHANNEL PART, is used the working power of TDA8044 and is
separated as a pattern.

!" I/Q wave has approx. 600mVpp and 1.7V ~1.9Vto BIAS in TDA8043.



I $ Check Point: Circuit Diagram
Page01/ TN1,Pin17



Q $ Check Point: Circuit Diagram
Page01/ Tn1,Pin16









3.3V $ Check Point: Circuit Diagram
Page02/ All power of U20









!" Eailure Causes & Action notes

In cases of the BAIS voltage low or failure, check the soldering at TDA8044 power and
components around TDA8044.




SM - OAK (English) 25 00-06-09

25
SECTION Channel Test
Item : 8,9) TDA8044 65MHz CLOCK & I2C BUS
Symptom : LOCKING Eailure
!" 65MHz external Clock makes A/D Clock through internal divider and uses internal
Clock(TDA8043 uses it). Check the wave from X-TAL.
!" I2C BUS is generated by SAA7219 for controlling TUNER and TDA8044. 12C BUS is used for
Data Setting in CHANNERL LOCKING and STATUS READING.






Check Point: Circuit Diagram
Page02/ Y20/Pin1,2
CLOCK $
(4.0625MHz)








Check Point: Circuit Diagram
Page02/ U20,Pin53
SDA0 $


Check Point: Circuit Diagram
Page02/ U20,Pin52
SCL0 $




!" Eailure Causes & Action notes

If the wave is different from above, cold-soldering or wrong insertion is the main cause. If
unlocking happens often, make sure to use the frequency counter. Since X-TAL oscillating can
deviate from /- 30ppm SPEC.

If there is no signal in I2C BUS LINE, mostly Pins are short or system down. Re-soldering is
necessary.


SM - OAK (English) 26 00-06-09

26
SECTION Channel Test
Item : 10, 11) TDA8044 OUTPUT Signal (1)
Symptom : LOCKING Eailure
!" TDA8043 output signal is divided into TDA8044 Output Bit Clock(5.4 MHz),
VALID( 25.8KHz ), 8BIT DATA, PBAD (LOW). It varies according to the setting of symbol
Rate. Each signal is generated when TDA8044 internal locking is all setup.
The order of TDA8044 internal lock is ;
1. A/D CONVERTOR 2. DE-PUNCTURING 3. VITERBI
4. DE-INTERLEVING 5. RS SOLOMOM 6 DE-RANDOMIZER

!"TDA8044 Status must be check for locking of each step, but it can be supposed that locking is
successful if TDA8044 56, 57,58 PIN(DEMOD LOCK, VITERBI, R-SOLOMOM) IS 3.3v
High.





TS CLOCK $





TS DATA $







!" Check Point
TS CLOCK : Circuit Diagram Page02/U20,Pin28
TS DATA : Circuit Diagram Page02/U20,Pin29
8044D|7..0]

!" Eailure Causes & Action notes

TS DATA should be changed into 8044D|7..0] when BIT CLK is POSITIVE-EDGE.
BIT CLOCK( R42) and 8BIT DATA is 8044 OUTPUT, and their DATA is synchronized with
BIT CLOCK and generated.

If BIT CLOCK and DATA are not coming, check the items mentioned above and replace
TDA8044 after re-soldering. If TDA8044 DATA is correct but Locking is fails, check carefully it
because it is caused mainly by short of the rear part at 8Bit data LINE Resistor.



SM - OAK (English) 27 00-06-09

27
Classification SMART CARD CHECK
Item: SMART CARD INTEREACE
Symptom: SMART CARD is Not Realized or
SMART CARD is realized, but the picture is Not Descrambled due to data disturbance

The SMART CARD I/E signal contains CARD DETECT, DATA I/O, RESET, VCCENABLE,
CARD CLOCK. Each of these functions as follows:

1) CARD DETECT: Informs SAA7219 whether the Smart Card is inserted into the SMART
CARD SOCKET or not
2) DATA I/O: Serial Communication Signal ( BIDIRECTION)
3) RESET: Sent to the SMART CARD in order to initialize it
4) VCCENABLE: Enables to supply power to the SMART CARD
5) CARD CLOCK: SMART CARD Operation Clock.

| Procedure for SMART CARD Communication ]
1. Inserting the SMART CARD
1) Insert the Smart Card into the Smart Card Slot.
2) SAA7219 realizes the SMART CARD is inserted and CLOCK is output.
- CLOCK is about 12MHz ( This value doesn`t comply with ISO7816-3)
- The effective clock of SMART CARD is 6 MHz. This value equals to half of the clock
that is generated by a 12 MHz of oscillator.
3) Supply power to the Smart Card by activating VCCENABLE PIN
4) To initialize the SMART CARD, SAA7219 switches Reset L` to Reset H`.
5) SERIAL DATA Communication runs.
2. Extracting the SMART CARD from the IRD
Do in reverse order to the above.

Countermeasures
!" Check that the supply voltages (3.3V and 5V) are normally applied from the main board to the
smart board.

!" When the Smart Card is inserted, check the voltage (0V,LOW)of pin 4 of JP700 (connector) goes
up to 3.3V (HIGH). If this operation is not properly done, it results in abnormal communication
(because CPU can`t realize whether the card has been inserted). In this case, check the connector
is correctly connected.

!" When the above function is normal, check the voltage of pin 7 of JP700 (3.3V, HIGH) goes
down to 0V LOW. If this operation is not properly done, the product doesn`t operate because the
power is not applied to the SMART CARD. In this case, check the connector is correctly
connected and monitor each signal line with using an oscilloscope.

!" Check each of the other signals normally functions. (Use an oscilloscope).

!" The Smart Board is not complex, so any particular defect except assay related ones doesn`t
happen on the board.





SM - OAK (English) 28 00-06-09

28
Classification Channel Check (CI-5100C,VA-5200C only)
Item: Channel Part Troubleshooting
Symptom: Items to be checked when troubleshooting the Channel part
Since Tuner and BCM3118B are linked together and locked, check all controlled signals relating to
Channel Part Troubleshooting.

2. Use an oscilloscope. (See the schematic diagrams to pages 29~30 )
2) Check the operation power (5V) of Tuner
( It must be within 4.75 ~ 5.25V)
3) Check the operation power (12V) of uPC2798G.
(It must be within 11 ~ 13V)
4) Check the power (5V) of BCM3118B.
(It must be within 5.25 ~ 5.25V)
5) Check the BCM3118B input signal level.
(Make sure the signal level is about 750 mV at 2.5 V of DC level)
6) Check XTAL (14MHz, BCM3118B clock source) oscillates.
7) When switching into Power ON, check the I2C-bus line that is produced when initializing
TUNER and BCM3118B.
8) Check 3118D|0..7], 3118BCLK, 3118VLD, 3118STR.
(3118BCLK varies between 0.75~7 MHz and the value depends on SYMBOL RATE and
QAM constellation. 3118VLD must keep HIGH during the output of 8 bit data.
3118D|0..7] is latched at the rising edge of 3118BCLK.

2. Use a spectrum analyzer. (See the schematic diagrams to pages 29~30)
9) Check the output spectrum of TUNER.
(At 36.125 MHz, the signal that its bandwidth is less than 8 MHz must exist.
9) Check XTAL (29.125MHz) oscillates.
(If the probe is placed on XTAL in normal condition robe, locking is released and therefore
No Picture` may happen)


Causes and appropriate countermeasures by each check item will be described in each chapter.



SM - OAK (English) 29 00-06-09

29

Classification Channel Check (CI-5100C,VA-5200C only)
Item : 1,2,3) The input voltage (5V & 12 V) of TUNER, uPC2798G and BCM3118B fails
Symptom :Locking fails.
!" 5V that is supplied to TUNER, uPC2798G and BCM3118B is an operating voltage. It can
cause a locking failure because it fluctuates the internal frequency of Tuner when the voltage
ripples and trembles.








5V $: Measurement:
m See the schematic diagram
to Page29/U2, Pin 0,7,
U3, Pin 4,
Page 30/U5, Pin 58, 64, 65




12V $





12V Measurement : See the schematic diagram to page29/U1,Pin 3

!" Cause & Countermeasure

After checking the soldering status, check the In/Out voltage of REG. IC and (if necessary)
replace 7805, 7812, SMPS.

SM - OAK (English) 30 00-06-09

30

Classification Channel Check (CI-5100C,VA-5200C only)
Item: 4) The BCM3118B input signal level doesn`t reach 750 mV.
Symptom: Locking Eails.
!" Even though the input voltage of the internal ADC of BCM3118B is 1 Vpeak-to-peak, the input
signal level is set at 75% of the input voltage to prevent the ADC saturation. Therefore when the
RE signal input is within normal range, the BCM3118B input level must be 750100 mV peak-
to-peak.

!" BCM3118B Input Signal Specification
Peak-to-peak voltage $ 750 mV
DC bias $ 2.5 V



!" Measurement
BCM3118B (U5) Input Signal Level $ See the schematic diagram page30/U5, pins 67, 68
BCM3118B (U5) Output Control Signal Level $ See the schematic diagram page30/U5, pin 55
Tuner (U2) Output Signal$ See the schematic diagram page29/U2, pins 10, 11
Tuner (U2) Control Signal$ See the schematic diagram page29/U2, pin 1
29.125 MHz XTAL (Y1) $ See the schematic diagram page29/U3, pins 9, 10
14 MHz XTAL (Y2) $ See the schematic diagram page30/U5, pins 51, 52

* Check 5V, 12V first and make sure the RE signal is correctly input.
Check the Tuner Output Spectrum (item 8). If no output signal exists at 36.125 MHz, check the
voltage of Tuner (U2) pin 1. If the voltage is 0V, check the voltage of U5 pin 55 is also 0V. IE the
voltage of U5 pin 55 is 0V, replace Y1 (if Y1 does not oscillate) or U5 (if Y1 oscillates) after checking
XTAL(Y1). But if the voltage of U5 pin 55 is not 0V, check the soldering status at R22, 23, 24.
If the Tuner Output Spectrum doesn`t exist even though the voltage of U2 pin 1is not 0V, replace
the tuner (U2).
If the BCM3118B input signal level is not 750100 mV even though the Tuner Output Spectrum
exists. Check 29.125 MHz XTAL(Y1) oscillates according to item 9.
If XTAL does not oscillate, replace XTAL(Y1). And if XTAL oscillates , replace U3.





SM - OAK (English) 31 00-06-09

31

Classification
Channel Check (CI-5100C,VA-5200C only)
Item : 5) 14MHz XTAL (clock source of BCM3118B) fails in oscillation
Symptom: Locking Eails
!" 14MHz XTAL(Y2) functions as the Main Clock of BCM3118B (U5). If this XTAL doesn`t
oscillate, the EEC board will NOT operate at all.
!" The output waveform of Y2 is as shown in the figure below. 14 MHz ( INPUT) and 14 MHz
(OUTPUT) apply to the waveforms that are measured at U5 pin 51 and 52 .

14 MHz ( INPUT) $


14 MHz (OUTPUT) $

!" Measurement

14 MHz (INPUT) : See the schematic diagram page30/U5, pin 51
14 MHz (OUTPUT) : See the schematic diagram page30/U5, pin 52

!" Cause & Countermeasure

- The oscillation of X-TAL may deviate from 50ppm standard. Check the oscillation of X-
TAL with using the frequency counter. If it deviates from 50ppm, replace XTAL.
- If the amplitude and duty of waveforms fail, replace Y2. If XTAL doesn`t oscillate after
replacing Y2, replace the capacitors (C26 and C29) around XTAL with 16 pE ones and
check again whether XTAL oscillates. If it does not oscillate nevertheless, check 5V
(supply voltage) of U5 and then replace U5.


SM - OAK (English) 32 00-06-09

32
Classification Channel Check (CI-5100C,VA-5200C only)
Item: 6) BCM3118B I2C bus signal fails
Symptom: Locking Eails

!" I2C BUS signal is generated via SAA7219 and it controls BCM3118B. It is usually used to set
the required data during CHANNEL LOCKING and also used to read STATUS. The tuner I2C
BUS signal is generated via BCM3118B pins 82(SCL) and 83(SDA) and it is used to select the
QAM signal input frequency.
!"
BSDA: See the schematic diagram page30/ U5, pin 39
BSCL: See the schematic diagram page30/ U5, pin 40















BSDA: See the schematic diagram page30/ U20, pin 83
BSCL: See the schematic diagram page30/U20, pin 82


!" Cause & Countermeasure

If there is no signal in I2C BUS LINE, it is assumed that that happens because the associated
pins are shorted or the system goes down. So re-solder them.


SM - OAK (English) 33 00-06-09

33

Classification Channel Check (CI-5100C,VA-5200C only)
Item: 7) BCM3118B output signal fails
Symptom: A/V Decoding Eails
!" BCM3118B OUTPUT includes 3118BCLK , 3118VLD, 3118D|0..7], and 3118STR. The
frequency depends on the set symbol rate and QAM constellation. Each signal is generated when
locking happens inside BCM3118B. The locking inside BCM3118B proceeds as follows.
2. AGC 2. CLOCK Sync 3. Adaptive Equalization 4. Carrier Sync
5. DE-INTERLEVING 6. R-S decoder 7. DE-RANDOMIZER
Whether each phase is locked can be checked by reading the BCM3118B register.
Externally, whether all phases (from AGC to DE-RANDOMIZER) are locked can be only
checked via pin 36( PERROR) locked. (If PERROR is 5V, it means all phases are LOCKED.)






3118BCLK $







3118D|0..7] $




!" Measurement
3118BCLK : See the schematic diagram page30/JP3, pin 9
3118D|0..7] : See the schematic diagram page30/ JP3, pins |12..19]
3118VLD : See the schematic diagram page30/ JP3, pin 11
3118STR : See the schematic diagram page30/JP3, pin 10
PERROR : See the schematic diagram page30/U5, pin 35


!" Cause & Countermeasure
TS DATA must be changed when performing 3118BCLK POSITIVE-EDGE via 3118D |7..0].
3118BCLK and 8 bit data are synchronized to 3118B OUTPUT and DATA to BYTE
CLOCK(3118BCLK ) and they are output.
If BYTE CLOCK and DATA are not output, check the above measurement items and then
replace PR1,/2/3 or 3118 after re-soldering. There are cases where 3118B DATA is correct but it can`t
be locked. Those cases may happen because the second part of 8Bit data line resistance is
SHORTED . Therefore, check carefully with your eyes.



SM - OAK (English) 34 00-06-09

34
Classification Channel Check (CI-5100C,VA-5200C only)
Item: 8) TUNER output spectrum fails
Symptom: Locking Eails
!" The tuner output signal is IE signal. Eor cable TV, the IE signal is 36.125 MHz. The IE output
level is about 10 dBm. (Use a spectrum analyzer to detect whether the signal exists. It is hard to
detect whether the signal exists by using an oscilloscope.)

!" Spectrum analyzer setting:
Center Ereq: 36 MHz, Ereq span : 20 MHz
VBW: 1 kHz, RBW: 30 kHz
Ref level : -50 dBm












36.125 MHz




!" Measurement

IE : See the schematic diagram page29/U2, pin 11
IE - : See the schematic diagram page29/U2, pin 10


!" Cause & Countermeasure

Check the RE signal and POWER are properly input. And check the voltage of Tuner (U2) pin 1.
If the voltage is 0V, check the voltage of U5 pin 55 is also 0V. If the voltage of U5 pin 55 is
0V, check XTAL(Y1) and then replace Y1 (if Y1 doesn`t oscillate) or U5(if Y1 oscillates). If the
voltage of U5 pin 55 is not 0V, check the soldering status at R22, 23, 24.
If the tuner output spectrum doesn`t exist, even though the voltage of U2 pin 1 is not 0V, replace
TUNER(U2).



SM - OAK (English) 35 00-06-09

35
Classification Channel Check (CI-5100C,VA-5200C only)
Item: 9) 29.125MHz XTAL fails in oscillation
Symptom: Locking Eails

!" 29.125 MHz XTAL is used to down-convert 36.125 MHz of the center frequency of IE signal to
7 MHz. If 29.125 MHz XTAL doesn`t oscillate, only noise is input to BCM3118B. Because the
XTAL output signal has very small amplitude, use a spectrum analyzer to detect whether it
oscillates. (The oscilloscope or frequency counter is not suitable.) It should be noted that No
Picture may happen because locking is released by accessing the probe to XTAL in normal
condition.

!" Spectrum analyzer setting:
Center Ereq: 29.125 MHz, Ereq span : 1 MHz
VBW: 1 kHz, RBW: 30 kHz
Ref level : -60 dBm













29.125 MHz


!" Measurement

See the schematic diagram page29/U5, pin 10


!" Cause & Countermeasure

Check 12V POWER is normally supplied. If 29.125 MHz spectrum doesn`t exist, even
though power is supplied, replace XTAL(Y1) . It may be damaged.


1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
(DIP-500)
All locations are from 1 to 19 in this page.
Heat Sink
(SY-200)
From/To TDA8044 :
SH2
2
10
14
()
()
()
8
9
13
17
()
()
()
[==]
7
12
16
()
()
()
()
[==]
6
11
15
()
()
()
1
5
TN601 PIN
ASSIGNMENT
HEAT-SINK
Tuner 1.0
Channel Part
OAK (IRCI-5400, CR-5510 CRCI-5500)
Custom
1 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
TUNER_I
TUNER_Q
SDA0
SCL0
LOOP
+5VT
TUNER_AGC
LNB_22KCMD
LNB_STATUS
LNB_EN
LNB_SEL
+30V
+5VT
+8V
+8V
+5VT
+24V +17V
+3.3V
TN1
SD1228/LA MK2
6
9
10
12
8
17
16
5
13
15
7
11
1234
14
LNC B
SCL
SDA
AGC
+5V
I
Q
LNC A
PRESC1
VCO
+30V
AS
G
N
D
G
N
D
N
C
N
C
PRESC2
C1
104p
D2
P6KE30
1
2
R8 223
C8
104p
C9
10u/16V
R4
472
C5
104p
C6
47u/16V
R5
272
U1
LM7805
1
2
3
VI
G
N
D
VO
C3
104p
C4
104p/50V/2012
K1
SY-6-K
3
1
6
5
2
D1
KDS193
2
3
R1
472
Q1
KST4401
2
1
3
R6 472
C7
334p/2012
R7
471
+ C10
4.7u/50V
+
C11 10u/16V R12 122
R11
470
R10
472
U2
LNBP15SP
8
6
2
7
1
5
4
3
9
10
CEXT
GND
VCC2
ENT
VCC1
EN
VSEL
LNBA
EXTM
OLF
L2 271uH
R9 3R9
C14
104p/50V/2012
R13
681/2W(FORMING TYPE)
+ C13
10u/35V
+ C12
10u/35V
C15
224p
+ C16
47u/35V
+ C17
47u/35V
LOOP
TUNER_I
TUNER_Q
SDA0
SCL0
TUNER_AGC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
HEAT-SINK
All locations are from 20 to 49 in this page.
TO Tuner
TO TUNER
TO MAIN BOARD
To I-Chip
From 7219
From 7219
To Tuner
8044 QPSK 1.0
Channel Part
OAK (IRCI-5400, CR-5510, CRCI-5500)
Custom
2 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
+3.3VCO
+3.3VE
TUNER_Q
TUNER_I
LNB_STATUS
LOOP
8043VLD
8043STR
8043D1
8043D0
8043D2
8043D7
8043D6
8043D5
8043D4
8043D3
SDA0
SCL0
8043IRQ
TUNER_AGC
8043CLK
1
0
2
1
0
1
LNB_EN
8043RST
LNB_22KCMD
LNB_SEL
+8V
+3.3V
+3.3V
8043STR
8043CLK
8043VLD
8043D0
8043D2
8043D1
8043D3
8043D4
8043D6
8043D5
8043D7
8043RST
SDA0
SCL0
8043IRQ
+17V
+30V
+24V
+3.3V
+3.3V
+3.3V
+5VT
C21
104p/X7R/16V/2012
C20
104p/X7R/16V/2012
C30
270p/2012
Y20
4.0625MHz
R22
105
C31
270p/2012
L23
BEAD-601
C32
100u/6.3V
C33
104p
C34
104p
C25
682p
C27
682p
C45
682p
C44
682p
R27 470
R26 470
C43
682p
C42
682p
C41
682p
C40
100u/6.3V C39
103p
R23
100
C37
682p
C38
100u/6.3V
L22
BEAD-601
C35
682p
C36
100u/6.3V
L21
BEAD-601
PR20 470-4
1 8
2 7
3 6
4 5
PR21 470-4
1 8
2 7
3 6
4 5
R30 103
R29
470
R28 103
C26
682p
C23
104p/50V/2012
C24
682p
C22
104p/50V/2012
U20
TDA8044AH
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
V
S
S
A
V
R
E
F
I
V
D
D
A
V
D
D
C
L
X
T
-
I
N
X
T
-
O
U
T
V
S
S
C
L
V
D
D
V
D
D
V
S
S
D
2
2
N
C
N
C
V
A
G
C
N
C
V
D
D
V
D
D
O
U
S
T
DI
0
I
1
I2
I3
VSS
NC
NC
I4
I5
I6
Q0
VDD
Q1
Q2
Q3
Q4
VSS
Q5
Q6
VSS
VDD
PRESET
E3
E2
E1
E0
VDD
E5
E4
PBCLK
PD0
PD1
P
D
2
V
S
S
P
D
3
P
D
4
P
D
5
N
C
N
C
P
D
6
N
C
V
D
D
V
D
D
V
S
S
V
D
D
V
D
D
P
D
7
N
C
N
C
P
B
A
D
P
V
A
L
I
D
P
S
Y
N
C
VSS
SCL
SDA
INT
A0
RS_LOCK
V_LOCK
D_LOCK
VDD
VDD
TEST
TRST
TCK
SCLT
SDAT
VDD
VSS
VSS
TMS
TDO
TDI
VDD
VSS
VSSA_DIG
VDDA_DIG
VREFB
VSSA
QANA
VREFM
IANA
R25
472
JP10
52045-2445
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 170 to 189 in this page.
VCC : 28,
GND : 14
GND : 4, 15, 29, 40, 54, 65, 79, 90
VCC : 3,14,28,33, 39,53,59,66,78,91
IChip 1.0
IChip
OAK (ONLY IRCI-5400)
Custom
3 30 Wednesday, May 31, 2000
Title
Size Document Number Rev
Date: Sheet of
8043D[0..7]
5VD[0..7]
MA[2..12]
IRDETOD[0..7]
IRAM_D[0..7]
MA11
IRDETOD1
8043VLD
IRAM_WR
IRAM_A9
IRAM_D7
IRAM_D5
IRAM_RD
EMM_INT
IRDETOD7
IRDETOD6
IRAM_A0
IRDETOSTR
IRAM_D6
5VD6
5VD5
IRDETOD0
8043D3
ICHIPRST
IRAM_A6
8043STR
8043D7
IRAM_D3
IRDETOD5
IRAM_A7
IRAM_D6
MIN_MCLK
MA10
8043D0
IRAM_A4
MA4
MA2
IRAM_D0
IRAM_A12
8043CLK
IRAM_A5
IRAM_A3
IRAM_D0
MA9
MA8
8043D4
IRAM_D4
MA3
5VD4
IRAM_D3
IRAM_D1
IRDETOD4
IRAM_A8
ECM_INT
IRAM_A10
MA7
MA6
8043D6
WEN
IRAM_D4
IRAM_D2
5VD3
5VD2
8043D5
IRAM_A11
IRAM_D2
MA12
5VD7
IRDETOD3
IRDETOD2
IRDETOVLD
IRAM_D7
IRAM_D5
MA5
IRAM_D1
IRDETOCLK
IRAM_A1
LCAS
ICHIPCS1
CLK27M
IRAM_A2
5VD1
5VD0
8043D2
8043D1
+5V
+5V
+5V
+5V
+5V
R170
472
C173
104p
C170
104p
C179
104p
C177
104p
U171
KM68257C-20
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
20
22
27
11
12
13
15
16
17
18
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
CS
OE
WE
D1
D2
D3
D4
D5
D6
D7
D8
PR170
103-4
1
8
2
7
3
6
4
5
C172
104p
C171
104p
U170
SAS004
34
35
36
37
38
41
42
43
44
45
46
50
51
52
55
56
57
58
60
47
48
49
25
27
30
26
12
61
62
69
70
71
72
74
75
83
73
86
85
84
11
10
9
63
64
67
68
76
77
80
81
82
87
88
89
92
93
94
95
96
97
98
99
100
1
2
13
16
17
5
6
7
8
18
19
20
21
24
23
22
31
32
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AS
ALE
AOE
CS
DS/RW
RW/WR
IOMODE
RST
MPEG-IN0
MPEG-IN1
MPEG-IN2
MPEG-IN3
MPEG-IN4
MPEG-IN5
MPEG-IN6
MPEG-IN7
MTL BYTE EN
MPEG-IN-CLK
MPEG-IN-VALID
PKT IN START
PKT IN ERR
IRD CLK
MOD CLK
CLKSEL
RAM-AD0
RAM-AD1
RAM-AD2
RAM-AD3
RAM-AD4
RAM-AD5
RAM-AD6
RAM-AD7
RAM-AD8
RAM-AD9
RAM-AD10
RAM-AD11
RAM-AD12
RAM-D0
RAM-D1
RAM-D2
RAM-D3
RAM-D4
RAM-D5
RAM-D6
RAM-D7
RAM-RD
RAM-WR
XMM
XTRE
XTWE
MPEG-OUT0
MPEG-OUT1
MPEG-OUT2
MPEG-OUT3
MPEG-OUT4
MPEG-OUT5
MPEG-OUT6
MPEG-OUT7
MPEG-OUT-CLK
MPEG OUT VALID
PKT OUT START
INT0
INT1
C174
104p
C180
104p
C175
104p
C178
104p
C176
104p
IRDETOSTR 8043STR
ICHIPCS1
5VD[0..7]
MA[2..12]
8043VLD
CLK27M
8043D[0..7]
IRDETOD[0..7]
ECM_INT
8043CLK
ICHIPRST
IRDETOVLD
IRDETOCLK
EMM_INT
WEN
LCAS
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
# Pull-up of R120 is 472.
All locations are from 100 to 129 in this page.
# CXD1957AQ is
2-Slot mode
ECO A00103 : Prevent picture problem
when using Irdeto CAM
(U101 : 74HC244 => 74HCT244)
CI Slot 1 1.0
Common Interface
OAK (IRCI-5400, CRCI-5500, CI-5100C)
Custom
4 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
D
O
1
4
D
O
1
5
D
O
1
6
D
O
1
7
C
L
K
_
O
1
C
A
S
1
R
S
T
V
L
D
O
1
S
T
R
O
1
C
1
O
E
C
1
I
O
R
D
C
1
I
O
W
R
C
1
D
5
C
1
I
R
Q
C
1
D
4
C
1
W
E
C
1
D
2
C
1
W
A
I
T
C
1
D
7
C
1
C
E
C
1
D
6
C
1
D
1
C
1
C
D
2
C
1
C
D
1
C
1
D
0
C1CD1
C1CD2
DO14
DO15
DO16
DO17
DO13
DO12
DO11
DO10
D
O
1
3
D
O
1
0
D
O
1
1
D
O
1
2
C
1
R
E
G
C1REG
C1WAIT
C1CE
STRO1
VLDO1
CLK_O1
C1IRQ
C1OE
C1WE
C1IORD
C1IOWR
DO10
STRO1
VLDO1
CLKO1 CLK_O1
DO11
DO12
DO13
DO14
DO15
DO16
DO17
WEN
1957DTACK
MA16
C
1
O
E
C
2
D
1
C2WE
C
1
I
O
W
R
C1WE
C
1
R
E
G
1957IRQ1
C2IORD
C
2
D
4
C
2
D
6
C2WAIT
C
2
D
0
C
A
S
2
M
U
X
C1D2
C1IORD
C
2
C
E
C2REG
C
2
D
3
C
2
D
5
C1WAIT
CAS1RST
C2IOWR
CAS2PWR
C1D1
5
V
D
0
CAS1CD
C1D5
C2OE
C1D7
C
A
S
2
S
I
G
C2IRQ
C1D0
P
R
E
S
E
T
C
A
S
2
R
S
T
C1IRQ
MA15
C
A
S
1
M
U
X
C
2
D
2
C
2
D
7
C1D6
C1D4
C
1
C
E
CAS2CD
5
V
D
1
5
V
D
2
5
V
D
3
5
V
D
4
5
V
D
5
5
V
D
6
5
V
D
7
IRDETOCLK
CAS1PWR
DI11
VLDI1
DI15 D
I
1
4
D
I
1
1
S
T
R
I
1
IRDETOD0
C
A
S
1
S
I
G
DI13
DI10
IRDETOVLD
D
I
1
5
DI14
D
I
1
0
CAS1SIG
IRDETOD3
IRDETOD2
V
L
D
I
1
IRDETOCLK
C
L
K
I
1
DI17
IRDETOVLD
C
1
D
3
D
I
1
3
CAS1PWR
DI16
DI12
CLKI1
IRDETOSTR STRI1
IRDETOD0
IRDETOSTR
D
I
1
6
C1D3
IRDETOD1
D
I
1
2
D
I
1
7
C1CD2
C1CD1
C2CD2
C2CD1
CAS1CD
CAS2CD
C
1
A
0
7
C
1
A
0
6
C
1
A
0
5
C
1
A
0
4
C
1
A
0
3
C
1
A
0
2
C
1
A
0
0
C
1
A
0
1
M
A
2
C
1
A
0
1
C
1
A
0
2
C
1
A
0
3
C
1
A
0
4
C
1
A
0
5
C
1
A
0
6
C
1
A
0
7
C
1
A
0
0
M
A
2
C
1
C
S
C
1
A
0
8
C
1
A
1
0
C
1
A
0
9
C
1
A
0
9
C
1
A
0
8
C
1
A
1
0
C
1
A
1
1
C
1
A
1
1
CAS1_CS1
IRDETOD1
IRDETOD2
IRDETOD3
IRDETOD4
IRDETOD5
IRDETOD6
IRDETOD7
IRDETOD4
IRDETOD5
IRDETOD6
IRDETOD7
C1A13
C
1
A
1
2
C
1
A
1
3
C
1
A
1
4
C1A14
C1A12
M
A
3
M
A
4
M
A
5
M
A
6
M
A
7
M
A
8
M
A
9
M
A
1
0
M
A
1
1
M
A
1
2
M
A
1
3
M
A
3
M
A
4
C
L
K
2
7
M
+8V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
Q100
KST4401
2
1
3
R103 472
C102
104p
C101
104p
R104
121/3216
C100
682p
R102
472
R109
103
C103
105p/2012
PR104
103-4
1 8
2 7
3 6
4 5
R106
103
PR103
103-4
1 8
2 7
3 6
4 5
R111 103
R113 103
R110 103
R112 103
R114 103
R115 103
R116 103
R117 103
R118 103
R119 103
R120 472
C106
104p
R107
102
L101 BEAD-601
R108
103
U102A
IRF7303
8
7
1
2
D1
D1
S1
G1
R101
472
PR100
470-4
1 8
2 7
3 6
4 5
PR101
470-4
1 8
2 7
3 6
4 5
R105
103
L100
BEAD-601
U100 74HC244D
2 18
4 16
6 14
8 12
11 9
13 7
15 5
17 3
1
19
1A1 1Y1
1A2 1Y2
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4
1G
2G
PR102
470-4
1 8
2 7
3 6
4 5
U106A
74HC02
2
3
5
6
1
4
14
7
A1
B1
A2
B2
Y1
Y2
VCC
GND
U106B
74HC02
8
9
11
12
10
13
A1
B1
A2
B2
Y1
Y2
U101A
74HCT244
2
4
6
8
1
18
16
14
12
A1
A2
A3
A4
G
Y1
Y2
Y3
Y4
U104
74HC244D
2
1
8
4
1
6
6
1
4
8
1
2
1
1
9
1
3
7
1
5
5
1
7
3
11
9
1
A
1
1
Y
1
1
A
2
1
Y
2
1
A
3
1
Y
3
1
A
4
1
Y
4
2
A
1
2
Y
1
2
A
2
2
Y
2
2
A
3
2
Y
3
2
A
4
2
Y
4
1
G
2
G
U105A
74HC244D
24681
1
8
1
6
1
4
1
2
A
1
A
2
A
3
A
4
G
Y
1
Y
2
Y
3
Y
4
U103
CXD1957AQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
SEL1
VSS
OE_B
IOWR_B
IORD_B
WE_B
REG_B
DOE_B
AOE_B
WAIT_B
ACK
VSS
IRQ
CS
SEL0
RW
SI0
SI1
SO0
SO1
S
O
2
C
K
V
S
S
A
O
E
_
A
D
0
_
B
D
1
_
B
D
2
_
B
D
3
_
B
D
4
_
B
D
5
_
B
D
6
_
B
V
S
S
V
D
D
D
7
_
B
C
E
1
_
B
S
O
6
S
O
7
S
O
5
D
O
E
_
A
R
E
G
_
A
WE_A
VSS
SO4
SO3
WAIT_A
SI3
SI2
D7_A
D6_A
D5_A
D4_A
VSS
D3_A
D2_A
D1_A
D0_A
MISTR
TSCK
TSSTR
IORD_A
I
O
W
R
_
A
O
E
_
A
V
S
S
C
E
1
_
A
C
P
U
M
O
D
E
T
E
S
T
H
D
7
H
D
6
H
D
5
H
D
4
V
S
S
V
D
D
H
D
3
H
D
2
H
D
1
H
D
0
H
A
0
H
A
1
H
A
2
C110
104p
C109
104p
C108
104p
C104
105p/2012
C107
104p
JP120
91931-31169
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
C105
102p
IRDETOD0
DO10
DO11
DO12
DO13
DO14
DO15
DO16
DO17
8043STR
8043VLD
8043CLK
STR01
VLD01
CLK01
IRDETOD1
IRDETOD2
IRDETOD3
IRDETOD4
IRDETOD5
IRDETOD6
IRDETOD7
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
# Pull-up of R151 is 472.
All locations are from 130 to 159 in this page
CI Address Buffer Enable
Irdeto I-Chip Selection with CS[4]
ECO A00103 : Prevent picture problem
when using Irdeto CAM
(U101 : 74HC244 => 74HCT244)
CI Slot 2 1.0
Common Interface
OAK (IRCI-5400, CRCI-5500, CI-5100C)
Custom
5 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
D
O
2
3
D
O
2
4
D
O
2
5
D
O
2
6
D
O
2
7
S
T
R
I
2
D
I
2
1
D
I
2
2
D
I
2
3
D
I
2
4
V
L
D
I
2
D
I
2
5
C
L
K
I
2
D
I
2
6
D
I
2
7
C
L
K
_
O
2
C
A
S
2
R
S
T
V
L
D
O
2
S
T
R
O
2
D
O
2
1
D
O
2
0
D
O
2
2
C
2
O
E
C
A
S
2
S
I
G
C
2
I
O
R
D
C
2
I
O
W
R
C
2
D
5
C
2
I
R
Q
C
2
D
4
C
2
D
3
CAS2PWR
C
2
W
E
C
2
D
2
C
2
W
A
I
T
C
2
D
7
C
2
C
E
C
2
D
6
C
2
D
1
C
2
R
E
G
C
2
C
D
2
C
2
A
0
0
C
2
C
D
1
C
2
D
0
C2CD1
C2CD2
C
2
A
0
1
C
2
A
0
2
C
2
A
0
3
C
2
A
0
4
C
2
A
0
5
C
2
A
0
6
C
2
A
0
7
C
2
A
0
8
C
2
A
0
9
C
2
A
1
0
C
2
A
1
1
C
2
A
1
2
C
2
A
1
3
C
2
A
1
4
D
I
2
0 CA1D4
CA1D5
CA1D6
CA1D7
CA1STR
CA1VLD
CA1CLK
CA1D1
CA1D3
CA1D0
CA1D2
DI20
DI21
DI22
DI23
DI24
DI25
DI26
DI27
STRI2
VLDI2
CLKI2
DO20
DO21
DO22
DO23
CA1D4
CA1D5
CA1D6
CA1D7
DO24
DO25
DO26
DO27
CA1STR
CA1VLD
CA1CLK
STRO2
VLDO2
CA1D2
CA1D0
CA1D1
CA1D3
CLKO2
DO24
DO25
DO26
DO27
DO20
DO22
DO21
DO23
C2REG
C2WAIT
C2CE
STRO2
VLDO2
CLK_O2
C2IRQ
C2OE
C2WE
C2IORD
C2IOWR
CLK_O2
CAS1_CS1
MA15
MA16 C1CS
C2CS M
A
2
C
2
A
0
5
C
2
A
0
1
C
2
A
0
7
C
2
A
0
4
C
2
A
0
3
C
2
A
0
0
C
2
A
0
6
C
2
A
0
2
C2A12
C
2
A
0
8
C
2
A
0
9
C
2
A
1
0
C
2
A
1
1
C2A13
C2A14
C
2
C
S
MA15
MA16
CAS2_CS
ICHIPCS
M
A
3
M
A
4
M
A
5
M
A
6
M
A
7
M
A
8
M
A
9
M
A
1
0
M
A
1
1
M
A
1
2
M
A
1
3
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+8V
Q130
KST4401
2
1
3
C132
104p
C131
104p
R134
121/3216
C130
682p
PR130
470-4
1 8
2 7
3 6
4 5
PR131
470-4
1 8
2 7
3 6
4 5
R132
472
PR132
470-4
1 8
2 7
3 6
4 5
L130
BEAD-601
R135
103
C138
104p
U130 74HC244D
2 18
4 16
6 14
8 12
11 9
13 7
15 5
17 3
1
19
1A1 1Y1
1A2 1Y2
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4
1G
2G
R131
472
R136
103
U102B
IRF7303
6
5
3
4
D1
D1
S1
G1
C139
104p
JP130
91931-31169
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
C137
104p
R139
103
R138
103
C135
105p/2012
C134
105p/2012
R140
102
C136
102p
L131 BEAD-601
PR134
103-4
1 8
2 7
3 6
4 5
PR133
103-4
1 8
2 7
3 6
4 5
R144 103
R142 103
R141 103
R143 103
R145 103
R146 103
R147 103
R148 103
R149 103
R150 103
R151 472
R133 472
U132A
74HC139
2
3
1
4
5
6
7
A
B
G
Y0
Y1
Y2
Y3
U132B
74HC139
14
13
15
12
11
10
9
A
B
G
Y0
Y1
Y2
Y3
C140
104p
U105B
74HC244D
1
1
1
3
1
5
1
7
1
9
9753
A
1
A
2
A
3
A
4
G
Y
1
Y
2
Y
3
Y
4
U131
74HC244D
2
1
8
4
1
6
6
1
4
8
1
2
1
1
9
1
3
7
1
5
5
1
7
3
11
9
1
A
1
1
Y
1
1
A
2
1
Y
2
1
A
3
1
Y
3
1
A
4
1
Y
4
2
A
1
2
Y
1
2
A
2
2
Y
2
2
A
3
2
Y
3
2
A
4
2
Y
4
1
G
2
G
U101B
74HC244D
11
13
15
17
19
9
7
5
3
A1
A2
A3
A4
G
Y1
Y2
Y3
Y4
C141
104p
CA1D0
CA1D1
CA1D2
CA1D3
DO20
DO21
DO22
DO23
CA1D4
CA1D5
CA1D6
CA1D7
DO24
DO25
DO26
DO27
CA1STR
CA1VLD
CA1CLK
STRO2
VLDO2
CLKO2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
CI 2 output Interface
To SAA7219 From CI 2 Interface
CI 1 output Interface
To CI SLOT2, PAGE4 From CI 1 Interface
All locations are from 160 to 169 in this page.
For TS
By-pass
For TS
By-pass
TIis ccn;c TIis ccn;c TIis ccn;c TIis ccn;crerI(F16D) is a;;icaLe Ic rerI(F16D) is a;;icaLe Ic rerI(F16D) is a;;icaLe Ic rerI(F16D) is a;;icaLe Ic
CF=5 CF=5 CF=5 CF=551D. V/=52DDC lcce. 51D. V/=52DDC lcce. 51D. V/=52DDC lcce. 51D. V/=52DDC lcce. TIis ccn;c TIis ccn;c TIis ccn;c TIis ccn;crerI(F161) is a;;icaLe Ic rerI(F161) is a;;icaLe Ic rerI(F161) is a;;icaLe Ic rerI(F161) is a;;icaLe Ic
CF=5 CF=5 CF=5 CF=551D. V/=52DDC lcce. 51D. V/=52DDC lcce. 51D. V/=52DDC lcce. 51D. V/=52DDC lcce.
TIis area ccn;crerIs is a;;icaLe Ic TIis area ccn;crerIs is a;;icaLe Ic TIis area ccn;crerIs is a;;icaLe Ic TIis area ccn;crerIs is a;;icaLe Ic a a a a
ncces exce;I ncces exce;I ncces exce;I ncces exce;I lFCl=5^DD lcce. lFCl=5^DD lcce. lFCl=5^DD lcce. lFCl=5^DD lcce.
de} de} de}
CI Out 1.0
Common Interface
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C, VA-5200C)
Custom
6 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
DO20
CAS2MUX
STRO2
CA1STR
CAD2
CAD4
VLDO2
CA1CLK
CAD3
CAD1
DO24
CA1D3
CA1D1
CAD5
CA1VLD
CA1D7
DO22
CA1D0
CACLK
CLKO2
CAD7
DO27
CAVLD
DO26
DO25
CA1D6
CA1D4
DO21
CAD0
CA1D5
CA1D2
CAD6
DO23
DO10
CAS1MUX
STRO1
IRDETOSTR
VLDO1
IRDETOCLK
IRDETOVLD
IRDETOD0
CA1CLK
CLKO1
CA1VLD
CA1D0
DO11
DO12
DO13
DO14
DO15
DO16
DO17
CA1D1
CA1D2
CA1D3
CA1D4
CA1D5
CA1D6
CA1D7
CA1STR
CASTR
IRDETOD1
IRDETOD2
IRDETOD3
IRDETOD4
IRDETOD5
IRDETOD6
IRDETOD7
8043CLK
IRDETOD5
8043D3
IRDETOD6
8043D7
IRDETOD3
IRDETOD1
IRDETOD7
8043D4
IRDETOCLK
8043D2 IRDETOD2
8043STR
IRDETOD4
IRDETOVLD 8043VLD
8043D6
8043D5
8043D1
IRDETOD0 8043D0
IRDETOSTR
+5V
+5V
U165 74HC257
2
7
1
5
11
14
3
6
10
13
4
9
12
15
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
PR163
470-4
1 8
2 7
3 6
4 5
U163 74HC257
2
7
1
5
11
14
3
6
10
13
4
9
12
15
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
PR164
470-4
1 8
2 7
3 6
4 5
PR165
470-4
1 8
2 7
3 6
4 5
U164 74HC257
2
7
1
5
11
14
3
6
10
13
4
9
12
15
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
R160
000-Option
R161
000-Option
U162 74HC257
2
7
1
5
11
14
3
6
10
13
4
9
12
15
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
PR160
470-4
1 8
2 7
3 6
4 5
U160 74HC257
2
7
1
5
11
14
3
6
10
13
4
9
12
15
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
PR161
470-4
1 8
2 7
3 6
4 5
PR162
470-4
1 8
2 7
3 6
4 5
U161 74HC257
2
7
1
5
11
14
3
6
10
13
4
9
12
15
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
C162
104p
C161
104p
C160
104p C165
104p
C164
104p
C163
104p
PR171
000-4
1 8
2 7
3 6
4 5
PR172
000-4
1 8
2 7
3 6
4 5
PR173
000-4
1 8
2 7
3 6
4 5
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
1. +30V/2A
2. +24V
3. +17V
4. GND
5. +8V/2A
6. GND
7. +5V/1.5A
8. GND
9. +3.3V/2A
10. GND
11.+15V/0.3A
12. GND
TO POWER
SUPPLY
All locations are from 190 to 209 in this page.
Front
Power
From u-Com
# Range = 16 - 17V
# Range = 14.5 - 15.5V
Power Control 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
7 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
+24V
+30V
+15V
+8V
POW_CTRL
+5VF
+5V
+3.3V
+17V
+30V
+24V
+15V
+8V
+5VF
+5V
+3.3V
+17V
C200
473p-OPEN
R200
472-OPEN
R201
472
Q200
KST4401 2
1
3
JP200
5267-12A
1
2
3
4
5
6
7
8
9
10
11
12
R202
472
U200
IRF7303
8
7
6
5
1
2
3
4
D1
D1
D2
D2
S1
G1
S2
G2
R203 0-OPEN 3216 CHIP
R204 0-OPEN 3216 CHIP
POW_CTRL
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
Location Number of 'L' is from 330 to 367.
And others are from 330 to 339.
TO FRONT
7219
7219
Power CTL
+5V Buffer
7219
# L363 of uCOM_CS is located near
7219 uCOM_CS OUT as L221
# Bead-601 is replaced by BLM21B222SB for EMI
FROM CHANNEL BOARD
TO CI PART
SH 3
1. +3.3V
2. +5V
3. GND
4. DETECT
5. IO
6. RESET
7. VCC_EN
8. CLOCK
9. GND
1. +3.3V
2. +5V
3. GND
4. DETECT
5. IO
6. RESET
7. VCC_EN
8. CLOCK
9. GND
TO Irdeto SC SLOT1
( Upper Slot )
TO 7816 SC SLOT2
( Lower Slot ) From/To
7219
From/To
7219
TIis area ccn;crerIs is a;;ic TIis area ccn;crerIs is a;;ic TIis area ccn;crerIs is a;;ic TIis area ccn;crerIs is a;;icaLe Ic aLe Ic aLe Ic aLe Ic
lFCl=5^D lFCl=5^D lFCl=5^D lFCl=5^DD. V/=52DDC lcce. D. V/=52DDC lcce. D. V/=52DDC lcce. D. V/=52DDC lcce.
TIis a TIis a TIis a TIis area ccn;creIrs is a;;icaLe Ic CFCl=55DD. rea ccn;creIrs is a;;icaLe Ic CFCl=55DD. rea ccn;creIrs is a;;icaLe Ic CFCl=55DD. rea ccn;creIrs is a;;icaLe Ic CFCl=55DD.
CF=5 CF=5 CF=5 CF=551D. V/=52DDC lcce. 51D. V/=52DDC lcce. 51D. V/=52DDC lcce. 51D. V/=52DDC lcce.
Main Connector 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
8 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
5VD1
5VD2
5VD3
5VD4
5VD5
uCom_CS
5VD7
LA1
LA2
uComIRQ
POW_CTRL
LA0
5VD6
LA3
5VD0
WEN
OEN
+8V
+3.3V
+3.3V
8043STR
8043CLK
8043VLD
8043D0
8043D2
8043D1
8043D3
8043D4
8043D6
8043D5
8043D7
8043RST
SDA0
SCL0
8043IRQ
+17V
+30V
+24V
SC_VCCN0
SC_DET0
SC_CLK1
SC_CLK0
SC_RST0
ISC_IO
SC_IO1
SC_RST1
SC_DET1
SC_VCCN1
+5VF
+5V
+3.3V
+5V
+3.3V
C331
104p
L352 000
L353 000
L364 BLM21A601SPTM00-03
L365 BLM21A601SPTM00-03
JP335
53014-1110
1
2
3
4
5
6
7
8
9
10
11
JP332
53014-1110
1
2
3
4
5
6
7
8
9
10
11
L346 BLM21A601SPTM00-03
L347 BLM21A601SPTM00-03
L348 BLM21A601SPTM00-03
L349 BLM21A601SPTM00-03
L355 121
L356 121
L357 121
L358 121
L359 121
L360 121
L361 121
L362 121
L350 121
L351 121
JP333
52045-2445
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C333
104p-Option
JP330
53014-0910-Option
1
2
3
4
5
6
7
8
9
C334
104p-Option
JP331
53014-0910-Option
1
2
3
4
5
6
7
8
9
C332
104p-Option
C335
104p-Option
L330
BLM21A601SPTM00-03-Optipn
L331 BLM21A601SPTM00-03-Ootion
L333 BLM21A601SPTM00-03-Option
L334 BLM21A601SPTM00-03-Option
L335 BLM21A601SPTM00-03-Option
L336 BLM21A601SPTM00-03-Option
L367
BLM21A601SPTM00-03-Option
L339 BLM21A601SPTM00-03-Option
L340 BLM21A601SPTM00-03-Option
L341 BLM21A601SPTM00-03-Option
L342 000-Option
L343 BLM21A601SPTM00-03-Option
L330
BLM21A601SPTM00-03-Option
C333
104p-Option
C332
104p-Option
C335
104p-Option
L367
BLM21A601SPTM00-03-Option
C334
104p-Option
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 210 to 219
SMALL TYPE DC JACK
From
7219
DC 12VE is used to
external modem
only.
To RF Modulator
Ths area ccnpcnenls s applcable lc all ncoels e Ths area ccnpcnenls s applcable lc all ncoels e Ths area ccnpcnenls s applcable lc all ncoels e Ths area ccnpcnenls s applcable lc all ncoels excepl Cl5100C. VA5200C Mcoel. xcepl Cl5100C. VA5200C Mcoel. xcepl Cl5100C. VA5200C Mcoel. xcepl Cl5100C. VA5200C Mcoel.
DC 12V 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
9 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
1
DC12V
+12V
+12VE
+5VRF RFCH
+15V
+5V
+12VE
+12V
C210
47u/50V
C211
104p
C212
104p
C213
10u/16V
U210
LM78L12
1
2
3
VI
G
N
D
VO
R211
102
R212
472
R210
472
R213
472
Q211
KST4401
2
1
3
Q210
KST4403
2
1 3 JP210
DDAE-9637
C214
104p
C215
104p
U211
LM78L12
1
2
3
VI
G
N
D
VO
R214
102
Q213
KST4401
2
1
3
R216
472
Q212
KST4403
2
1 3
R215
472
R217 102-OPEN R218 000-OPEN
DC12V
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 220 to 249 in this page.
From CI OUT
/ IChip
Irdeto SC
7816 SC
MPEG(7215)
I/F
Modem
I/F
Irdeto
I/F
232
I/F
Irdeto IO
# F210 is replaced by 50M
Filter(NFM51R00P506)
TIis area ccn;crerIs is a;;ica TIis area ccn;crerIs is a;;ica TIis area ccn;crerIs is a;;ica TIis area ccn;crerIs is a;;icaLe Ic Le Ic Le Ic Le Ic
lFCl=5^DD lcc lFCl=5^DD lcc lFCl=5^DD lcc lFCl=5^DD lcce. e. e. e.
F2S6 is cry F2S6 is cry F2S6 is cry F2S6 is cry !cr lFCl=5^DD lcce !cr lFCl=5^DD lcce !cr lFCl=5^DD lcce !cr lFCl=5^DD lcce
F2S2 is c F2S2 is c F2S2 is c F2S2 is cry !cr V/=52DDC lcce. ry !cr V/=52DDC lcce. ry !cr V/=52DDC lcce. ry !cr V/=52DDC lcce.
F2S1 is a;;icaLe Ic a ncces exce;I V/=5 F2S1 is a;;icaLe Ic a ncces exce;I V/=5 F2S1 is a;;icaLe Ic a ncces exce;I V/=5 F2S1 is a;;icaLe Ic a ncces exce;I V/=52DDC lcce. 2DDC lcce. 2DDC lcce. 2DDC lcce.
Ncle Ncle Ncle Ncle
# L224 is to
connector
TIis area ccn;crerIs is a;;ic TIis area ccn;crerIs is a;;ic TIis area ccn;crerIs is a;;ic TIis area ccn;crerIs is a;;icaLe Ic aLe Ic aLe Ic aLe Ic
lFCl=5^DD lc lFCl=5^DD lc lFCl=5^DD lc lFCl=5^DD lcce. ce. ce. ce.
Demux - CPU 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
10 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
CASTR
M
A
5
AVD0
AVD3
E
C
M
_
I
N
T
L
A
0
M
A
8
M
A
7
M
A
6
SCLK
CAVLD
SCL0
M
D
1
L
C
A
S
R
S
2
3
2
R
X
D
D
S
R
R
I
CACLK
M
A
1
8
0
4
3
I
R
Q
R
X
D
1
L
A
1
CAD4
M
A
1
2
M
D
9
I
M
_
R
S
T
L
A
3
M
D
8
ROM_CS
C
T
S
1
D
T
R
L
A
2
SDA1
M
D
6
M
A
4
M
D
1
5
AVD4
A_STROBE
CS_RGN
R
S
2
3
2
C
T
S
D
C
1
2
V
CAD2
CAD7
M
A
1
9
M
A
1
5
M
A
2
D
C
D
CAD5
M
D
4
M
D
5
M
D
7
AVD5
AV_ERR
V_STROBE
M
D
3
M
A
1
4
M
A
1
0
M
D
1
2
D
A
C
_
D
A
T
A
AVD7
D
T
A
C
K
7
2
1
5
I
R
Q
1
CAS1_CS
CAD0
M
A
1
7
M
D
1
3
O
E
N
R
S
2
3
2
R
T
S
CAD1
CAD6
M
A
1
8
M
A
1
6
AVD2
M
L
C
A
S
R
S
2
3
2
T
X
D
T
X
D
1
M
A
2
0
M
A
1
3
M
D
1
1
u
C
o
m
I
R
Q
R
A
S
0
CAS2_CS
D
A
C
_
C
L
K
M
A
9
M
D
1
4
M
A
0
1
9
5
7
I
R
Q
1
7
2
1
5
I
R
Q
0
SCL1
M
A
1
1
M
D
1
0
M
A
3
CS_SDN
D
A
C
_
E
N
B
1
CAD3
SDA0
M
D
0
M
D
2
AVD1
AVD6
FLASH1_CS
FLASH2_CS
R
T
S
1
SC_CLK0
SC_VCCN0
SC_RST0
SC_DET0
ISC_IO
SC_CLK1
SC_VCCN1
SC_RST1
SC_DET1
SC_IO1
PRESET
D
C
S
0
W
E
N
CLK405
SCLK
TxD2
ISC_IO
T
X
D
2
I
S
C
_
I
O
I
C
H
I
P
R
S
T
E
M
M
_
I
N
T
7
2
1
5
R
S
T
uCom_CS
8043RST
ISC_CLK0
+3.3V
+3.3V
+3.3V
+5V
+3.3V
+3.3V
+5V
+3.3V
+5V
+3.3V
+5V
+3.3V
+3.3V
+5V
+5V
U221
KIA7027F
1 2 3
V
C
C
G
N
D
O
U
T
C234
104p
L220 BEAD-330
R228
101-OPEN
S221
KPT1105A-OPEN
C229
104p
C230
104p
C231
104p
C232
104p
C233
104p
JP221
53014-0410-OPEN
1
2
3
4
R230
102-OPEN
C225
104p
C222
104p
C226
104p
C227
104p
C228
104p
C223
104p
C220
104p
C221
104p
C224
104p
+ C235
2.2u/50V
PR220
472-4
1
8
2
7
3
6
4
5
PR222 472-4
1 8
2 7
3 6
4 5
PR221 472-4
1 8
2 7
3 6
4 5
R222 472
R232 0-Option
VDDP : 3, 17, 27, 31, 43, 66, 79, 80, 92, 115, 130, 145, 182, 187
VSSP : 10, 23, 26, 37, 57, 72, 78, 86, 104, 127, 131, 170, 183, 198
SQFP208

SAA7219HS/C1
178
1
3
9
179
1
4
3
180
1
4
0
181
60
184
1
4
1
1
4
4
4
2
1
4
6
61
50
4
6
51
4
4
1
0
5
4
5
52
4
9
53
4
8
208
4
7
54
5
8
55
6
2
1
0
6
5
9
56
9
1
197
1
0
7
207
1
0
8
93
1
0
9
206
1
1
0
196
1
1
1
205
1
1
2
151
204
195
203
94
202
194
201
200
193
199
95
192
152
191
96
190
97
153
98
185
99
165
100
101
102
6
3
103
186
2
1
188
6
4
189
2
2
6
5
128
6
7
2
4
6
8
2
5
6
9
129
7
0
2
8
7
1
2
9
7
3
132
7
4
3
0
7
5
3
2
7
6
133
7
7
3
3
8
1
3
4
8
2
134
8
3
3
5
8
4
3
6
8
5
122
8
7
3
8
8
8
3
9
8
9
123
9
0
4
0
4
1
124
125
126
147
148
149
150
154
155
156
157
158
159
160
161
162
163
164
166
167
168
169
171
172
173
174
175
176
177
1
24567891
1
1
2
1
3
1
4
1
5
1
6
1
8
1
9
2
0
113
114
1
1
6
1
1
7
1
1
8
1
1
9
1
2
0
1
2
1
1
3
5
1
3
6
1
3
7
1
3
8
1
4
2
TDO
R
T
S
1
TDI
R
T
S
0
TMS
C
T
S
1
TRST
CS_SDN
TCK
R
X
D
0
C
T
S
0
U
C
A
S
M
C
L
K
CS_RGN
CS6
L
C
A
S
CS5
M
U
C
A
S
P
I
O
0
M
L
C
A
S
CS4
R
A
S
0
CS3
R
A
S
1
/
D
C
S
1
DIR1284
D
C
S
0
CS2
O
E
N
CS1
W
E
N
P
I
O
1
D
T
A
C
K
CS0
C
L
K
_
4
0
.
5
M
GPD7
P
I
O
2
NFAULT
P
I
O
3
V_STROBE
P
I
O
4
NAUTOF
P
I
O
5
GPD6
P
I
O
6
SELECT
P
I
O
7
VDD_PLL
PERR
GPD5
BUSY
A_STROBE
NACK
GPD4
NSTRB
NINIT
GPD3
NSELIN
AV_ERR
GPD2
XTAL2
GPD1
AV_DATA7
GPD0
AV_DATA6
XTAL1
AV_DATA5
DS_CLK
AV_DATA4
PWM0
AV_DATA3
AV_DATA2
AV_DATA1
A
0
AV_DATA0
PCST0
D
1
5
PCST1
A
1
PCST2
D
1
4
A
2
SC_CLK_0
A
3
D
1
3
A
4
D
1
2
A
5
SC_VCCN_0
A
6
D
1
1
A
7
D
1
0
A
8
SC_RST_0
A
9
D
9
A
1
0
D
8
A
1
1
SC_DET_0
A
1
2
D
7
A
1
3
D
6
A
1
4
SC_IO_0
A
1
5
D
5
A
1
6
D
4
A
1
7
SC_CLK_1
A
1
8
D
3
A
1
9
D
2
A
2
0
SC_VCCN_1
A
2
1
D
1
D
0
SC_RST_1
SC_DET_1
SC_IO_1
SCL1
SDA1
SCL0
SDA0
PKT_STRB
PKT_SYNC
PKT_VLD
PKT_DATA7
PKT_DATA6
PKT_DATA5
PKT_DATA4
PKT_DATA3
PKT_DATA2
PKT_DATA1
PKT_DATA0
GP_DATA7
GP_DATA6
GP_DATA5
GP_DATA4
GP_DATA3
GP_DATA2
GP_DATA1
GP_DATA0
GP_VLD
GP_SYNC
GP_STRB
RESET_IN
P
I
O
3
1
_
D
3
1
P
I
O
3
0
_
D
3
0
P
I
O
2
9
_
D
2
9
P
I
O
2
8
_
D
2
8
P
I
O
2
7
_
D
2
7
P
I
O
2
6
_
D
2
6
P
I
O
2
5
_
D
2
5
P
I
O
2
4
_
D
2
4
P
I
O
2
3
_
D
2
3
P
I
O
2
2
_
D
2
2
P
I
O
2
1
_
D
2
1
P
I
O
2
0
_
D
2
0
P
I
O
1
9
_
D
1
9
P
I
O
1
8
_
D
1
8
P
I
O
1
7
_
D
1
7
P
I
O
1
6
_
D
1
6
PIO8_BOOT32
PIO9_BOOT16
P
I
O
1
0
P
I
O
1
1
P
I
O
1
2
P
I
O
1
3
P
I
O
1
4
P
I
O
1
5
R
X
D
2
T
X
D
2
R
X
D
1
T
X
D
1
T
X
D
0
R225
470
C239
100p
NFM51R00P506
F210
1 3
2
S S
C
R226
472
C240
104p
R227
751
U223
74HC05-Option
1
2
4
5
6
14
7
3
8
9
11
10
13
12
A1
Y1
Y2
A3
Y3
VCC
GND
A2
Y4
A4
A5
Y5
A6
Y6
C237
104p
+ C238
1000u/6.3V
U222 13.5M
1
3 4
2
VI
CLK VCC
GND
R229
103
C236
104p
R233
272
R235
472-Option
R234
472-Option
L221 BLM21A601SPTM00-03
C241
104p-Option
L222
BLM21A601SPTM00-03
R231 472-Option
R
2
3
6
0
0
0
-
O
p
t
io
n
U224
74HC04-Option
1
2
3
4
6
5
8
9
10
11
14
7
13
12
A1
Y1
A2
Y2
Y3
A3
V4
A4
Y5
A5
+5V
DGND
A6
Y6
C249
390p/2012-Option
Y220
12MHz-Option
R237 105-Option
C248
390p/2012-Option
C247
104p-Option
L224 BEAD-601-Option L223 000-Option
PRESET
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 250 to 254 in this page.
To CXD1957,
FRONT &
IChip
From SAA7219
From 7219
# 5V Data IC = CXD1957, u-COM, I-Chip
Ths area ccn Ths area ccn Ths area ccn Ths area ccnpcnenls s applcable lc CRCl5500. pcnenls s applcable lc CRCl5500. pcnenls s applcable lc CRCl5500. pcnenls s applcable lc CRCl5500.
Cl5100C Cl5100C Cl5100C Cl5100C.lRCl5400 Mcoel .lRCl5400 Mcoel .lRCl5400 Mcoel .lRCl5400 Mcoel
+5V Buffer 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
11 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
OEN
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
5VD0
5VD1
5VD2
5VD3
5VD4
5VD5
5VD6
5VD7
CAS1_CS
1957DTACK
DTACK
7215DTACK
CAS2_CS
uCom_CS
CAS1_CS1
ICHIPCS1
ICHIPCS
CAS1_CS
CLK27M
+3.3V
+5V
+3.3V
+5V
+3.3V
U250
74LVT245
10
20 1
19
11
12
13
14
15
16
17
18 2
3
4
5
6
7
8
9
GND
VCC T/R
/OE
B7
B6
B5
B4
B3
B2
B1
B0 A0
A1
A2
A3
A4
A5
A6
A7
C250
104p
C251
104p
R250
472
R251
472-OPEN
U251
74LVC08D
8
9
10
11
12
13
14 1
2
3
4
5
6
7
U252
74HC32
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A1
B1
Y1
A2
B2
Y2
G
VCC
B4
A4
Y4
B3
A3
Y3
U253
74HC174
1
2
3
4
5
6
7
16
15
14
13
12
11
9 8
10
CLR
1Q
1D
2D
2Q
3D
3Q
VCC
6Q
6D
5D
5Q
4D
CLK G
4Q
C252
104p
C253
104p
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 255 to 259 in this page.
Flash nencry sze labl Flash nencry sze labl Flash nencry sze labl Flash nencry sze lable ee e
lCLEL lCLEL lCLEL lCLEL Lsec Fa Lsec Fa Lsec Fa Lsec FasI nencry sI nencry sI nencry sI nencry
Cl=51DD Cl=51DD Cl=51DD Cl=51DDC CC C DT28F800F3E95
CF=551 CF=551 CF=551 CF=551D DD D
CFC CFC CFC CFCl=55DD l=55DD l=55DD l=55DD LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5
LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5
LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5 V/= V/= V/= V/=52DDC 52DDC 52DDC 52DDC
LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5 LT28F16DFSE=D5 lFCl=5 lFCl=5 lFCl=5 lFCl=5^DD ^DD ^DD ^DD
Flash 1 (8M) 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
12 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
M
A
1
9
M
A
1
8
M
A
1
7
M
A
1
6
M
A
1
5
M
A
1
4
M
A
1
3
M
A
1
2
M
A
1
1
M
A
1
0
M
A
9
M
A
8
M
A
7
M
A
6
M
A
5
M
A
4
M
A
3
M
A
1
M
A
2
M
D
0
M
D
1
M
D
2
M
D
3
M
D
4
M
D
5
M
D
6
M
D
7
M
D
8
M
D
9
M
D
1
0
M
D
1
1
M
D
1
2
M
D
1
3
M
D
1
4
M
D
1
5
OEN
WEN
CLK405
M
A
1
M
A
2
M
A
3
M
A
4
M
A
5
M
A
6
M
A
7
M
A
8
M
A
9
M
A
1
0
M
A
1
1
M
A
1
2
M
A
1
3
M
A
1
4
M
A
1
5
M
A
1
6
M
A
1
7
M
A
1
8
M
A
1
9
M
A
2
0
M
D
0
M
D
1
M
D
2
M
D
3
M
D
4
M
D
5
M
D
6
M
D
7
M
D
8
M
D
9
M
D
1
0
M
D
1
1
M
D
1
2
M
D
1
3
M
D
1
4
M
D
1
5
ROM_CS
FLASH1_CS
M
A
2
0
P
R
E
S
E
T
+3.3V
+5V
+3.3V
+3.3V
DT28F800F3B-95 or DT28F160F3B-95
U255
5
5
3
6
5
3
3
9
2
3
3
8
3
5
5
6
4
1
3 5
1
2
3
2
5
0
3
0
4
9
2
7
4
8
2
5
4
7
1
6
4
6
1
8
4
5
4
0
1
3
4
2
1
2
3
1
1
1
2
9
1
0
2
6
9
2
4
8
1
7
7
1
9
62
2
4
4
4
3
5
2
51
4
3
4
1
28
21
33
54
4
15
20
37
R
S
T
#
C
E
#
W
P
#
D
Q
0
W
A
I
T
#
O
E
#
A
0
W
E
#
D
Q
1
A
D
V
#
A
1
C
L
K
D
Q
2
A
2
D
Q
3
A
3
D
Q
4
A
4
D
Q
5
A
5
D
Q
6
A
6
D
Q
7
A
7
D
Q
8
A
8
D
Q
9
A
9
D
Q
1
0
A
1
0
D
Q
1
1
A
1
1
D
Q
1
2
A
1
2
D
Q
1
3
A
1
3
D
Q
1
4
A
1
4
D
Q
1
5
A
1
5
A
1
6
A
1
7
A
1
8
A
1
9
N
C
N
C
N
C
VCC
VCC
VCCQ
VCCQ
VPP
GND
GND
GND
GND
C255
104p
C256
104p
C257
104p
JP255
52368-0401
12345678
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
91
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
C258
104p
R256
472
U256
74HC257
16
8
2
7
1
5
11
14
3
6
10
13
4
9
12
15
VCC
GND
1A
2Y
A/B
2A
3A
4A
1B
2B
3B
4B
1Y
3Y
4Y
G
C259
104p
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 260 to 269 in this page.
( 28F160B3B-90 )
Flash nencry sze lable Flash nencry sze lable Flash nencry sze lable Flash nencry sze lable
lCLEL lCLEL lCLEL lCLEL Lsec Fa Lsec Fa Lsec Fa Lsec FasI nencry sI nencry sI nencry sI nencry
28F800E3E90
28F800E3E90 Cl=51DD Cl=51DD Cl=51DD Cl=51DDC CC C
28F800E3E90
V/= V/= V/= V/=52DDC 52DDC 52DDC 52DDC
28F16DESE=DD 28F16DESE=DD 28F16DESE=DD 28F16DESE=DD
CF CF CF CFCl=55DD Cl=55DD Cl=55DD Cl=55DD
28F800E3E90
CF=551 CF=551 CF=551 CF=551D DD D
lFCl=5 lFCl=5 lFCl=5 lFCl=5^DD ^DD ^DD ^DD
Flash 1 (8M) 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
13 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MA13
MA12
MA10
MA9
MA8
MA7
OEN
FLASH2_CS
MA15
MA14
MA18
MA16
MA6
MA5
MA4
WEN
MA19
MA17
MA3
MA2
MA20
MA11
MA1
PRESET
+3.3V
+3.3V
C261
104p
C262
104p
U260
28F800B3B-90
14
25
47
12
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
1
3
3
7
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
11
2
7
4
6
26
28
15
9
10
WP
A0
VCCQ
RP
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
V
P
P
V
C
C
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
WE
G
N
D
G
N
D
CE
OE
A19
N.C
A20
C260
104p
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 280 to 289 in this page.
# Option : U270 or 280
16M SDRAM 1.0
Main
OAK (ONLY IRCI-5400)
Custom
15 30 Wednesday, May 31, 2000
Title
Size Document Number Rev
Date: Sheet of
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MLCAS
LCAS
WEN
OEN
RAS0
DCS0
CLK405
+3.3VSD
+3.3V
U280
KM416S1020BT-G10-Option
36
21
14
22
15
23
16
24
17
27
18
28
35
29
30
31
32
20
19
2
3
5
6
8
9
11
12
39
40
42
43
45
46
48
49
34
1
25
26
50
4
10
41
47
7
13
38
44
33
37
UDQM
BA0
LDQM
BA1
/WE
BA2
/CAS
BA3
/RAS
BA4
/CS
BA5
CLK
BA6
BA7
BA8
BA9
BA10
BA11
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
CKE
VCC
VCC
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VCCQ
VCCQ
VCCQ
VCCQ
NC
NC
C270
104p-Option
C271
104p-Option
C272
104p-Option
C273
104p-Option
C275
104p-Option
L270
BEAD 601-Option
C274
104p-Option
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
E E
F F
All locations are from 290 to 309 in this page.
MPEG SDRAM
SDRAM CLOCK
GRAPHIC SDRAM
EBIU
7219
ANALOG VIDEO OUT
DIGITAL AUDIO OUT
SPDIF
To CXD1957 & ICHIP
# Patern ZZZ means that patern
length is to be longed
MPEG I/F
TIis area ccn;crerIs is TIis area ccn;crerIs is TIis area ccn;crerIs is TIis area ccn;crerIs is rcI Lsec rcI Lsec rcI Lsec rcI Lsec
TIis TIis TIis TIis area ccn;crerIs is a;;icaLe Ic lFCl=5^DD. area ccn;crerIs is a;;icaLe Ic lFCl=5^DD. area ccn;crerIs is a;;icaLe Ic lFCl=5^DD. area ccn;crerIs is a;;icaLe Ic lFCl=5^DD.
CFCl CFCl CFCl CFCl=55DD. Cl=51DDC lcce. =55DD. Cl=51DDC lcce. =55DD. Cl=51DDC lcce. =55DD. Cl=51DDC lcce.
MPEG Decoder 1.0
Main
OAK (IRCI-5400, CR-5510, CRCI-5500, CI-5100C,VA-5200C)
Custom
16 30 Thursday, June 08, 2000
Title
Size Document Number Rev
Date: Sheet of
M
A
2
M
A
3
M
A
4
M
A
5
M
A
6
M
A
7
M
A
8
M
A
9
M
A
1
0
M
A
1
1
M
A
1
2
M
A
1
3
M
A
1
4
M
A
1
5
MA16
MA17
MA18
MA19
MA20
M
D
0
M
D
1
M
D
2
M
D
3
M
D
4
M
D
5
M
D
6
M
D
7
M
D
8
M
D
9
M
D
1
0
M
D
1
1
M
D
1
2
M
D
1
3
M
D
1
4
M
D
1
5
O
E
N
7
2
1
5
D
T
A
C
K
C
S
_
R
G
N
7
2
1
5
I
R
Q
0
7
2
1
5
I
R
Q
1
L
C
A
S
M
L
C
A
S
S
D
G
_
D
0
S
D
G
_
D
1
S
D
G
_
D
2
S
D
G
_
D
3
S
D
G
_
D
4
S
D
G
_
D
5
S
D
G
_
D
6
S
D
G
_
D
7
S
D
G
_
D
8
S
D
G
_
D
9
S
D
G
_
D
1
0
S
D
G
_
D
1
1
S
D
G
_
D
1
2
S
D
G
_
D
1
3
S
D
G
_
D
1
4
S
D
G
_
D
1
5
S
D
G
_
A
0
S
D
G
_
A
1
S
D
G
_
A
2
S
D
G
_
A
3
S
D
G
_
A
4
S
D
G
_
A
5
S
D
G
_
A
6
S
D
G
_
A
7
S
D
G
_
A
8
S
D
G
_
A
9
S
D
G
_
A
1
0
S
D
G
_
A
1
1
S
D
G
_
C
A
S
S
D
G
_
W
E
S
D
G
_
U
D
Q
1
S
D
G
_
U
D
Q
0
SBLUE
SGREEN
SRED
SY/CVBS
SC/CVBS
DA_WS
DA_DATA
DA_CLK
DA_FSCLK
SPDIF
M
A
1
S
D
G
_
R
A
S
W
E
N
C
S
_
S
D
N
SDM_A4
SDM_A11
SDM_A0
SDM_D4
SDM_D14
AVD7
SDM_A10
SDM_D2
SDM_D5
SDM_D15
SDM_A1
SDM_D6
SDM_A8
SDM_D7
SDM_D9
SDM_A5
SDM_D10
AVD1
SDM_D8
AVD6
AVD5
AVD4
SDM_D0
SDM_D11
SDM_A2
AVD3
SDM_A9
SDM_D12
V_STROBE
SDM_A3
AVD2
SDM_D1
SDM_D13
CLK405
SDM_A6
SDM_A7
AV_ERR
PRESET
7215RST
CP81M
SDM_UDQ
SDM_WE
SDM_CAS
SDM_RAS
CP81MEXT
SDM_D3
A_STROBE
AVD0
CLK27M
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+5V
+3.3V
R292 750
C307
100p
R293 202
R294 120
R295 180
L290
BEAD-330
L291 BEAD-330
C308
104p
C292
104p
C293
104p
C294
104p
C295
104p
C296
104p
C302
104p
C303
104p
C304
104p
C305
104p
C306
104p
C297
104p
C298
104p
C299
104p
C300
104p
C301
104p
R296
103
PR290
103-4
1 8
2 7
3 6
4 5
VDD : 8, 22, 27, 36, 50, 60, 74, 79, 89, 103, 127, 130, 148,
183, 184 (15Pin)
VSS : 1, 15, 26, 31, 43, 57, 67, 78, 83, 96, 122, 129, 138,
166, 169, 182 (15Pin)
TOTAL : 208Pin