1.1) Design all basic gates and simulate them. ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.

ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity all_gates is Port ( pand : out STD_LOGIC; por : out STD_LOGIC; pnor : out STD_LOGIC; pnand : out STD_LOGIC; pxor : out STD_LOGIC; pxnor : out STD_LOGIC; pnot : out STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC); end all_gates; architecture Behavioral of all_gates is begin pand <= a and b; por <= a or b; pnot <= (not a); pxor <= a xor b; pnand <= a nand b; pnor <= a nor b; pxnor <= a xnor b; end Behavioral;

RTL Schematic

Technology Schematic:

Output:

Conclusion: Hence, we have implemented all basic gates. Also, from the RTL Schematic & Technology schematic we can say that if we are combining all basic gates in one VHDL code, VHDL itself tries to minimize the no. of gates and gives optimum hardware layout. Maximum combinational path delay is 6.497ns.

1.2) Design one bit full adder using all the modelling styles and compare them. 1.2.1) Behavioural Modelling ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fa_behavioral is Port ( a : in STD_LOGIC; b : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end fa_behavioral; architecture Behavioral of fa_behavioral is begin process(a,b,Cin) begin if(a='0' and b='0' and cin='0')then Sum <= '0'; Cout <= '0'; elsif(a='0' and b='0' and cin='1')then Sum <= '1'; Cout <= '0'; elsif(a='0' and b='1' and cin='0')then Sum <= '1'; Cout <= '0'; elsif(a='0' and b='1' and cin='1')then Sum <= '0'; Cout <= '1'; elsif(a='1' and b='0' and cin='0')then Sum <= '1'; Cout <= '0'; elsif(a='1' and b='0' and cin='1')then Sum <= '0';

Cout <= '1'; elsif(a='1' and b='1' and cin='0')then Sum <= '0'; Cout <= '1'; else Sum <= '1'; Cout <= '1'; end if; end process; end Behavioral; RTL Schematic:

Technology Schematic:

Output:

1.2.2) Dataflow Modelling ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fa_data is Port ( a : in STD_LOGIC; b : in STD_LOGIC; Cin : in STD_LOGIC; Cout : out STD_LOGIC; sum : out STD_LOGIC); end fa_data; architecture Behavioral of fa_data is begin sum <= a xor b xor Cin; Cout <= ((a and b) or (b and Cin) or (a and Cin)); end Behavioral;

RTL Schematic:

Technology Schematic:

Output:

1.2.3) Structural Modelling --------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use UNISIM.VComponents.all; entity fa_struct is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; cout : out STD_LOGIC); end fa_struct; architecture Behavioral of fa_struct is component HA is Port ( P : in STD_LOGIC; Q : in STD_LOGIC; Sum : out STD_LOGIC; Carry : out STD_LOGIC); end component; component or_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end component; signal s1,s2,s3 : std_logic; begin xx3 : HA port map (a,b,s1,s2); xx4 : HA port map (s1,cin,sum,s3); xx5 : or_gate port map (s2,s3,cout); end Behavioral; ---------------------------------------------------------------------------------entity HA is Port ( P : in STD_LOGIC; Q : in STD_LOGIC; Sum : out STD_LOGIC; Carry : out STD_LOGIC); end HA; architecture Behavioral of HA is component and_gate port ( A,B : in std_logic; C: out std_logic ); end component ; component xor_gate port ( X,Y : in std_logic; Z: out std_logic );

end component ; begin A1 : and_gate port map(P,Q,Carry); X1 : xor_gate port map(P,Q,Sum); end Behavioral; ---------------------------------------------------------------------------------entity and_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end and_gate; architecture Behavioral of and_gate is begin C <= A and B; end Behavioral; ---------------------------------------------------------------------------------entity xor_gate is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; Z : out STD_LOGIC); end xor_gate; architecture Behavioral of xor_gate is begin Z <= X xor Y; end Behavioral; ---------------------------------------------------------------------------------entity or_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end or_gate; architecture Behavioral of or_gate is begin c <= a or b; end Behavioral; RTL Schematic:

Technology Schematic:

Output:

Conclusion: After implementing all modelling styles we conclude that for dataflow modelling path delay is least but the hardware is not optimum. Where In the behaviour modelling hardware is on the basis of branching or conditional statements (i.e. we have to know all system entities and its flow) where in the structural modelling path delay is maximum. But, this type of modelling is very optimum when we are calling bigger repetitive body again and again. The Maximum path delay for this is 6.236ns and LUTs are 2.