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Micromachines
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High-Reliability Semiconductor Devices and Integrated Circuits
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High-Reliability Semiconductor Devices and Integrated Circuits

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: closed (30 November 2023) | Viewed by 30363

Special Issue Editors

Dr. Yiqiang Chen

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Guest Editor
China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 511370, China
Interests: failure mechanism and model of key devices; prognostics and health management (PHM) of power conversion system (PCS); PHM of system on chip (SoC)
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Yi Liu

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Guest Editor
School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: integrated circuits design; simulation and evaluation method of radiation effects in aerospace integrated circuits
Special Issues, Collections and Topics in MDPI journals
Dr. Changqing Xu

E-Mail Website
Guest Editor
Guangzhou institute of Technology, School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: VLSI design and optimization; brain-inspired computing; EDA technology
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In this Special Issue on “High-Reliability Semiconductor Devices and Integrated Circuits”, we will focus on simulation, modeling, design, and optimization for high-reliability devices and integrated circuits for automobiles, avionics, and aerospace. High-reliability devices and integrated circuits are intensely studied because they are widely used in traditional aerospace electronic systems, avionics, automobiles, etc. In recent years, in addition to the development of traditional highly reliable devices and circuits, new technologies such as intelligent analysis, optimization, and manufacturing based on artificial intelligence and other novel technologies have brought vitality to the field of high-reliability devices and circuits.

The objective of this Special Issue is to collect research works focused on mathematical models, high-efficiency/-precision numerical solution methods, and intelligent design and optimization methods for high-reliability materials and devices and integrated circuits. We welcome novel works reporting on high-reliability devices and circuits and their applications to discuss the most recent breakthroughs and the potential impacts in related research fields. The specific topics of interest include, but are not limited to, the following:

  • Novel design method for high-reliability devices and integrated circuit;
  • Novel optimization technology for high-reliability devices and integrated circuit;
  • Advanced device structure or materials for high-reliability design;
  • Reliability analysis of the special environment, such as a strong magnetic field, radiation environment, etc.;
  • Application of novel technology, such as AI, in high-reliability design and analysis;
  • Novel simulation technology for functional safety.

Dr. Yiqiang Chen
Prof. Dr. Yi Liu
Dr. Changqing Xu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • high reliability
  • semiconductor devices
  • integrated circuits
  • strong magnetic field
  • radiation environment
  • intelligent design

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Related Special Issues

Published Papers (17 papers)

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Research

12 pages, 5039 KiB  
Article
Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset
by Hongwei Zhang, Yang Guo, Shida Wang, Yi Sun, Bo Mei, Min Tang and Jingyi Liu
Micromachines 2024, 15(2), 201; https://doi.org/10.3390/mi15020201 - 29 Jan 2024
Viewed by 1457
Abstract
Planar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses this gap by establishing a FinFET SRAM simulation structure [...] Read more.
Planar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses this gap by establishing a FinFET SRAM simulation structure and employing simulation software to delve into the charge collection process of FinFET devices during single-event upset. The results reveal substantial differences in charge collection between NMOS and PMOS, and that direct incidence of PMOS leads to the phenomenon of multiple-node charge collection causing SRAM unit upset followed by recovery. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
►▼ Show Figures

Figure 1

Figure 1
<p>Physical distribution of MCU in SRAM arrays horizontally corresponds to the bitline direction and vertically corresponds to the wordline direction [<a href="#B17-micromachines-15-00201" class="html-bibr">17</a>].</p> Full article ">Figure 2
<p>SRAM Simulation Models Based on FinFET Technology.</p> Full article ">Figure 3
<p>Calibration Curves of TCAD Model and SPICE Model: (<b>a</b>) PMOS; (<b>b</b>) NMOS.</p> Full article ">Figure 4
<p>Top View of the SRAM Model (the STI is hidden) and Circuit Interconnect.</p> Full article ">Figure 5
<p>The source current of the N1 transistor and the variation in drain voltage over time at 0.009 pC/μm.</p> Full article ">Figure 6
<p>Variation in N1 drain current over time for LET values of 0.1, 0.2, 0.3, and 0.5 pC/μm.</p> Full article ">Figure 7
<p>The Variation in Drain Current in N1 Transistor over Time for LET values ranging from 0.003 to 0.0011 pC/μm.</p> Full article ">Figure 8
<p>Variation in source and drain currents over time in the P2 transistor.</p> Full article ">Figure 9
<p>Time-dependent curve of Q-point voltage under high LET conditions.</p> Full article ">Figure 10
<p>Total current situation of P2 drain and source at LET = 0.7 pC/μm. Positive current values represent current flowing into the device; negative values represent current flowing out of the device.</p> Full article ">Figure 11
<p>Potential variation of P2 drain, source, and channel at LET = 0.7 pC/μm.</p> Full article ">Figure 12
<p>Time-dependent curve of <math display="inline"><semantics> <mrow> <mover accent="true"> <mrow> <mi mathvariant="normal">Q</mi> </mrow> <mo>¯</mo> </mover> </mrow> </semantics></math>-point voltage under high LET conditions.</p> Full article ">Figure 13
<p>3D TCAD process simulation before ion incident and after 0.01 ns, 10 ps, and 20 ps (the STI is hidden).</p> Full article ">
14 pages, 3557 KiB  
Article
A High-Accuracy RC Time Constant Auto-Tuning Scheme for Integrated Continuous-Time Filters
by Gang Jin, Hao Wu, Yue Yin, Lei Zheng and Yiqi Zhuang
Micromachines 2024, 15(1), 166; https://doi.org/10.3390/mi15010166 - 22 Jan 2024
Cited by 1 | Viewed by 1654
Abstract
The reliability of the resistor-capacitor (RC) time constant of a continuous-time (CT) filter has long been an obstacle with integrated circuits. Due to process and temperature variations in complementary metal-oxide semiconductor (CMOS) technology, the absolute value of the RC time constant may vary [...] Read more.
The reliability of the resistor-capacitor (RC) time constant of a continuous-time (CT) filter has long been an obstacle with integrated circuits. Due to process and temperature variations in complementary metal-oxide semiconductor (CMOS) technology, the absolute value of the RC time constant may vary over ±50%, which is a big issue for many integrated continuous-time analog circuits. This study proposes an on-chip RC time constant auto-tuning scheme. The proposed scheme is based on the discrete master–slave auto-tuning concept. Considering the limitations in conventional works, a higher tuning accuracy is achieved by adopting two techniques: firstly, parasitic capacitance cancelation is proposed to eliminate the effects caused by parasitic capacitance; secondly, symmetric comparison is introduced to minimize the influence of the DC offset of the comparator. A successive approximation procedure is applied to improve the tuning speed. The proposed auto-tuning scheme has been validated in 55 nm CMOS technology with a fourth-order active-RC low-pass filter under PVT variations and 60 mV input offset voltage. The average tuning error is 2.21%, and the maximum error is 3.67%. The tuning error of the proposed scheme is considerably lower than the conventional scheme. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
►▼ Show Figures

Figure 1

Figure 1
<p>MFB low-pass biquad.</p> Full article ">Figure 2
<p>The conventional master–slave tuning scheme.</p> Full article ">Figure 3
<p>The proposed master–slave scheme.</p> Full article ">Figure 4
<p>Transient waveforms of the proposed tuning circuit.</p> Full article ">Figure 5
<p>Flow chart of the four-phase tuning procedure.</p> Full article ">Figure 6
<p>The 4th-order low-pass active-RC filter.</p> Full article ">Figure 7
<p>Comparator circuit.</p> Full article ">Figure 8
<p>Simulated frequency response of the filter under PVT variations (<b>a</b>) before calibration and (<b>b</b>) after calibration.</p> Full article ">Figure 9
<p>Circuit area and power consumption of the tuning circuits.</p> Full article ">Figure 10
<p>Tuning error at different corners.</p> Full article ">
17 pages, 2001 KiB  
Article
Logical Resolving-Based Methodology for Efficient Reliability Analysis
by Zhengguang Tang, Cong Li, Hailong You, Xingming Liu, Yu Wang, Yong Dai, Geng Bai and Xiaoling Lin
Micromachines 2024, 15(1), 85; https://doi.org/10.3390/mi15010085 - 30 Dec 2023
Cited by 1 | Viewed by 1178
Abstract
With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has [...] Read more.
With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has recently focused on reliability-aware circuit analysis. Nevertheless, the aging dependence among different devices is not considered, which will induce errors of degradation evaluation in the digital circuit. In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. Experimental results show that the proposed method has a better evaluation accuracy of aging path delay than traditional strategies. For aging timing evaluation on aging paths, excessive pessimism can be reduced by employing the proposed method. And, a 378× speedup is achieved while having a 0.56% relative error compared with precise SPICE simulation. Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. Due to the high efficiency and high accuracy, the proposed method can meet the speed demands of large-scale digital circuit reliability analysis while achieving transistor simulation accuracy. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
►▼ Show Figures

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Figure 1
<p>The delay difference (aged delay—fresh delay) of FO4 under both NBTI and PBTI aging. The PTM model [<a href="#B7-micromachines-15-00085" class="html-bibr">7</a>] is used and the aging model will be given in <a href="#sec4dot1-micromachines-15-00085" class="html-sec">Section 4.1</a>.</p> Full article ">Figure 2
<p>The aging STA flow is based on analytical SP calculation. Note that SP is one of the parameters in the long-term aging model (see <a href="#sec4dot1-micromachines-15-00085" class="html-sec">Section 4.1</a>), and the aging result <math display="inline"> <semantics> <mo>Δ</mo> </semantics> </math><span class="html-italic">V</span><sub>th</sub> is obtained based on SP.</p> Full article ">Figure 3
<p>Circuit-level schematic of a full adder. Where <span class="html-italic">A</span>, <span class="html-italic">B</span>, and <math display="inline"> <semantics> <mrow> <mi>C</mi> <mi>I</mi> </mrow> </semantics> </math> are input signals and <math display="inline"> <semantics> <mrow> <mi>C</mi> <mn>0</mn> </mrow> </semantics> </math> and <span class="html-italic">S</span> are output signals. The stages are split based on the standard of intermediate signal serving as the output or driving signal.</p> Full article ">Figure 4
<p>NBTI normalized <span class="html-italic">SP</span> and <math display="inline"> <semantics> <mo>Δ</mo> </semantics> </math><span class="html-italic">V</span><sub>th</sub> degradation of <span class="html-italic">MP</span>5 (<b>a</b>) and <span class="html-italic">MP</span>10 (<b>b</b>) in full adder based on the conventional algorithm and the method considering aging dependence.</p> Full article ">Figure 5
<p>BDD structure of BTI stress function and the final result for (<b>a</b>) <span class="html-italic">MP</span>5 and (<b>b</b>) <span class="html-italic">MP</span>10, where the endpoint “0” presents that the logic combinations will not cause degradation, and endpoint “1” is the opposite.</p> Full article ">Figure 6
<p>Calibrations of the experimental data for aging model, all the experiment data come from [<a href="#B28-micromachines-15-00085" class="html-bibr">28</a>]: (<b>a</b>) the data for NBTI and PBTI aging under DC stress and model fitting; and (<b>b</b>) the data for NBTI and PBTI aging under AC stress and model fitting, where the AC stress time equals 1000 s.</p> Full article ">Figure 7
<p>Evaluation flow of aging-aware STA for the critical paths.</p> Full article ">Figure 8
<p>The aged delay of FA_X1 under different workloads, where the random waveform for workloads is generated by applying the perjitter command [<a href="#B32-micromachines-15-00085" class="html-bibr">32</a>] in commercial SPICE simulation tool [<a href="#B22-micromachines-15-00085" class="html-bibr">22</a>].</p> Full article ">Figure 9
<p>The analysis flow of the timing guardband and aging-aware synthesis.</p> Full article ">Figure 10
<p>Performance, power, and area of aging-aware synthesis result comparison between the proposed and conventional analytical [<a href="#B16-micromachines-15-00085" class="html-bibr">16</a>] method: (<b>a</b>) clock period; (<b>b</b>) synthesis area; and (<b>c</b>) total power consumption.</p> Full article ">
15 pages, 3906 KiB  
Article
Study on Cavitation, Warpage Deformation, and Moisture Diffusion of Sop-8 Devices during Molding Process
by Wenchao Tian, Shuaiqi Zhang, Wenbin Li, Yuanming Chen, Jingrong Zhao, Fei Xin, Yingying Qian and Wenhua Li
Micromachines 2023, 14(12), 2175; https://doi.org/10.3390/mi14122175 - 29 Nov 2023
Cited by 1 | Viewed by 1509
Abstract
Plastic packaging has shown its advantages over ceramic packaging and metal packaging in lightweight, thin, and high-density electronic devices. In this paper, the reliability and moisture diffusion of Sop-8 (Small Out-Line Package-8) plastic packaging devices are studied, and we put forward a set [...] Read more.
Plastic packaging has shown its advantages over ceramic packaging and metal packaging in lightweight, thin, and high-density electronic devices. In this paper, the reliability and moisture diffusion of Sop-8 (Small Out-Line Package-8) plastic packaging devices are studied, and we put forward a set of complete optimization methods. Firstly, we propose to improve the reliability of plastic packaging devices by reducing the amount of cavitation and warpage deformation. Structural and process factors were investigated in the injection molding process. An orthogonal experiment design was used to create 25 groups of simulation experiments, and Moldflow software was used to simulate the flow mode analysis. Then, the simulation results are subjected to range analysis and comprehensive weighted score analysis. Finally, different optimization methods are proposed according to different production conditions, and each optimization method can reduce cavitation or warpage by more than 9%. The moisture diffusion of the Sop-8 plastic packing devices was also investigated at the same time. It was determined that the contact surface between the lead frame and the plastic packaging material was more likely to exhibit delamination under the condition of MSL2 moisture diffusion because the humidity gradient was easily produced at the crucial points of different materials. The diffusion of moisture is related to the type of plastic packaging material and the diffusion path. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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Figure 1

Figure 1
<p>Cavitation failure diagram.</p> Full article ">Figure 2
<p>Three-dimensional simulation model. (<b>a</b>) Three-dimensional model of the lead frame; (<b>b</b>) Three-dimensional explosion diagram of the model.</p> Full article ">Figure 3
<p>Acoustic sweep after high-temperature steam test. (<b>a</b>) Initial scheme experiment; (<b>b</b>) Optimized scheme experiment.</p> Full article ">Figure 4
<p>SOP-8 structure diagram.</p> Full article ">Figure 5
<p>SOP-8 devices dimensions. (<b>a</b>) Front view; (<b>b</b>) Right view. (<b>c</b>) Top view.</p> Full article ">Figure 6
<p>Node location of SOP-8 plastic packaging devices.</p> Full article ">Figure 7
<p>Wet stress and wet deformation diagrams of SOP-8 plastic packaging devices. (<b>a</b>) Wet stress diagram of SOP-8 plastic packaging devices; (<b>b</b>) Wet deformation diagram of SOP-8 plastic packaging devices.</p> Full article ">
13 pages, 2936 KiB  
Article
An Improved Model of Single-Event Transients Based on Effective Space Charge for Metal–Oxide–Semiconductor Field-Effect Transistor
by Yutao Zhang, Hongliang Lu, Chen Liu, Yuming Zhang, Ruxue Yao and Xingming Liu
Micromachines 2023, 14(11), 2085; https://doi.org/10.3390/mi14112085 - 11 Nov 2023
Viewed by 1217
Abstract
In this paper, a single-event transient model based on the effective space charge for MOSFETs is proposed. The physical process of deposited and moving charges is analyzed in detail. The influence of deposited charges on the electric field in the depletion region is [...] Read more.
In this paper, a single-event transient model based on the effective space charge for MOSFETs is proposed. The physical process of deposited and moving charges is analyzed in detail. The influence of deposited charges on the electric field in the depletion region is investigated. The electric field decreases in a short time period due to the neutralization of the space charge. After that, the electric field increases first and then decreases when the deposited charge is moved out. The movement of the deposited charge in the body mainly occurs through ambipolar diffusion because of its high-density electrons and holes. The derivation of the variation in electric field in the depletion region is modeled in the physical process according to the analysis. In combination with the ambipolar diffusion model of excessive charge in the body, a physics-based model is built to describe the current pulse in the drain terminal. The proposed model takes into account the influence of multiple factors, like linear-energy transfer (LET), drain bias, and the doping concentration of the well. The model results are validated with the simulation results from TCAD. Through calculation, the root-mean-square error (RMSE) between the simulation and model is less than 3.7 × 10−4, which means that the model matches well with the TCAD results. Moreover, a CMOS inverter is simulated using TCAD and SPICE to validate the applicability of the proposed model in a circuit-level simulation. The proposed model captures the variation in net voltage in the inverter. The simulation result obviously shows the current plateau effect, while the relative error of the pulse width is 23.5%, much better than that in the classic model. In comparison with the classic model, the proposed model provides an RMSE of 7.59 × 10−5 for the output current curve and an RMSE of 0.158 for the output voltage curve, which are significantly better than those of the classic model. In the meantime, the proposed model does not produce extra simulation time compared with the classic double exponential model. So, the model has potential for application to flow estimation of the soft error rate (SER) at the circuit level to improve the accuracy of the results. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
►▼ Show Figures

Figure 1

Figure 1
<p>NMOS structure schematic using 45 nm CMOS technology. The electrode of body is on the top of bulk, which is connected with source.</p> Full article ">Figure 2
<p>Simulated Id-Vg curves compared with PDK results.</p> Full article ">Figure 3
<p>Single-event transient current in drain terminal with an LET of 0.5 pC/μm and a characteristic radius of 0.05 μm. Six points of time that cover almost the whole process of SET are chosen to extract the electronic parameters, which are marked using points and texts.</p> Full article ">Figure 4
<p>Space charge around metallurgical junction extracted along the cutline at different time points. The red dashed line indicates the metallurgical junction.</p> Full article ">Figure 5
<p>Electric field extracted along the cutline at different time points. The red dashed line indicates the metallurgical junction and the blue dashed line indicates the border of original depletion region.</p> Full article ">Figure 6
<p>Electron and hole densities in the body are extracted along the cutline at different time points. The inset picture indicates the carriers’ density close to the metallurgical junction.</p> Full article ">Figure 7
<p>The schematic illustration of the physical process after heavy ion injects into devices.</p> Full article ">Figure 8
<p>SET current curves versus time for different LETs. The voltages setting is V<sub>G</sub> = V<sub>S</sub> = 0 V, V<sub>D</sub> = 1 V.</p> Full article ">Figure 9
<p>SET current curves versus time for different drain voltages. The voltages setting is V<sub>G</sub> = V<sub>S</sub> = 0 V and the LET is 0.6 pC/μm.</p> Full article ">Figure 10
<p>SET current comparison between TCAD, proposed model, and double exponential model. The voltage setting is V<sub>G</sub> = V<sub>S</sub> = 0 V and V<sub>D</sub> = 0.2 V and the LET is 0.6 pC/μm.</p> Full article ">Figure 11
<p>Vout-Vin results in TCAD and SPICE.</p> Full article ">Figure 12
<p>Output voltage comparison among proposed model, double exponential model, and TCAD simulation in inverter SET simulation. The input state is Vin = 0 V and the LET is 1 pC/μm. A green dashed line is drawn in the figure indicating the 0 V voltage level.</p> Full article ">Figure 13
<p>Output current comparison among proposed model results, double exponential model, and TCAD in inverter SET simulation. The input state is Vin = 0 V and the LET is 1 pC/μm. The green dashed box indicates the current plateau effect. The inset figure is an enlarged view of simulation results based on proposed model and TCAD.</p> Full article ">
12 pages, 6622 KiB  
Article
A Novel Super-Junction DT-MOS with Floating p Regions to Improve Short-Circuit Ruggedness
by Sujie Yin, Wei Cao, Xiarong Hu, Xinglai Ge and Dong Liu
Micromachines 2023, 14(10), 1962; https://doi.org/10.3390/mi14101962 - 21 Oct 2023
Viewed by 1738
Abstract
A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t [...] Read more.
A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (tsc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (Ron,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Qgd) and gate-drain capacitance (Cgd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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Figure 1

Figure 1
<p>Cross-sectional structures of (<b>a</b>) DT-MOS, (<b>b</b>) SJ-DTMOS, and (<b>c</b>) proposed MOSFET (drawing not to scale).</p> Full article ">Figure 2
<p>The simulation results of (<b>a</b>) <span class="html-italic">BV</span> characteristics, (<b>b</b>) vertical electric field distribution along <span class="html-italic">x</span> = 0.6 μm at breakdown, (<b>c</b>) <span class="html-italic">I</span>-<span class="html-italic">V</span> characteristics at low drain voltages, and (<b>d</b>) <span class="html-italic">I</span>-<span class="html-italic">V</span> characteristics (<span class="html-italic">V</span><sub>ds</sub> from 0 to 800 V).</p> Full article ">Figure 2 Cont.
<p>The simulation results of (<b>a</b>) <span class="html-italic">BV</span> characteristics, (<b>b</b>) vertical electric field distribution along <span class="html-italic">x</span> = 0.6 μm at breakdown, (<b>c</b>) <span class="html-italic">I</span>-<span class="html-italic">V</span> characteristics at low drain voltages, and (<b>d</b>) <span class="html-italic">I</span>-<span class="html-italic">V</span> characteristics (<span class="html-italic">V</span><sub>ds</sub> from 0 to 800 V).</p> Full article ">Figure 3
<p>Electric field contours of the three devices with <span class="html-italic">V</span><sub>d</sub> = 1200 V.</p> Full article ">Figure 4
<p>(<b>a</b>) Effect of the <span class="html-italic">N</span><sub>P</sub> on <span class="html-italic">BV</span> of SJ-DTMOS and the proposed MOSFET with a different <span class="html-italic">N</span><sub>N</sub>. (<b>b</b>) Relationship between the <span class="html-italic">BFOM</span> and <span class="html-italic">R</span><sub>on,sp</sub> of two devices under different <span class="html-italic">N</span><sub>N</sub>.</p> Full article ">Figure 5
<p>The effects of (<b>a</b>) <span class="html-italic">N</span><sub>p-region</sub>, (<b>b</b>) <span class="html-italic">h</span>, and (<b>c</b>) <span class="html-italic">w</span> on the static characteristics of the proposed MOSFET.</p> Full article ">Figure 6
<p>The effect of process deviation on the breakdown voltage (<span class="html-italic">BV</span>), specific on-resistance (<span class="html-italic">R</span><sub>on,sp</sub>), and saturation current density (<span class="html-italic">I</span><sub>sat</sub>) of the device.</p> Full article ">Figure 7
<p>(<b>a</b>) Capacitance characteristics for the three studied devices. (<b>b</b>) Gate charge characteristic curves of three studied devices. (<b>c</b>) Gate charge test circuit.</p> Full article ">Figure 8
<p>(<b>a</b>) Voltage and current waveforms of the three studied MOSFETs during double-pulse testing. (<b>b</b>) Power losses of the three studied MOSFETs during turn-on and turn-off.</p> Full article ">Figure 9
<p>Multiple switching of the three studied MOSFETs: (<b>a</b>) <span class="html-italic">V</span><sub>ds</sub>, (<b>b</b>) <span class="html-italic">I</span><sub>density</sub>, (<b>c</b>) <span class="html-italic">R</span><sub>d</sub>.</p> Full article ">Figure 10
<p>(<b>a</b>) Voltage and current waveforms of the three MOSFETs during the short circuit. (<b>b</b>) Short-circuit test circuit.</p> Full article ">Figure 11
<p>(<b>a</b>) Total current and temperature waveforms for the three studied devices during short-circuit conditions (600 V dc bus voltage). (<b>b</b>) Lattice temperature distribution of the DT-MOS (at <span class="html-italic">t</span> = 11 μs, 20 μs), the SJ-DTMOS (at <span class="html-italic">t</span> = 11 μs, 50 μs), and the proposed MOSFET (at <span class="html-italic">t</span> = 11 μs, 50 μs). (<b>c</b>) Total current density distribution of the DT-MOS (at <span class="html-italic">t</span> = 11 μs, 20 μs), the SJ-DTMOS (at <span class="html-italic">t</span> = 11 μs, 50 μs), and the proposed MOSFET (at <span class="html-italic">t</span> = 11 μs, 50 μs).</p> Full article ">Figure 12
<p>The key processing steps to fabricate the SJ structure with floating p regions. (<b>a</b>) Substrate wafer with first epitaxy. (<b>b</b>) Masked aluminum (Al) implantation to form p-pillar. (<b>c</b>) Masked Al implantation to form p-pillar and floating p regions. (<b>d</b>) Multiple epitaxy and ion implantation to form SJ structure with floating p regions.</p> Full article ">Figure 13
<p>The fabrication process flow of the proposed MOSFET: (<b>a</b>) Substrate wafer with first epitaxy. (<b>b</b>) Super-junction structure with floating p regions formed through multiple epitaxy and ion implantation. (<b>c</b>) Epitaxy and ion implantation form CSL and p+ region. (<b>d</b>) Formation of p-well through epitaxy. (<b>e</b>) Formation of N+ region through epitaxy. (<b>f</b>) Trench etching. (<b>g</b>) Thermal oxidation of gate oxide and deposition of polysilicon gate. (<b>h</b>) Deposition of the interlayer dielectric (ILD). (<b>i</b>) Metallization forms contacts.</p> Full article ">
14 pages, 1759 KiB  
Article
A Fast Simulation Method for Evaluating the Single-Event Effect in Aerospace Integrated Circuits
by Xiaorui Zhang, Yi Liu, Changqing Xu, Xinfang Liao, Dongdong Chen and Yintang Yang
Micromachines 2023, 14(10), 1887; https://doi.org/10.3390/mi14101887 - 30 Sep 2023
Cited by 1 | Viewed by 1177
Abstract
With the continuous progress in integrated circuit technology, single-event effect (SEE) has become a key factor affecting the reliability of aerospace integrated circuits. Simulating fault injection using the computer simulation technique effectively reflects the SEE in aerospace integrated circuits. Due to various masking [...] Read more.
With the continuous progress in integrated circuit technology, single-event effect (SEE) has become a key factor affecting the reliability of aerospace integrated circuits. Simulating fault injection using the computer simulation technique effectively reflects the SEE in aerospace integrated circuits. Due to various masking effects, only a small number of faults will result in errors; the traditional method of injecting one fault in one workload execution is inefficient. The method of injecting multiple faults in one workload execution will make it impossible to judge which fault results in errors because the propagation characteristic of SEE and faults may affect each other. This paper proposes an improved multi-point fault injection method to improve simulation efficiency and solve the problems of the general multi-point fault injection method. If one workload execution does not result in errors, multiple faults can be verified by one workload execution. If one workload execution results in errors, a specific grouping method can be used to determine which faults result in errors. The experimental results show that the proposed method achieves a good acceleration effect and significantly improves the simulation efficiency. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Mixture simulation method.</p> Full article ">Figure 2
<p>The process of deciding whether to group the injected faults.</p> Full article ">Figure 3
<p>The structure of one multi-point fault injection process.</p> Full article ">Figure 4
<p>There are four structures and the number of the first layer faults is 8: (<b>a</b>) the number of error faults is 0 and the number of workload executions required is 1; (<b>b</b>) the number of error faults is 1 and the number of workload executions required is 7; (<b>c</b>) the number of error faults is 2 and the number of workload executions required is 9; (<b>d</b>) the number of error faults is 2 and the number of workload executions required is 11.</p> Full article ">Figure 5
<p>The process of determining error checkpoints.</p> Full article ">Figure 6
<p>The process of one multi-point fault injection process with addition of checkpoints.</p> Full article ">Figure 7
<p>The overall simulation flow.</p> Full article ">Figure 8
<p>The structure of the Leon2 system.</p> Full article ">
13 pages, 10649 KiB  
Article
Investigation of the Degradation Mechanism of SiC MOSFET Subjected to Multiple Stresses
by Huifen Dong, Yunxia Wu, Chan Li and Hai Xu
Micromachines 2023, 14(7), 1469; https://doi.org/10.3390/mi14071469 - 21 Jul 2023
Cited by 1 | Viewed by 1750
Abstract
The performance requirements for power devices in airborne equipment are increasingly demanding, while environmental and working stresses are becoming more diverse. The degradation mechanisms of devices subjected to multiple stresses become more complex. Most proposed degradation mechanisms and models in current research only [...] Read more.
The performance requirements for power devices in airborne equipment are increasingly demanding, while environmental and working stresses are becoming more diverse. The degradation mechanisms of devices subjected to multiple stresses become more complex. Most proposed degradation mechanisms and models in current research only consider a single stress, making it difficult to describe the correlation between multiple stresses and the correlation of failures. Then, a multi-physical field coupling model based on COMSOL is proposed. The influence relationship between temperature, moisture, electrical load, and vibration during device operation is considered, and a three-dimensional finite element model is built to investigate the multi-stress degradation mechanism under multi-physical field coupling. The simulation results show that, compared with single-stress models, the proposed multi-stress coupled model can more accurately simulate the degradation process of SiC MOSFET. This provides references for improving the reliability design of power device packaging. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Coupling relationship between fields. Where <math display="inline"><semantics> <mrow> <mi mathvariant="normal">J</mi> </mrow> </semantics></math> is the current density; <math display="inline"><semantics> <mrow> <mi mathvariant="sans-serif">σ</mi> </mrow> </semantics></math> is the conductivity; <math display="inline"><semantics> <mrow> <msub> <mrow> <mi mathvariant="normal">P</mi> </mrow> <mrow> <mi mathvariant="normal">s</mi> <mi mathvariant="normal">a</mi> <mi mathvariant="normal">t</mi> </mrow> </msub> </mrow> </semantics></math> is the vapor saturation pressure; <math display="inline"><semantics> <mrow> <msub> <mrow> <mi mathvariant="normal">k</mi> </mrow> <mrow> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">f</mi> <mi mathvariant="normal">f</mi> </mrow> </msub> </mrow> </semantics></math> is the effective thermal conductivity; <math display="inline"><semantics> <mrow> <mi mathvariant="normal">Q</mi> </mrow> </semantics></math> is the heat source; <math display="inline"><semantics> <mrow> <mi mathvariant="normal">D</mi> </mrow> </semantics></math> is the diffusion coefficient; <math display="inline"><semantics> <mrow> <mi mathvariant="normal">e</mi> </mrow> </semantics></math> is the modulus of elasticity; and <math display="inline"><semantics> <mrow> <mo>[</mo> <mi mathvariant="normal">K</mi> <mo>]</mo> </mrow> </semantics></math> is the structural stiffness matrix.</p> Full article ">Figure 2
<p>Three-dimensional model of SiC MOSFET.</p> Full article ">Figure 3
<p>Thermal stress distribution diagram (MPa). (<b>a</b>) The SiC device thermal stress distribution diagram. (<b>b</b>) Chip solder layer thermal stress distribution diagram.</p> Full article ">Figure 4
<p>Chip solder layer temperature and stress average curve.</p> Full article ">Figure 5
<p>Switching times definition.</p> Full article ">Figure 6
<p>Switching time at different junction temperatures. (<b>a</b>) Turn−on delay time. (<b>b</b>) Rise time. (<b>c</b>) Turn−off delay time. (<b>d</b>) Fall time.</p> Full article ">Figure 7
<p>Interaction laws in thermal–moisture coupling fields. (<b>a</b>) Relative moisture and temperature change patterns with time. (<b>b</b>) The effect law of thermal–moisture coupling on relative moisture. (<b>c</b>) The effect law of thermal–moisture coupling on temperature.</p> Full article ">Figure 8
<p>Silica gel layer concentration distribution (mol/m<sup>3</sup>). (<b>a</b>) Moisture field. (<b>b</b>) Thermal−moisture coupling field.</p> Full article ">Figure 9
<p>Moisture stress distribution (MPa). (<b>a</b>) Passivation layer. (<b>b</b>) Solder layer.</p> Full article ">Figure 10
<p>Analysis of stress results for the silica gel layer (MPa). (<b>a</b>) Thermal stress. (<b>b</b>) Moisture stress. (<b>c</b>) Stress after thermal−moisture coupling.</p> Full article ">Figure 11
<p>Acceleration power spectral density.</p> Full article ">Figure 12
<p>The natural frequencies of the device under different fields.</p> Full article ">
13 pages, 4293 KiB  
Article
Simulation of Total Ionizing Dose Effects Technique for CMOS Inverter Circuit
by Tianzhi Gao, Chenyu Yin, Yaolin Chen, Ruibo Chen, Cong Yan and Hongxia Liu
Micromachines 2023, 14(7), 1438; https://doi.org/10.3390/mi14071438 - 18 Jul 2023
Cited by 1 | Viewed by 2026
Abstract
The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on–off function of devices. At present, most of the irradiation research on the circuit level is focused on the single [...] Read more.
The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on–off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and there is very little research on the total ionizing dose effect. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose was 400 krad (Si), the logic threshold drift of the inverter was approximately 0.052 V. These results help further investigate the impact on integrated circuits in an irradiation environment. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Calibration model: structure of (<b>a</b>) NMOS and (<b>b</b>) PMOS.2.2.</p> Full article ">Figure 2
<p>The test device diagram.</p> Full article ">Figure 3
<p>Layout file: (<b>a</b>) NMOS; (<b>b</b>) PMOS.</p> Full article ">Figure 4
<p>Comparison of the experimental transfer characteristic curves of the NMOS devices. When simulating irradiation, the bias was set as Vds = 0.1 V/0.8 V.</p> Full article ">Figure 5
<p>Comparison of the experimental transfer characteristic curves of the PMOS devices. When simulating irradiation, the bias was set as Vds = −0.1 V/−0.8 V.</p> Full article ">Figure 6
<p>When simulating irradiation, the bias was set as Vds = 0.1 V. The I–V curves are plotted before irradiation and at several TID steps (gray curves) up to 800 k rad (Si).</p> Full article ">Figure 7
<p>When simulating irradiation, the bias was set as Vds = −0.1 V. The I–V curves are plotted before irradiation and at several TID steps (gray curves) up to 800 k rad (Si).</p> Full article ">Figure 8
<p>Variation in the threshold voltage drift under different irradiation doses: (<b>a</b>) NMOS; (<b>b</b>) PMOS.</p> Full article ">Figure 9
<p>The distribution of trapped charge in the BOX layer of NMOS devices after dose irradiation: (<b>a</b>) 100 krad; (<b>b</b>) 300 krad; (<b>c</b>) 500 krad; (<b>d</b>) 700 krad; (<b>e</b>) 1 Mrad (Si).</p> Full article ">Figure 10
<p>The distribution of trapped charge in a BOX layer of PMOS devices after dose irradiation: (<b>a</b>) 100 krad; (<b>b</b>) 300 krad; (<b>c</b>) 500 krad; (<b>d</b>) 700 krad; (<b>e</b>) 1 Mrad (Si).</p> Full article ">Figure 11
<p>Transfer characteristics of the experiments and simulations: (<b>a</b>) NMOS; (<b>b</b>) PMOS.</p> Full article ">Figure 12
<p>Variation in the threshold voltage of the experiments and simulations: (<b>a</b>) NMOS; (<b>b</b>) PMOS.</p> Full article ">Figure 13
<p>The inverter structure.</p> Full article ">Figure 14
<p>Voltage–transfer curve (VTC) of the inverter for different total ionizing doses.</p> Full article ">Figure 15
<p>The voltage–gain curve of the inverter for different total ionizing doses.</p> Full article ">Figure 16
<p>The logic threshold (V<sub>M</sub>) of the inverter for different total ionizing doses.</p> Full article ">Figure 17
<p>Noise tolerance of the (<b>a</b>) logic high level (N<sub>MH</sub>) and (<b>b</b>) low level (N<sub>ML</sub>) of the inverter for different total ionizing doses.</p> Full article ">
12 pages, 19795 KiB  
Article
A 17.8–20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers
by Javier del Pino, Sunil L. Khemchandani, Mario San-Miguel-Montesdeoca, Sergio Mateos-Angulo, Daniel Mayor-Duarte, Jose Luis Saiz-Perez and David Galante-Sempere
Micromachines 2023, 14(6), 1184; https://doi.org/10.3390/mi14061184 - 31 May 2023
Viewed by 1768
Abstract
This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 [...] Read more.
This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 to 20.2 GHz frequency range. The proposed architecture uses four variable gain amplifiers (VGA) that are active at any given time and are switched to generate the four quadrants. Compared to conventional architectures, this structure is more compact and produces double the output amplitude. The design offers 6-bit phase control for 360°, and the total root mean square (RMS) phase and gain errors are 2.36° and 1.46 dB, respectively. The design occupies an area of 1309.4 μm × 1783.8 μm (including pads). Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Phased array block diagram.</p> Full article ">Figure 2
<p>Single-ended vector-sum phase shifters: (<b>a</b>) 90° based on two non-inverting amplifiers; (<b>b</b>) 360° based on two inverting and two non-inverting amplifiers; (<b>c</b>) 360° based on four non-inverting amplifiers with crossed outputs.</p> Full article ">Figure 3
<p>Differential vector-sum phase shifters: (<b>a</b>) 360° based on a double Gilbert-cell; (<b>b</b>) 360° based on a single Gilbert-cell and an adder at the output; (<b>c</b>) 360° based on a single Gilbert-cell, a subtracter at the output, and four switches to control the quadrant (proposed architecture).</p> Full article ">Figure 3 Cont.
<p>Differential vector-sum phase shifters: (<b>a</b>) 360° based on a double Gilbert-cell; (<b>b</b>) 360° based on a single Gilbert-cell and an adder at the output; (<b>c</b>) 360° based on a single Gilbert-cell, a subtracter at the output, and four switches to control the quadrant (proposed architecture).</p> Full article ">Figure 4
<p>Constellations: (<b>a</b>) generated from <a href="#micromachines-14-01184-f003" class="html-fig">Figure 3</a>b circuit; (<b>b</b>) generated from <a href="#micromachines-14-01184-f003" class="html-fig">Figure 3</a>c circuit.</p> Full article ">Figure 5
<p>Implementation of the architecture proposed in <a href="#micromachines-14-01184-f003" class="html-fig">Figure 3</a>c based on bipolar transistors: (<b>a</b>) schematic of the VGAs; (<b>b</b>) input balun, differential I/Q generator, and matching network; (<b>c</b>) output subtractor based on a differential amplifier and buffer.</p> Full article ">Figure 6
<p>Marchand balun: (<b>a</b>) distributed model, (<b>b</b>) lumped model, and (<b>c</b>) 3-D momentum model.</p> Full article ">Figure 7
<p>Die photograph of the fabricated chip.</p> Full article ">Figure 8
<p>Measurement setup: (<b>a</b>) blocks diagram and (<b>b</b>) photograph.</p> Full article ">Figure 9
<p>Simulated and measured phase shifting at 19 GHz (polar plot).</p> Full article ">Figure 10
<p>Measured frequency response: (<b>a</b>) phase-shift, (<b>b</b>) S21, (<b>c</b>) S11, and (<b>d</b>) S22.</p> Full article ">
10 pages, 2951 KiB  
Article
Research on Temperature Dependence of Single-Event Burnout in Power MOSFETs
by Chen Wang, Yi Liu, Changqing Xu, Xinfang Liao, Dongdong Chen and Zhenyu Wu
Micromachines 2023, 14(5), 1028; https://doi.org/10.3390/mi14051028 - 11 May 2023
Cited by 2 | Viewed by 1921
Abstract
Power MOSFETs are found to be very vulnerable to single-event burnout (SEB) in space irradiation environments, and the military components generally require that devices could operate reliably as the temperature varies from 218 K to 423 K (−55 °C to 150 °C); thus, [...] Read more.
Power MOSFETs are found to be very vulnerable to single-event burnout (SEB) in space irradiation environments, and the military components generally require that devices could operate reliably as the temperature varies from 218 K to 423 K (−55 °C to 150 °C); thus, the temperature dependence of single-event burnout (SEB) in power MOSFETs should be investigated. Our simulation results showed that the Si power MOSFETs are more tolerant to SEB at a higher temperature at the lower LET (10 MeV∙cm2/mg) due to the decrease of the impact ionization rate, which is in good agreement with the previous research. However, the state of the parasitic BJT plays a primary role in the SEB failure mechanism when the LET value is greater than 40 MeV∙cm2/mg, which exhibits a completely different temperature dependence from that of 10 MeV∙cm2/mg. Results indicate that with the temperature increasing, the lower difficulty to turn on the parasitic BJT and the increasing current gain all make it easier to build up the regenerative feedback process responsible for SEB failure. As a result, the SEB susceptibility of power MOSFETs increases as ambient temperature increases when the LET value is greater than 40 MeV∙cm2/mg. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Schematic cross-sectional view of the simulated power MOSFET.</p> Full article ">Figure 2
<p>Static characteristics of the power MOSFET device (<b>a</b>) breakdown characteristic and (<b>b</b>) transfer characteristic.</p> Full article ">Figure 3
<p>SEB threshold voltage as a function of the ion strike position (LET = 75 MeV∙cm<sup>2</sup>/mg).</p> Full article ">Figure 4
<p>Relationship between <span class="html-italic">V<sub>th, SEB,</sub></span> and ambient temperature as a function of LET.</p> Full article ">Figure 5
<p>The impact generation rate distributions of the device at (<b>a</b>) Ta = 250 K, (<b>b</b>) Ta = 423 K, (<b>c</b>) Ta = 250 K, (<b>d</b>) Ta = 423 K after the ion strike under condition A (LET = 10 MeV∙cm<sup>2</sup>/mg, Vds = 300 V).</p> Full article ">Figure 6
<p>The temperature response after the ion strike under condition A (LET = 10 MeV∙cm<sup>2</sup>/mg and Vds = 300 V).</p> Full article ">Figure 7
<p>The SEB response of the power MOSFET at different Ta under condition B (LET = 100 MeV∙cm<sup>2</sup>/mg and Vds = 100 V) (<b>a</b>) temperature responses and (<b>b</b>) drain current responses.</p> Full article ">Figure 8
<p>The electric field distributions of power MOSFET after an ion’s strike at (<b>a</b>) LET = 10 MeV∙cm<sup>2</sup>/mg and (<b>b</b>) LET = 100 MeV∙cm<sup>2</sup>/mg (Ta = 250 K, Vds = 300 V).</p> Full article ">Figure 9
<p>The electron current density distributions near the parasitic BJT after the ion strike at (<b>a</b>) Ta = 250 K and (<b>b</b>) Ta = 423 K under condition B.</p> Full article ">Figure 10
<p>The minority carrier electron lifetime distribution in the base region under condition B after the ion strike 500 ps at (<b>a</b>) Ta = 250 K and (<b>b</b>) Ta = 423 K.</p> Full article ">
12 pages, 1852 KiB  
Article
Performance Degradation Modeling and Its Prediction Algorithm of an IGBT Gate Oxide Layer Based on a CNN-LSTM Network
by Xin Wang, Zhenwei Zhou, Shilie He, Junbin Liu and Wei Cui
Micromachines 2023, 14(5), 959; https://doi.org/10.3390/mi14050959 - 28 Apr 2023
Cited by 2 | Viewed by 1917
Abstract
The problem of health status prediction of insulated-gate bipolar transistors (IGBTs) has gained significant attention in the field of health management of power electronic equipment. The performance degradation of the IGBT gate oxide layer is one of the most important failure modes. In [...] Read more.
The problem of health status prediction of insulated-gate bipolar transistors (IGBTs) has gained significant attention in the field of health management of power electronic equipment. The performance degradation of the IGBT gate oxide layer is one of the most important failure modes. In view of failure mechanism analysis and the easy implementation of monitoring circuits, this paper selects the gate leakage current of an IGBT as the precursor parameter of gate oxide degradation, and uses time domain characteristic analysis, gray correlation degree, Mahalanobis distance, Kalman filter, and other methods to carry out feature selection and fusion. Finally, it obtains a health indicator, characterizing the degradation of IGBT gate oxide. The degradation prediction model of the IGBT gate oxide layer is constructed by the Convolutional Neural Network and Long Short-Term Memory (CNN-LSTM) Network, which show the highest fitting accuracy compared with Long Short-Term Memory (LSTM), Convolutional Neural Network (CNN), Support Vector Regression (SVR), Gaussian Process Regression (GPR), and CNN-LSTM models in our experiment. The extraction of the health indicator and the construction and verification of the degradation prediction model are carried out on the dataset released by the NASA-Ames Laboratory, and the average absolute error of performance degradation prediction is as low as 0.0216. These results show the feasibility of the gate leakage current as a precursor parameter of IGBT gate oxide layer failure, as well as the accuracy and reliability of the CNN-LSTM prediction model. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Construction of Performance Degradation Indicator of IGBT.</p> Full article ">Figure 2
<p>Dynamic curve of grid current.</p> Full article ">Figure 3
<p>Thermal diagram of correlation f I<sub>G</sub> time-domain feature.</p> Full article ">Figure 4
<p>Mahalanobis distance value of I<sub>G</sub>.</p> Full article ">Figure 5
<p>Flow chart of IGBT degradation prediction.</p> Full article ">Figure 6
<p>Forecast curves of CNN-LSTM, CNN, LSTM, SVR and GP models.</p> Full article ">
13 pages, 4357 KiB  
Article
Investigation of Anomalous Degradation Tendency of Low-Frequency Noise in Irradiated SOI-NMOSFETs
by Rui Liu, Linchun Gao, Juanjuan Wang, Tao Ni, Yifan Li, Runjian Wang, Duoli Li, Jianhui Bu, Chuanbin Zeng, Bo Li and Jiajun Luo
Micromachines 2023, 14(3), 602; https://doi.org/10.3390/mi14030602 - 4 Mar 2023
Viewed by 1718
Abstract
In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the [...] Read more.
In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO2 interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>(<b>a</b>) Layout of measured devices. (<b>b</b>) Cross-sectional view of measured devices along the dashed line (1) in (<b>a</b>). (<b>c</b>) Cross-sectional view of measured devices along the dashed line (2) in (<b>a</b>).</p> Full article ">Figure 2
<p>Illustration of the low-frequency noise measurement system.</p> Full article ">Figure 3
<p><span class="html-italic">I</span><sub>d</sub>–<span class="html-italic">V</span><sub>gs</sub> curves in the linear region (<span class="html-italic">V</span><sub>ds</sub> = 0.1 V) of (<b>a</b>) 1.8 V NMOSFETs for geometry: <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/0.18 μm and (<b>b</b>) 5 V NMOSFETs for geometry: <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/0.5 μm. All devices were irradiated up to 1 Mrad(Si) under the “on” bias condition.</p> Full article ">Figure 4
<p>Threshold-voltage shift ∆<span class="html-italic">V</span><sub>th</sub> as a function of irradiation dose for (<b>a</b>) 1.8 V NMOSFETs with geometries <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/10 μm, 10 μm/0.18 μm, and 1.8 μm/0.18 μm and (<b>b</b>) 5 V NMOSFETs with geometries <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/10 μm and 10 μm/0.5 μm. All devices were irradiated up to 1 Mrad(Si) under the “on” bias condition.</p> Full article ">Figure 5
<p>Net threshold-voltage shifts and components due to oxide-trap charge and interface-trap charge as a function of irradiation dose for the 5 V NMOSFETs (<b>a</b>) with a width of 10 μm and a length of 0.5 μm, as well as those (<b>b</b>) with a width of 10 μm and a length of 10 μm. All devices were irradiated up to 1 Mrad(Si) under the “on” bias condition.</p> Full article ">Figure 6
<p>Drain-current noise power density spectrum of 5 V NMOSFETs for geometries: (<b>a</b>) <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/10 μm and (<b>b</b>) <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/0.5 μm and 1.8 V NMOSFETs for geometries: (<b>c</b>) <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/10 μm, (<b>d</b>) <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/0.18 μm and (<b>e</b>) <span class="html-italic">W</span>/<span class="html-italic">L</span> = 1.8 μm/0.18 μm at different irradiation doses. All devices were irradiated up to 1 Mrad(Si) under the “on” bias condition. Noise measurements were carried out when <span class="html-italic">V</span><sub>gs</sub> − <span class="html-italic">V</span><sub>th</sub> = 0.3V and <span class="html-italic">V</span><sub>ds</sub> = 0.1V.</p> Full article ">Figure 7
<p>Drain-current noise magnitudes at <span class="html-italic">f</span> = 10 Hz as a function of radiation dose. (<b>a</b>) 1.8 V NMOSFETs for geometries: <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/10 μm, 10 μm/0.18 μm and 1.8 μm/0.18 μm, and (<b>b</b>) 5 V NMOSFETs for geometries: <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/10 μm and 10 μm/0.5 μm. All devices were irradiated up to 1 Mrad(Si) in the “on” bias condition. Noise measurements were carried out when <span class="html-italic">V</span><sub>gs</sub> − <span class="html-italic">V</span><sub>th</sub> = 0.3 V and <span class="html-italic">V</span><sub>ds</sub> = 0.1 V.</p> Full article ">Figure 8
<p>The physical processes of the origin of low-frequency noise in NMOSFETs under (<b>a</b>) pre-irradiation/lower-dose irradiation and (<b>b</b>) higher-dose irradiation in the energy band diagram.</p> Full article ">Figure 9
<p>Illustration of low-frequency noise generation in NMOSFETs (<b>a</b>) before/under lower-dose irradiation, (<b>b</b>) under higher-dose irradiation.</p> Full article ">Figure 10
<p>Noise magnitudes at <span class="html-italic">f</span> = 10 Hz of 5 V NMOSFETs for geometries: (<b>a</b>) <span class="html-italic">W</span>/<span class="html-italic">L</span> = 10 μm/0.5 μm and (<b>b</b>) 10 μm/10 μm as a function of irradiation dose which are measured and calculated under the modified physical mechanism.</p> Full article ">
14 pages, 1391 KiB  
Article
A Reliability System Evaluation Model of NoC Communication with Crosstalk Analysis from Backend to Frontend
by Xiaodong Weng, Xiaoling Lin, Yi Liu, Changqing Xu, Linjun Zhan, Shunyao Wang, Dongdong Chen and Yintang Yang
Micromachines 2023, 14(2), 469; https://doi.org/10.3390/mi14020469 - 17 Feb 2023
Cited by 1 | Viewed by 1942
Abstract
Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron [...] Read more.
Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>A coupling interconnect model: (<b>a</b>) is the equivalent capacitance model; (<b>b</b>) is the dimensions of an interconnect.</p> Full article ">Figure 2
<p>Distributed three-wire RLC spice model.</p> Full article ">Figure 3
<p>The flowchart of RSHARQ.</p> Full article ">Figure 4
<p>Real three-wire model realization with INNOVUS: (<b>a</b>) is the circuit diagram; (<b>b</b>) is the standard cell logic diagram; (<b>c</b>) is the layout graph.</p> Full article ">
11 pages, 3292 KiB  
Article
Analytical Separated Neuro-Space Mapping Modeling Method of Power Transistor
by Xu Wang, Tingpeng Li, Shuxia Yan and Jian Wang
Micromachines 2023, 14(2), 426; https://doi.org/10.3390/mi14020426 - 10 Feb 2023
Cited by 1 | Viewed by 1493
Abstract
An analytically separated neuro-space mapping (Neuro-SM) model of power transistors is proposed in this paper. Two separated mapping networks are introduced into the new model to improve the characteristics of the DC and AC, avoiding interference of the internal parameters in neural networks. [...] Read more.
An analytically separated neuro-space mapping (Neuro-SM) model of power transistors is proposed in this paper. Two separated mapping networks are introduced into the new model to improve the characteristics of the DC and AC, avoiding interference of the internal parameters in neural networks. Novel analytical formulations are derived to develop effective combinations between the mapping networks and the coarse model. In addition, an advanced training approach with simple sensitivity analysis expressions is proposed to accelerate the optimization process. The flexible transformation of terminal signals in the proposed model allows existing models to exceed their current capabilities, addressing accuracy limitations. The modeling experiment for the measurement data of laterally diffused metal-oxide-semiconductor transistors demonstrates that the novel method accurately represents the characteristics of the DC and AC of transistors with a simple structure and efficient training process. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Circuit-based structure of the separated model.</p> Full article ">Figure 2
<p>Schematic of the analytical DC model.</p> Full article ">Figure 3
<p>Schematic of the analytical AC model. (<b>a</b>) The input and output signals of the AC model. (<b>b</b>) The detailed process of the AC model.</p> Full article ">Figure 4
<p>Advanced training process of the separated model. (<b>a</b>) DC model training. (<b>b</b>) AC model training.</p> Full article ">Figure 5
<p>I–V comparison between the fine data and the models.</p> Full article ">Figure 6
<p>The parameters comparison between the models and the fine data. (<b>a</b>) Gain versus <span class="html-italic">P<sub>in</sub></span>. (<b>b</b>) <span class="html-italic">PAE</span> versus <span class="html-italic">P<sub>in</sub></span>.</p> Full article ">
10 pages, 3409 KiB  
Article
Linearity Enhancement Techniques for PGA Design
by Yujun Wang, Yi Wang, Lixi Wan and Zhi Jin
Micromachines 2023, 14(2), 356; https://doi.org/10.3390/mi14020356 - 31 Jan 2023
Viewed by 1893
Abstract
This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA’s linearity can be improved. The PGA’s [...] Read more.
This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA’s linearity can be improved. The PGA’s linearity is further improved with an additional capacitor, which is used for pre-charging the sampling capacitor to strengthen its capability to drive the sampling capacitor without any extra power consumption. The pre-charge technique is especially suitable for the case where the PGA drives a large sampling capacitance. Implemented in SMIC 0.18 um CMOS technology, the proposed PGA can achieve a gain of 0.5 or 1 and consumes 4.68 mW at a single 5 V supply with the switched output stage enabled. When driving a 20 pF sampling capacitor at a sampling frequency of 200 kHz, the simulation results show that the proposed PGA can give a 9 dBc improvement in SFDR of the sampled signal compared to the traditional PGA design and the SFDR can reach up to 114 dBc. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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<p>Block diagram of a typical analog front-end.</p> Full article ">Figure 2
<p>PGA architectures with (<b>a</b>) control switches at the output of the op-amp and (<b>b</b>) control switches at the input of the op-amp.</p> Full article ">Figure 3
<p>Typical block diagram of a data acquisition system.</p> Full article ">Figure 4
<p>Block diagram of (<b>a</b>) the proposed PGA and (<b>b</b>) SC-OPA.</p> Full article ">Figure 5
<p>(<b>a</b>) Block diagram of the pre-charge technique used in the PGA. (<b>b</b>) Timing diagram of the pre-charge technique.</p> Full article ">Figure 6
<p>(<b>a</b>) The proposed PGA design. (<b>b</b>) Schematic of the SC-OPA.</p> Full article ">Figure 7
<p>Layout of the proposed PGA.</p> Full article ">Figure 8
<p>(<b>a</b>) The closed-loop gain verse frequency. (<b>b</b>) The simulated SFDR versus input amplitude. (<b>c</b>) The simulated SFDR versus frequency.</p> Full article ">Figure 9
<p>The simulated THD versus (<b>a</b>) the output swing at 1 KHz and (<b>b</b>) the frequency when the output swing = 5 Vpk.</p> Full article ">
9 pages, 2779 KiB  
Article
Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC
by Yu-Jun Wang, Peng Wang, Li-Xi Wan and Zhi Jin
Micromachines 2023, 14(2), 300; https://doi.org/10.3390/mi14020300 - 23 Jan 2023
Viewed by 2236
Abstract
This brief proposes a signal-independent background calibration in pipeline-SAR analog-to-digital converters (ADCs) with a convergence-accelerated technique. To achieve signal independence, an auxiliary capacitor array CA is introduced to pre-inject a pseudo-random noise (PN) in the sampling phase to cancel out the opposite [...] Read more.
This brief proposes a signal-independent background calibration in pipeline-SAR analog-to-digital converters (ADCs) with a convergence-accelerated technique. To achieve signal independence, an auxiliary capacitor array CA is introduced to pre-inject a pseudo-random noise (PN) in the sampling phase to cancel out the opposite PN injection of the calibrated capacitor in the conversion phase, and CA is also used to realize the D/A function of the calibrated capacitor in the conversion phase. In this way, no matter what the signal is, the residue headroom remains unchanged even with PN injection. Moreover, the first sub-ADC is designed with extended conversion bits to quantize its own residue after delivering the conversion bits required by the first stage. Afterwards, this result is provided to the calibration algorithm to reduce the signal component and accelerate the convergence. Based on the simulation, the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) improve from 45.3 dB and 56.4 dB to 68.2 dB and 88.4 dB, respectively, after calibration. In addition, with the acceleration technique, convergence cycles decrease from 1.7 × 108 to 5.8 × 106. Moreover, no matter whether the input signal is DC, sine wave or band-limited white noise, the calibration all works normally. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits)
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Graphical abstract

Graphical abstract
Full article ">Figure 1
<p>(<b>a</b>) Block diagram, (<b>b</b>) timing diagram and (<b>c</b>) simplified signal flow diagram of the proposed pipeline-SAR ADC.</p> Full article ">Figure 2
<p>The connection configurations of the 1st stage CDAC when PN is injected into C<sub>M1</sub> (<b>a</b>) in sampling phase; (<b>b</b>) in residue generation phase.</p> Full article ">Figure 3
<p>Bit-weight learning curve.</p> Full article ">Figure 4
<p>Output spectra: (<b>a</b>) without calibration; (<b>b</b>) with calibration.</p> Full article ">Figure 5
<p>ADC dynamic performance learning curves: (<b>a</b>) without signal elimination; (<b>b</b>) with signal elimination.</p> Full article ">Figure 6
<p>MSB learning curve with DC, square and band-limited white noise inputs.</p> Full article ">Figure 7
<p>Histogram of output spectra’s SFDR with mismatch of 1% of sub-ADC 5 MSBs.</p> Full article ">Figure 8
<p>SFDR with different mismatch of sub-ADC 5 MSBs.</p> Full article ">
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