The necessity for higher computer efficiency is constantly increasing to successfully manage issues related, for example, to climate changes, extreme weather conditions, etc. High-Performance Computing (HPC) is a key technology to help deal with and overcome many of these obstacles, which will make computing better for citizens. It is more than obvious that with current data centres consuming ever more power, there is a critical need for improved energy-efficient solutions.
Back in October 2011, the Mont-Blanc consortium launched the first phase of a project aimed at exploring an energy-efficient alternative to current supercomputers, based on low-power mobile processors, with the ambition to set future HPC standards for the Exascale era.
The three key partners throughout the various Mont-Blanc projects have been Arm, Bull (Atos group), and the Barcelona Supercomputing Center (BSC). However, throughout the years, a lot of other European partners have been involved and have contributed to the development and successful realization of the project, thus bringing valuable expertise from research labs, academia, and industry.
Mont-Blanc has been realized throughout 4 phases, all of which had the objective to explore energy-efficient solutions for the era of Exascale computing. Before we continue, if you wish to deep dive and find out more about the top Mont-Blanc 2020 achievements, here is a useful review.
The Mont-Blanc 1 project had three core objectives. The first one was to elaborate an HPC model through purchasable, low-power technology. The second goal was to design a next-generation HPC system together with a range of embedded technologies to overcome the limitations identified in the prototype system. Lastly, the team had to develop a portfolio of exascale applications to be run on this new generation of HPC systems.
This solution would lead to the possibility of elaborating a computer architecture, which would be able to provide a high level of performance using less energy.
Since Mont-Blanc 1 began in 2011, its researchers had been studying computer architecture using the kind of Systems-on-Chips (SoCs) embedded in mobile phones and tablets. Having the ambition to set new HPC standards for the coming Exascale era, Mont-Blanc focused on transferring some of this technology to supercomputers. One of the Mont-Blanc project partners was the British company ARM, whose primary business has been the design of ARM processors.
The mobile device market has been largely dominated by SoC processors designed by ARM. Such low-power and commercially available technology was used for the first time in HPC systems during the realization of the Mont-Blanc project.
Thus, one of the major achievements of Mont-Blanc has been the deployment of a large ARM-based prototype based on over 1,000 mobile SoCs. This is a unique platform, where it is possible to test and study applications at scale and develop a fully functional system software stack for ARM-based supercomputers.
The Mont-Blanc 2 project had four objectives:
Mont-Blanc 2 contributed to the development of extreme-scale energy-efficient platforms, with potential for Exascale computing, addressing the challenges of massive parallelism, heterogeneous computing, and resiliency.
The team working behind Mont-Blanc 2 essentially focused on improved software. All the scientific libraries and runtime systems were converted to ARMv8 as part of the ecosystem that Mont-Blanc created. A complete development tools ecosystem was created for the likes of debugging, performance analysis, performance prediction, and automated kernel optimisation.
The system’s ability to continue operating despite failures was improved and new structures were investigated. Furthermore, the market has offered various opportunities for the platforms that would be acquired, and these opportunities were determined. Afterwards, the Mont-Blanc structure was made available to the scientific community. At the final stage, the models which were developed throughout the project were given to a group of industrial customers. The latter was an essential step towards future commercial exploitation.
It was very important to improve and upgrade the gained insights during the previous phases. The first of the three targets was to design a well-balanced architecture and to deliver the design for an ARM-based SoC or SoP (System on Package) capable of providing pre-exascale performance when implemented in the timeframe of 2019-2020. The predicted performance target had to be measured using real HPC applications.
Finally, Mont-Blanc 3 was also about developing the necessary software ecosystem for the future SoC. This additional objective was important to maximize the impact of the project and ensure that this ARM architecture path would be successful on the market.
Here are some of the major scientific and technological results of the project:
The impact of the third phase of Mont-Blanc has been widely recognized by the community. The project has won two prestigious HPCwire awards. It has also twice received the honour of the “Top 500 Hits and Misses Yearly Report.”
Besides, the project received two awards at the SC17: International Conference for High-Performance Computing, Networking, Storage and Analysis. It won the HPCwire Editors’ Choice award for “Best HPC Collaboration (Academia/Government/Industry)”. In addition, the technological implementation by Atos got the “Editors’ Choice: Top 5 New Products or Technologies to Watch” award.
Mont-Blanc 2020 was the last of the series of projects. It focused on processor design, setting as a target to activate and strengthen the European industrial capacity in processor design and enhance the skills necessary for chip design.
The major achievement of the Mont-Blanc 2020 has been the IP developed for a low-power Network on Chip (NoC). The NoC IP will be included in the next generation EPI processor, the European Processor for HPC.
If you are eager to learn more about the major achievements of Mont Blanc 2020, here is a summary:
The developing team eagerly promoted Mont-Blanc 2020 and its achievements by organising joint activities with other European Exascale projects. A lot of advertising initiatives were held through the project, including peer-reviewed publications, invited talks, booths at tradeshows, presentations at workshops, peer-reviewed posters, hackathons, tutorials, and a MOOC.
One of the strong points of the successive Mont-Blanc projects is the collaboration between industry and academia. The team of Mont Blanc 2020 encompasses 3 core partners (Arm, Atos, BSC), 3 SMEs (Kalray, Semidynamics, Sipearl) and prominent research partners (BSC, CEA, JSC). This is essential in ensuring that the technologies developed within the project are or will be introduced to the European and international systems and further projects.
Just to give you a brief outline, all Mont-Blanc 2020 partners have declared Exploitable Results. On top of that, all “commercial” Mont-Blanc 2020 partners have already integrated or will integrate some outcomes of the project in their products and offers. Further, all academic Mont-Blanc 2020 partners are already using or planning to use some of the project’s outcomes for further research endeavours.
The major MB2020 impact is that the project has provided the foundation to develop a family of European-grown processors, and, in particular, a processor that can power the future European Exascale supercomputers. MB2020 developed IP for a low-power Network on Chip (NoC). This IP will be included in the next generation of EPI processors.
The increased processing power and efficiency from the Mont-Blanc project can significantly enhance the speed and reliability of transaction processing systems used by online casinos, particularly benefiting fast withdrawal casinos. This improvement enables quicker withdrawals for players, thus boosting the overall user experience and potentially revolutionizing industries where speed and reliability are critical for customer satisfaction and operational efficiency.
To conclude, the project was crucial to reinforce the skills necessary for chip design. Therefore, the consortium made significant efforts to share and extend the knowledge, methodology and tools that allowed the researchers to test applications and evaluate future performance. The team developed a unique co-design methodology for SoC infrastructure verification and optimization.
That knowledge was shared by the consortium members through many workshops, tutorials and hackathons. Additionally, various features developed for the Simulation Framework are already used outside of the project.
