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A parallel branch-and-cut approach for detailed placement

Published: 07 April 2011 Publication History

Abstract

We introduce a technique that utilizes distributing computing resources for the efficient optimization of a traditional physical design problem. Specifically, we present a detailed placement strategy designed to exploit distributed computing environments, where the additional computing resources are employed in parallel to improve the optimization time. A Mixed Integer Programming (MIP) model and branch-and-cut optimization strategy are employed to solve the standard cell placement problem. By exploiting the problem structure, our algorithm improves upon the solutions afforded by existing optimization algorithms. First, an efficient batch-branching technique can eliminate several integer decision variables during each step of the optimization procedure. This batch-branching scheme can be performed serially or in parallel. In addition, custom cutting-planes are shown to significantly reduce the run time for optimizations as they efficiently refine the feasible region in order to quickly produce integer solutions. Our serial branch-and-cut strategies allow for significant reductions in wirelength, relative to the state-of-the-art commercial software package CPLEX, assuming a fixed allotment of time. Furthermore, we show that distributed computing resources can be used to significantly reduce the time required to achieve reductions in wirelength.

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  • (2022)Inducing Non-uniform FPGA Aging Using Configuration-based Short CircuitsACM Transactions on Reconfigurable Technology and Systems10.1145/351704215:4(1-33)Online publication date: 6-Jun-2022
  • (2022)Detailed Placement for Dedicated LUT-Level FPGA InterconnectACM Transactions on Reconfigurable Technology and Systems10.1145/350180215:4(1-33)Online publication date: 9-Dec-2022
  • (2022)A Framework for Identification and Validation of Affine Hybrid Automata from Input-Output TracesACM Transactions on Cyber-Physical Systems10.1145/34704556:2(1-24)Online publication date: 11-Apr-2022
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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 16, Issue 2
    March 2011
    180 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1929943
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 07 April 2011
    Accepted: 01 September 2010
    Revised: 01 May 2010
    Received: 01 December 2009
    Published in TODAES Volume 16, Issue 2

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    Author Tags

    1. MIP
    2. Parallel
    3. detailed placement

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    Cited By

    View all
    • (2022)Inducing Non-uniform FPGA Aging Using Configuration-based Short CircuitsACM Transactions on Reconfigurable Technology and Systems10.1145/351704215:4(1-33)Online publication date: 6-Jun-2022
    • (2022)Detailed Placement for Dedicated LUT-Level FPGA InterconnectACM Transactions on Reconfigurable Technology and Systems10.1145/350180215:4(1-33)Online publication date: 9-Dec-2022
    • (2022)A Framework for Identification and Validation of Affine Hybrid Automata from Input-Output TracesACM Transactions on Cyber-Physical Systems10.1145/34704556:2(1-24)Online publication date: 11-Apr-2022
    • (2020)Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00035(153-161)Online publication date: Aug-2020
    • (2020)Parallel computational optimization in operations research: A new integrative framework, literature review and research directionsEuropean Journal of Operational Research10.1016/j.ejor.2019.11.033287:1(1-18)Online publication date: Nov-2020
    • (2019)Optimal Batch Plants Design on Parallel Systems: A Comparative Study2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2019.00097(549-558)Online publication date: May-2019
    • (2017)Placement mitigation techniques for power grid electromigration2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2017.8009178(1-6)Online publication date: Jul-2017
    • (2015)Progress and Challenges in VLSI Placement ResearchProceedings of the IEEE10.1109/JPROC.2015.2478963103:11(1985-2003)Online publication date: Nov-2015
    • (2014)Density-aware Detailed Placement with Instant LegalizationProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593120(1-6)Online publication date: 1-Jun-2014
    • (2014)MIP-based detailed placer for mixed-size circuitsProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560526(11-18)Online publication date: 30-Mar-2014
    • Show More Cited By

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