research-article

Speculative DMA for architecturally visible storage in instruction set extensions

Authors:

Theo Kluter,

Philip Brisk,

Paolo Ienne,

Edoardo CharbonAuthors Info & Claims

CODES+ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis

Pages 243 - 248

https://doi.org/10.1145/1450135.1450191

Published: 19 October 2008 Publication History

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Abstract

Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expanded to include Architecturally Visible Storage (AVS) - compiler-controlled memories, similar to scratchpads, that are accessible only to ISEs. To achieve a speedup using AVS, Direct Memory Access (DMA) transfers are required to move data from the main memory to the AVS; unfortunately, this creates coherence problems between the AVS and the cache, which previous methods for ISEs with AVS failed to address; additionally, these methods need to leave many conservative DMA transfers in place, whose execution significantly limits the achievable speedup. This paper presents a memory coherence scheme for ISEs with AVS, which can ensure execution correctness and memory consistency with minimal area overhead. We also present a method that speculatively removes redundant DMA transfers. Cycle-accurate experimental results were obtained using an FPGA-emulation platform. These results show that the application-specific instruction-set extended processors with speculative DMA-enhanced AVS gain significantly over previous techniques, despite the overhead of the coherence mechanism.

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Prakash AClarke CLam SSrikanthan T(2018)Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276912526:3(445-456)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2769125
Dehyadegari MMarongiu AKakoee MMohammadi SYazdani NBenini L(2015)Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW AcceleratorsIEEE Transactions on Computers10.1109/TC.2014.236052264:8(2132-2144)Online publication date: 1-Aug-2015
https://doi.org/10.1109/TC.2014.2360522
Kluter TBurri SBrisk PCharbon EIenne P(2014)Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible StorageACM Transactions on Architecture and Code Optimization10.1145/257687711:2(1-26)Online publication date: 15-Jul-2014
https://dl.acm.org/doi/10.1145/2576877
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Information & Contributors

Information

Published In

CODES+ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis

October 2008

288 pages

ISBN:9781605584706

DOI:10.1145/1450135

Program Chairs:
Catherine Gebotys
University of Waterloo, Canada
,
Grant Martin
Tensilica, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 October 2008

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ESWEEK 08

Sponsor:

ESWEEK 08: Fourth Embedded Systems Week

October 19 - 24, 2008

GA, Atlanta, USA

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CODES+ISSS '08 Paper Acceptance Rate 44 of 143 submissions, 31%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Prakash AClarke CLam SSrikanthan T(2018)Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276912526:3(445-456)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2769125
Dehyadegari MMarongiu AKakoee MMohammadi SYazdani NBenini L(2015)Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW AcceleratorsIEEE Transactions on Computers10.1109/TC.2014.236052264:8(2132-2144)Online publication date: 1-Aug-2015
https://doi.org/10.1109/TC.2014.2360522
Kluter TBurri SBrisk PCharbon EIenne P(2014)Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible StorageACM Transactions on Architecture and Code Optimization10.1145/257687711:2(1-26)Online publication date: 15-Jul-2014
https://dl.acm.org/doi/10.1145/2576877
Kluter TBrisk PCharbon EIenne P(2014)Way StealingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223668922:1(62-75)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1109/TVLSI.2012.2236689
Ding HHuang M(2014)Improve memory access for achieving both performance and energy efficiencies on heterogeneous systems2014 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2014.7082759(91-98)Online publication date: Dec-2014
https://doi.org/10.1109/FPT.2014.7082759
Burgio PMarongiu ACoussy PBenini L(2014)A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared MemoryProceedings of the 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2014.27(130-137)Online publication date: 26-Aug-2014
https://dl.acm.org/doi/10.1109/EUC.2014.27
Ross VLeeser M(2013)GPGPU Computing for Cloud AuditingHigh Performance Cloud Auditing and Applications10.1007/978-1-4614-3296-8_10(259-282)Online publication date: 1-Aug-2013
https://doi.org/10.1007/978-1-4614-3296-8_10
Guan XFei YLin H(2012)Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT ProcessingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.210551220:3(551-563)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2105512
Favi CKluter TMester CCharbon E(2012)Optically-Clocked Instruction Set Extensions for High Efficiency Embedded ProcessorsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2011.216973059:3(604-615)Online publication date: Mar-2012
https://doi.org/10.1109/TCSI.2011.2169730
Brisk P(2011)Architecture and design automation for application-specific processors2011 9th IEEE International Conference on ASIC10.1109/ASICON.2011.6157399(1094-1097)Online publication date: Oct-2011
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