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Fast synchronization for chip multiprocessors

Authors:

Jack Sampson,

Rubén González,

Jean-Francois Collard,

Norman P. Jouppi,

Mike SchlanskerAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 33, Issue 4

Pages 64 - 69

https://doi.org/10.1145/1105734.1105743

Published: 01 November 2005 Publication History

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Abstract

This paper presents a novel mechanism for barrier synchronization on chip multi-processors (CMPs). By forcing the invalidation of selected I-cache lines, this mechanism starves threads and thus forces their execution to stop. Threads are let free when all have entered the barrier.We evaluated this mechanism using SMTSim and report much better (and most importantly, more flat) performance than lock-based barriers supported by existing microprocessors.

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Maroun EHansen HKristensen ASchoeberl M(2019)Time-predictable synchronization support with a shared scratchpad memoryMicroprocessors and Microsystems10.1016/j.micpro.2018.09.01464(34-42)Online publication date: Feb-2019
https://doi.org/10.1016/j.micpro.2018.09.014
Wei ZLiu PZeng ZXu JYing R(2014)Instruction-based high-efficient synchronization in a many-core Network-on-Chip processor2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865604(2193-2196)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865604
Savadi ADeldari H(2014)Measurement of the latency parameters of the Multi-BSP modelThe Journal of Supercomputing10.1007/s11227-013-1018-467:2(565-584)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1007/s11227-013-1018-4
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Fast synchronization for chip multiprocessors

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 33, Issue 4

Special issue: dasCMP'05

November 2005

130 pages

ISSN:0163-5964

DOI:10.1145/1105734

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Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 November 2005

Published in SIGARCH Volume 33, Issue 4

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Maroun EHansen HKristensen ASchoeberl M(2019)Time-predictable synchronization support with a shared scratchpad memoryMicroprocessors and Microsystems10.1016/j.micpro.2018.09.01464(34-42)Online publication date: Feb-2019
https://doi.org/10.1016/j.micpro.2018.09.014
Wei ZLiu PZeng ZXu JYing R(2014)Instruction-based high-efficient synchronization in a many-core Network-on-Chip processor2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865604(2193-2196)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865604
Savadi ADeldari H(2014)Measurement of the latency parameters of the Multi-BSP modelThe Journal of Supercomputing10.1007/s11227-013-1018-467:2(565-584)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1007/s11227-013-1018-4
Chen XChen S(2011)DSBSProceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2011.141(1030-1037)Online publication date: 16-Nov-2011
https://dl.acm.org/doi/10.1109/TrustCom.2011.141
Stoif CSchoeberl MLiccardi BHaase J(2011)Hardware synchronization for embedded multi-core processors2011 IEEE International Symposium of Circuits and Systems (ISCAS)10.1109/ISCAS.2011.5938126(2557-2560)Online publication date: May-2011
https://doi.org/10.1109/ISCAS.2011.5938126
Valiant L(2011)A bridging model for multi-core computingJournal of Computer and System Sciences10.1016/j.jcss.2010.06.01277:1(154-166)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1016/j.jcss.2010.06.012
Chen XLu ZJantsch AChen S(2010)Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory23rd IEEE International SOC Conference10.1109/SOCC.2010.5784680(467-472)Online publication date: Sep-2010
https://doi.org/10.1109/SOCC.2010.5784680
Chen XLu ZJantsch AChen SLu JWu H(2010)Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation TechniqueProceedings of the 2010 IEEE Annual Symposium on VLSI10.1109/ISVLSI.2010.16(462-463)Online publication date: 5-Jul-2010
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Marongiu ABenini LKandemir MKim TSainrat PLumetta SNavarro N(2007)Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platformsProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289908(145-149)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289881.1289908

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