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Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression

Published: 16 February 2004 Publication History

Abstract

This paper presents a new test data compression technique based on a compression code that uses exactly nine code-words. In spite of its simplicity, it provides significant reduction intest data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bitsunchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single- or multiple-scan chain designs to reduce test application time and pin requirement. Experimentalresults for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

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Cited By

View all
  • (2008)GECOMProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356943(577-582)Online publication date: 21-Jan-2008
  • (2007)A selective pattern-compression scheme for power and test-data reductionProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326180(520-525)Online publication date: 5-Nov-2007
  • (2007)Functional Constraints vs. Test Compression in Scan-Based Delay TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-007-5013-723:5(445-455)Online publication date: 1-Oct-2007
  • Show More Cited By

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  1. Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression

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          cover image ACM Conferences
          DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2
          February 2004
          606 pages
          ISBN:0769520855

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          Published: 16 February 2004

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          View all
          • (2008)GECOMProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356943(577-582)Online publication date: 21-Jan-2008
          • (2007)A selective pattern-compression scheme for power and test-data reductionProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326180(520-525)Online publication date: 5-Nov-2007
          • (2007)Functional Constraints vs. Test Compression in Scan-Based Delay TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-007-5013-723:5(445-455)Online publication date: 1-Oct-2007
          • (2006)Functional constraints vs. test compression in scan-based delay testingProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131769(1039-1044)Online publication date: 6-Mar-2006
          • (2006)FCSCANProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118454(653-658)Online publication date: 24-Jan-2006
          • (2005)Using MUXs Network to Hide Bunches of Scan ChainsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.127(238-243)Online publication date: 21-Mar-2005
          • (2005)Evolutionary Optimization in Code-Based Test CompressionProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.144(1124-1129)Online publication date: 7-Mar-2005
          • (2004)Design space exploration for aggressive test cost reduction in CircularScan architecturesProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382671(726-731)Online publication date: 7-Nov-2004

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