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Correct interactive transformational synthesis of DSP hardware

Published: 25 February 1991 Publication History

Abstract

We present a new interactive tool for the guided synthesis of digital signal processing hardware. The tool is driven from a HDL. It will suggest different ways of implementing different architectures for the same specification, maintaining the correctness of implementations during the design process. The tool will automatically generate input for the Boyer Moore theorem prover from the HDL specification in order to verify the correctness of the implementations.

References

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{Bo88} Boyer, R. S., Moore, J. S. A Computational Logic Handbook. Academic Press, 1988.
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{Br88} Brayton, R. K., Camposano, R., DeMicheli, G., Otten, R. H, vanEijndhoven, J. The Yorktown Silicon Compiler. In: "Silicon Compilation", Gajski, (Ed), Addison Wesley, 1988.
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{Ca84} Campbell, R. H., Koelmans, A. M., McLauchlan, M. R. STRICT: a design language for strongly typed recursive integrated circuits. IEE Proc. Vol 132, Pts E and I, No 2, 1985.
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{Ca88} Camposano, R. Behavior-preserving transformations for High Level Synthesis, Lecture Notes in Computer Science 408, Springer Verlag, pp. 106--128.
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{De86} DeMan, H., Rabaey, J., Six, P., Claesen, L. Cathedral II: A Silicon Compiler for Digital Signal Processing. IEEE Design and Test, Vol 3, No 6, Dec. 1986.
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{De89} Denyer, B. P. SAGE, A Methodology and Toolset for Architectural Synthesis. Technical Report, Department of Electrical Engineering, Edinburgh University, 1989.
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{E189} Elmasry, M. I., Buset, O. A. ACE, A Hierarchical Graphical Interface for Architectural Synthesis. Proc. 26th ACM/IEEE Design Aut. Conf., 1989.
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{Fi89} Finn, M., Fourman, M. P., Francis, M., Harris, R. Formal System Design-Interactive synthesis based on Computer-Assisted Formal Reasoning. Proc. IFIP workshop "Applied Formal Methods for Correct VLSI Design", Belgium, 1989.
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{Hu85} Hunt, W. FM8501: A Verified Microprocessor. PhD Thesis, University of Texas at Austin, 1985.
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{IE87} IEEE Standard VHDL Language Reference Manual, IEEE Press, 1987.
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{Ka88}. Kalker, T. HOL Semantics for DSP, Philips Research Labs Technical Report, Eindhoven, The Netherlands, 1988.
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{Mc88} McFarland, S. J., Parker, A. C., Camposano, R. Tutorial on High Level Synthesis. Proc. 25th ACM/IEEE Design Aut. Conf., IEEE, 1988.
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{Pi89a} Pierre, L. The formal proof of the "min-max" sequential benchmark described in CASCADE using the Boyer--Moore theorem prover. Proc. IFIP workshop "Applied Formal Methods for Correct VLSI Design", Belgium, 1989.
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{Pi89b} Pierre, L. The formal proof of sequential circuits described in CASCADE using the Boyer-Moore Theorem Prover. Proc. IFIP workshop "Applied Formal Methods for Correct VLSI Design", Belgium, 1989.
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{Ve88} Verkest, D., Johannes, P., Claesen, L., DeMan, H. Formal Techniques for Proving Correctness of Parameterized Hardware using Correctness Preserving Transformations. In Proc. IFIP workshop "The Fusion of Hardware Design and Verification". North Holland, 1988.

Cited By

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  • (1994)Formal verification of behavioral VHDL specificationsProceedings of the conference on European design automation10.5555/198174.198328(560-565)Online publication date: 23-Sep-1994

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Published In

cover image ACM Conferences
EURO-DAC '91: Proceedings of the conference on European design automation
February 1991
577 pages
ISBN:0818621303
  • Conference Chair:
  • Tony Ambler,
  • General Chair:
  • Jochen Jess,
  • Program Chair:
  • Hugo De Man

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 25 February 1991

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  • (1994)Formal verification of behavioral VHDL specificationsProceedings of the conference on European design automation10.5555/198174.198328(560-565)Online publication date: 23-Sep-1994

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