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A systolic design rule checker

Authors:

Rajiv Kane,

Sartaj SahniAuthors Info & Claims

DAC '84: Proceedings of the 21st Design Automation Conference

Pages 243 - 250

Published: 25 June 1984 Publication History

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Abstract

We develop a systolic design rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design rule check phase of chip design.

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Rajiv Kane, and Sartaj Sahni, "ASystolic Design Rule Checker", TR 83-13, Department of Computer Science, University of Minnesota

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Cited By

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Luo ZMartonosi MAshar P(1999)An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule CheckingProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795846Online publication date: 21-Apr-1999
https://dl.acm.org/doi/10.5555/795658.795846
Won YSahni SEl-Zig Y(1990)A Hardware Accelerator for Maze RoutingIEEE Transactions on Computers10.1109/12.4629139:1(141-145)Online publication date: 1-Jan-1990
https://dl.acm.org/doi/10.1109/12.46291
Won YSahni SEl-ziq Y(1987)A hardware accelerator for maze routingProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.38014(800-806)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.38014
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Index Terms

A systolic design rule checker
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

DAC '84: Proceedings of the 21st Design Automation Conference

June 1984

715 pages

ISBN:0818605421

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IEEE Press

Publication History

Published: 25 June 1984

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DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Luo ZMartonosi MAshar P(1999)An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule CheckingProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795846Online publication date: 21-Apr-1999
https://dl.acm.org/doi/10.5555/795658.795846
Won YSahni SEl-Zig Y(1990)A Hardware Accelerator for Maze RoutingIEEE Transactions on Computers10.1109/12.4629139:1(141-145)Online publication date: 1-Jan-1990
https://dl.acm.org/doi/10.1109/12.46291
Won YSahni SEl-ziq Y(1987)A hardware accelerator for maze routingProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.38014(800-806)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.38014
Spira PHage COfek HO'Neill L(1985)Hardware acceleration of gate array layoutProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317913(359-366)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317913

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A Systolic Design-Rule Checker

Linear systolic array design for wafer scale integration

Design of a Multiple-Valued Systolic System for the Computation of the Chrestenson Spectrum