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On the relation between wire length distributions and placement of logic on master slice ICs

Published: 25 June 1984 Publication History

Abstract

The quality of placement and routing on gate arrays is commonly measured by average wire length. With regard to wire length, placement and routing are mutually competing tasks and the solution space for both is exponential. Estimates of measures of placement such as average wire length or, total wiring tracks prior to routing give some indication of the routability of the placement and, can be used to select another placement and repeat.
The nature of these problems necessitates a probabilistic approach to the wirability analysis of integrated circuits. Stochastic models for wiring space estimation and the relation between wire length distribution and placement optimization have received attention recently [1], [6], [2], [5], [7], [3] and [4]. Much of the reported work on wire length distributions and placement of logic rests on empirical evidence that indicates that “well placed” chips exhibit Rent's Rule between the number of components and the number of corresponding external connections. Rent's Rule has been the basis of the heuristic arguments used to derive upper bounds on the average wire length and the form of the wire length distribution. Rent's Rule has the form
T = KC p (1)
where T is the average number of external connections, C is the average number of components, K is number of connections per component and p is a positive constant. In [1], [2] and [4] the effect of placement on wire length distribution was introduced by assuming that a hierarchical partitioning scheme aimed at minimizing the average wire length results in a configuration that exhibits Rent's Rule. In [2] an upper bound r-k for the average wire length between elements of different subsets of components of size k was derived, and using Rent's Rule to obtain the number of connections between such subsets, an upper bound on the average wire length was derived. In [3] the Pareto distribution is proposed for the distribution of wire lengths. Similar results were presented in [4].
In this paper we present a model that provides a mathematical basis for Rent's Rule and its relation to wire length distribution. It will be shown that Rent's Rule, an observed fact, is a manifestation of a more fundamental underlying process characterized by a function which leads directly to a general class of wire length distributions, the Weibull family. That is, Rent's Rule contains all the information about the distribution of wire lengths. Thus, estimates for the average wire length can be derived. Theory presented here is substantiated by simulation results and earlier research data.

References

[1]
W. E. Donath, and W. F. Mikhail. Some Results from a Probabilistic Wiring Model. Technical Report TR 22.1556, IBM System East Fishkill Facility, IBM East Fishkill Facility, Hopewell Junction, N.Y. 12533, Nov, 1972.]]
[2]
Wilm E. Donath. Placement and Average Interconnection Lengths of Computer Logic. IEEE Transactions on Circuits and Systems CAS-26(4):272-277, Apr, 1979.]]
[3]
W. E. Donath. Wire Length Distribution for Placements of Computer Logic. IBM Journal of Research and Developement 25(3):152-155, May, 1981.]]
[4]
Michael Feuer. Connectivity of Random Logic. IEEE Transactions on Computers C-31(1):29-33, Jan, 1982.]]
[5]
Abbas A. EL Gamal. Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits. IEEE Transactions on Circuits and Systems CAS-28(2):127-138, Feb, 1981.]]
[6]
W. Heller, W. Mikhail, and W. Donath. Prediction of Wire Space Requirements for LSI. Design Automation and Fault-Tolerant Computing: 117-144, 1978.]]
[7]
Zahir Ali Syed. On Routing for Custom Integrated Circuits. PhD thesis, University of Southern California, 1981.]]

Cited By

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  • (2005)Intrinsic shortest path lengthProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129627(173-180)Online publication date: 31-May-2005
  • (1992)Combined topological and functionality based delay estimation using a layout-driven approach for high level applicationsProceedings of the conference on European design automation10.5555/159754.159771(72-78)Online publication date: 1-Nov-1992
  • (1989)An investigation into statistical properties of partitioning and floorplanning problemsProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74446(382-387)Online publication date: 1-Jun-1989

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        cover image ACM Conferences
        DAC '84: Proceedings of the 21st Design Automation Conference
        June 1984
        715 pages

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        IEEE Press

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        Published: 25 June 1984

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        DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;
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        View all
        • (2005)Intrinsic shortest path lengthProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129627(173-180)Online publication date: 31-May-2005
        • (1992)Combined topological and functionality based delay estimation using a layout-driven approach for high level applicationsProceedings of the conference on European design automation10.5555/159754.159771(72-78)Online publication date: 1-Nov-1992
        • (1989)An investigation into statistical properties of partitioning and floorplanning problemsProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74446(382-387)Online publication date: 1-Jun-1989

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