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Testing for bridging faults (shorts) in CMOS circuits

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John M. AckenAuthors Info & Claims

DAC '83: Proceedings of the 20th Design Automation Conference

Pages 717 - 718

Published: 27 June 1983 Publication History

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Abstract

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

References

[1]

McCluskey, E. J., "Verification Testing," Nineteenth Design Automation Conference Proceedings, pp 495-500, June 1982.

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Google Scholar

[2]

Armstrong, D. B., "On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets," IEEE Trans. on Electronic Computers, Vol. ECI5, pp 66-73, February 1966.

Google Scholar

[3]

Verna, J. P., Selove, D. M., and Tessier, J. N., "Automatic Test Generation and Test-Verification of Digital Systems" Eleventh Design Automation Workshop Proceedings, pp 149-158, 1974.

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Google Scholar

[4]

Friedman, A., and Menon, P., (F. Kup, Editor), Fault Detection in Digital Circuits, Prentice Hall, 1971.

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Rao LBushnell MAgrawal V(2007)Graphical IDDQ signatures reduce defect level and yield lossIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90412815:11(1245-1255)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.904128
Stopjaková VMalošek PMičušík DMatej MMargala M(2004)Classification of Defective Analog Integrated Circuits Using Artificial Neural NetworksJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000009311.63472.d620:1(25-37)Online publication date: 1-Feb-2004
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Renovell MAzaïs FBertrand Y(2002)Improving Defect Detection in Static-Voltage TestingIEEE Design & Test10.1109/MDT.2002.104774719:6(83-89)Online publication date: 1-Nov-2002
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Testing for bridging faults (shorts) in CMOS circuits
1. Hardware

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Published In

DAC '83: Proceedings of the 20th Design Automation Conference

June 1983

700 pages

ISBN:0818600268

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IEEE Press

Publication History

Published: 27 June 1983

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Rao LBushnell MAgrawal V(2007)Graphical IDDQ signatures reduce defect level and yield lossIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90412815:11(1245-1255)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.904128
Stopjaková VMalošek PMičušík DMatej MMargala M(2004)Classification of Defective Analog Integrated Circuits Using Artificial Neural NetworksJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000009311.63472.d620:1(25-37)Online publication date: 1-Feb-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000009311.63472.d6
Renovell MAzaïs FBertrand Y(2002)Improving Defect Detection in Static-Voltage TestingIEEE Design & Test10.1109/MDT.2002.104774719:6(83-89)Online publication date: 1-Nov-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1047747
(2001)Revisiting the Classical Fault Models through a Detailed Analysis of Realistic DefectsProceedings of the 2nd International Symposium on Quality Electronic Design10.5555/558593.850112Online publication date: 26-Mar-2001
https://dl.acm.org/doi/10.5555/558593.850112
Margala MDragic SEl-Abasiry AEkpe SStopjaková V(2000)I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog TestProceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)10.5555/850960.854316Online publication date: 3-Jul-2000
https://dl.acm.org/doi/10.5555/850960.854316
Ma SShaik IFetherston R(1999)A Comparison of Bridging Fault Simulation MethodsProceedings of the 1999 IEEE International Test Conference10.5555/518925.939320Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939320
Renovell MAzaïs FBertrand Y(1999)Detection of Defects Using Fault Model Oriented Test SequencesJournal of Electronic Testing: Theory and Applications10.1023/A:100833691967114:1-2(13-22)Online publication date: 1-Feb-1999
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Sidiropulos MStopjakova´ VManhaeve HMusil V(1999)An Analog Self-Test Based on Differential I _{\tf="P6965" DD} Monitoring Supported by Differential I_{\tf="P6965"OUT} CheckingAnalog Integrated Circuits and Signal Processing10.1023/A:100832371001521:1(33-44)Online publication date: 1-Oct-1999
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Chess BLarrabee T(1998)Logic Testing of Bridging Faults in CMOS Integrated CircuitsIEEE Transactions on Computers10.1109/12.66017047:3(338-345)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1109/12.660170
Nigh PForlenza DMotika F(1997)APPLICATION AND ANALYSIS OF IDDQ DIAGNOSTIC SOFTWAREProceedings of the 1997 IEEE International Test Conference10.5555/844384.845768Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.5555/844384.845768
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Logic Testing of Bridging Faults in CMOS Integrated Circuits

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