Accurate Area and Delay Estimators for FPGAs

We present an area and delay estimator in the context of a compilerthat takes in high level signal and image processing applicationsdescribed in MATLAB and performs automatic design spaceexploration to synthesize hardware for a Field Programmable GateArray (FPGA) which meets the user area and frequency specifications.We present an area estimator which is used to estimatethe maximum number of Configurable Logic Blocks (CLBs) consumedby the hardware synthesized for the Xilinx XC4010 fromthe input MATLAB algorithm. We also present a delay estimatorwhich finds out the delay in the logic elements in the criticalpath and the delay in the interconnects. The total number of CLBspredicted by us is within 16% of the actual CLB consumption andthe synthesized frequency estimated by us is within an error of13% of the actual frequency after synthesis through Synplify logicsynthesis tools and after placement and routing through the XACTtools from Xilinx. Since the estimators proposed by us are fastand accurate enough, they can be used in a high level synthesisframework like ours to perform rapid design space exploration.