Partial scan selection for user-specified fault coverage
Pages 111 - 116
References
[1]
S.T. Chakradhar and S. Dey. Resynthesis and Retiming for Optimum Partial Scan. In ACM/IEEE 31st Design Automation Conference, pages 87 - 93, June 1994.
[2]
Y. Higami, S. Kajihara, and K. Kinoshita. A Partial Scan Algorithm Based on Reduced Scan Shift. In Third Asian Test Symposium, pages 277-282, Nov 1994.
[3]
S. Day, M. Potkonjak, and R. Roy. Exploiting Hardware- Sharing in High Level Synthesis for Partial Scan Optimization. In IEEE International Conference on Computer-Aided Design, pages 20 - 25, November 1993.
[4]
H. Gundlach, B. Koch, and K. Muller-Glaser. On the Selection of a Partial Scan Path with Respect to Target Faults. In European Design Automation Conference, 1991.
[5]
V. Chickermane and J. Patel. A Fault Oriented Partial Scan Design Approach. In IEEE International Conference on Computer-Aided Design, November 1991.
[6]
D. Lee. and S. Reddy. On Determining Scan Flip-Flops in Partial Scan Designs. In IEEE International Conference on Computer-Aided Design, pages 322-325, November 1990.
[7]
V. Chickermane and J. Patel. An Optimization Based Approach to the Partial Scan Problem. In International Test Conference, IEEE, pages 377-387, September 1990.
[8]
K.T. Cheng and V.D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, 39(4):544-548, April 1990.
[9]
Rajesh Gupta, Rajiv Gupta and Melvin Breuer. An Efficient Implementation of the BALLAST Partial Scan Architecture. IEEE Transactions on Computers, 39(4):538-544, April 1990.
[10]
A. Kunzmann and H. Wunderlich. An Analytical Approach to the Partial Scan Problem. Journal of Electronic Testing: Theory and Application, 1(2):163-174, 1990.
[11]
A. Motohara, T. Ohta, and M. Akino. Critical Flip-Flop Identification Algotithms for Partial Scan Design. In IFIP Workshop on Design ~ Test of ASICs, pages 75-78, 1990.
[12]
V. Agrawal, K.-T. Chang, D. Johnson, and T. Lin. Designing Circuits with Partial Scan. IEEE Design ~ Test of Computers, 5:8-15, April 1988.
[13]
S. Bhawmik, K.-T. Cheng, C. Lin, and V. Agrawal. PASCANT: A Partial Scan and Test Generation System. In IEEE Custom Integrated Circuits Conference, pages 17.3.1-17.3.4, 1991.
[14]
D. Pellkofer. Fast Fault Simulation in Digital Circuits. PhD thesis, Dept. of Electrical Engineering, Technical University of Munich, April 1992.
[15]
K. Kozminski, (Ed.). OASIS2.0 User's Guide. MCNC, Research Triangle Park, N.C. 27709, 1992.
[16]
J. Calhoun and F. Brglez. A Framework and Method for Hierarchical Test Generation. IEEE Transactions on Computer- Aided Design, 11(1):45-67, January 1992.
[17]
C.-J. Lin, Y. Zorian, and S. Bhawmik. PSBIST: A Partial- Scan Based Built-in Self-Test Scheme. In International Test Conference, IEEE, pages 507-516, October 1993.
[18]
M. Abramovici, J. Kulikowski, and R. Roy. The Best Flip- Flops To Scan. In International Test Conference, IEEE, pages 166-173, October 1991.
[19]
T. Chakraborty, V. Agrawal, and M. Bushnell. Design for Testability for Path Delay Faults in Sequential Circuits. In 30th Design Automation Conference, A CM//IEEE, pages 453- 457, June 1993.
[20]
K.-T. Cheng. Partial Scan Designs Without a Separate Scan Clock. In VLSI Test Symposium, pages 277-282, April 1995.
[21]
K. Kim and C. Kime. Partial Scan Using Reverse Direction EmpiricalTestability. In International Test Conference, IEEE, pages 498-506, October 1993.
[22]
C. Gloster. ISCAS'89 Addendum Benchmark Set. ACM/SIGDA Benchmarks Electronic Newsletter, F. Brglez (Ed.), June 1993. Available via ftp at ftp.cbl.ncsu.edu or www at http://www.cbl.ncsu.edu/www/; for autoreply e-mail to [email protected].
[23]
T. Niermann and J. Patel. HITEC: A Test Generation Package for Sequential Circuits. In European Design Automation Conference, 1991.
[24]
C. Papadimitriou and K. Steiglitz. Combinatorial Optimization. Prentice Hall, Englewood, New Jersey, 1982.
[25]
M. Abramovici, P. Parikh, B. Mathew, and D Saab. On Selecting Flip-Flops for Partial Reset. In IEEE International Test Conference, pages 1008- 1012, September 1993.
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