Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection

With increasing design complexity, post-silicon validation has become a critical problem. In pre-silicon validation, coverage is the primary metric of validation effectiveness, but in post-silicon, the lack of observability makes coverage measurement problematic. On-chip coverage monitors are a possible solution, but prior research has shown that the overhead is prohibitive for anything beyond a small number of coverage points. This paper presents a novel solution for post-silicon coverage monitoring: fully instrument the design in emulation to sample the relationships between coverage points, and then use this statistical data to choose a small set of coverage points whose coverage provides high probability that all the other coverage points are covered as well; only that small set is instrumented on silicon. To demonstrate the method, we propose a simple feature selection algorithm based on Bayesian networks to choose the small set of coverage points. In experiments emulating a non-trivial SoC, our technique reduces the number of coverage monitors by 92%, yet predicts over 98% probability that all coverage points are covered.