research-article

System level synthesis of hardware for DSP applications using pre-characterized function implementations

Authors:

Nasim Farahini,

Kathrin Rosvall,

Ingo SanderAuthors Info & Claims

CODES+ISSS '13: Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Article No.: 16, Pages 1 - 10

Published: 29 September 2013 Publication History

Abstract

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FIMPs). It explores the design space in three dimensions, number of FIMPs, type of FIMPs and pipeline parallelism between the producing and consuming FIMPs. We introduce timing and interface model of FIMPs to enable reuse and automatic generation of Global Inter-connect and Control (GLIC) to glue the FIMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.

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Cited By

Yang YStathis DSharma PPaul KHemani AGrabherr MAhmad RMudge TPnevmatikatos D(2018)RiBoSOMProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229650(105-114)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1145/3229631.3229650
Lee HMoghaddam MSuh DEgger B(2018)Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/DecompressionACM Transactions on Architecture and Code Optimization10.1145/316201815:1(1-26)Online publication date: 22-Mar-2018
https://dl.acm.org/doi/10.1145/3162018
Hemani AJafri SMasoumian S(2017)Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs AffordableProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3132339(1-10)Online publication date: 19-Oct-2017
https://dl.acm.org/doi/10.1145/3130218.3132339
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Information

Published In

cover image ACM Conferences

CODES+ISSS '13: Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 2013

335 pages

ISBN:9781479914173

Program Chairs:
Radu Marculescu
Carnegie Mellon University
,
Preeti Ranjan Panda
IIT Delhi

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IEEE Press

Publication History

Published: 29 September 2013

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ESWEEK'13

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ESWEEK'13: Ninth Embedded System Week

September 29 - October 4, 2013

Quebec, Montreal, Canada

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CODES+ISSS '13 Paper Acceptance Rate 31 of 111 submissions, 28%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Yang YStathis DSharma PPaul KHemani AGrabherr MAhmad RMudge TPnevmatikatos D(2018)RiBoSOMProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229650(105-114)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1145/3229631.3229650
Lee HMoghaddam MSuh DEgger B(2018)Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/DecompressionACM Transactions on Architecture and Code Optimization10.1145/316201815:1(1-26)Online publication date: 22-Mar-2018
https://dl.acm.org/doi/10.1145/3162018
Hemani AJafri SMasoumian S(2017)Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs AffordableProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3132339(1-10)Online publication date: 19-Oct-2017
https://dl.acm.org/doi/10.1145/3130218.3132339
Pilato CMantovani PDi Guglielmo GCarloni L(2017)System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261150636:3(435-448)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2611506
Corre YDiguet JHeller DBlouin DLagadec L(2016)TBESACM Transactions on Embedded Computing Systems10.1145/281681715:1(1-27)Online publication date: 13-Jan-2016
https://dl.acm.org/doi/10.1145/2816817
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2656075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656075.2656098
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2565075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2565075.2656098

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