Robust test generation for power supply noise induced path delay faults
Authors: 
Xiang Fu, Huawei Li, 
Yu Hu, 
Xiaowei LiAuthors Info & Claims
Pages 659 - 662
Abstract
In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.
References
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Index Terms
- Robust test generation for power supply noise induced path delay faults
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Information
Published In
January 2008
812 pages
ISBN:9781424419227
- General Chair:
- Chong-Min Kyung,
- Program Chairs:
- Kiyoung Choi,
- Soonhoi Ha
Sponsors
- IEEE Circuits and Systems Society
- SIGDA: ACM Special Interest Group on Design Automation
- IEEK: The Institute of Electronics Engineers of Korea
Publisher
IEEE Computer Society Press
Washington, DC, United States
Publication History
Published: 21 January 2008
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- Research-article
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ASPDAC '08
Sponsor:
- SIGDA
- IEEK
Acceptance Rates
ASP-DAC '08 Paper Acceptance Rate 122 of 350 submissions, 35%;
Overall Acceptance Rate 466 of 1,454 submissions, 32%
Upcoming Conference
ASPDAC '25
- Sponsor:
- sigda
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