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HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths

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Mario SchölzelAuthors Info & Claims

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 723 - 728

Published: 08 March 2010 Publication History

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Abstract

This paper describes a hardware-/software-based technique to make the data path of a statically scheduled super scalar processor fault tolerant. The results of concurrently executed operations can be compared with little hardware overhead in order to detect a transient or permanent fault. Furthermore, the hardware extension allows to recover from a fault within one to two clock cycles and to distinguish between transient and permanent faults. If a permanent fault was detected, this fault is masked for the rest of the program execution such that no further time is needed for recovering from that fault. The proposed extensions were implemented in the data path of a simple VLIW processor in order to prove the feasibility and to determine the hardware overhead. Finally a reliability analysis is presented. It shows that for medium and large scaled data paths our extension provides an up to 98% better reliability than triple modular redundancy.

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Cited By

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Sabena DReorda MSterpone LRosenstiel WMacii E(2012)A new SBST algorithm for testing the register file of VLIW processorsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492812(412-417)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492812

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Information & Contributors

Information

Published In

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

March 2010

1868 pages

ISBN:9783981080162

General Chairs:
Giovanni De Micheli
EPF Lausanne, CH
,
Bashir Al-Hashimi
University of Southampton, UK
,
Program Chairs:
Wolfgang Mueller
University of Paderborn, SE
,
Enrico Macii
Politecnico di Torino, IT

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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DATE '10

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '10: Design, Automation and Test in Europe

March 8 - 12, 2010

Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Sabena DReorda MSterpone LRosenstiel WMacii E(2012)A new SBST algorithm for testing the register file of VLIW processorsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492812(412-417)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492812

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