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Scaling and evaluation of carbon nanotube interconnects for VLSI applications

Authors:

Vladimir Stojanović,

Anantha ChandrakasanAuthors Info & Claims

Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks

Article No.: 24, Pages 1 - 8

Published: 24 September 2007 Publication History

Abstract

The work in this paper addresses the need to evaluate the impact of emerging interconnect technologies, such as carbon nanotubes (CNTs), in the context of system applications. The critical properties of CNTs are described in terms of equivalent material parameters such that a general methodology of interconnect sizing can be used. This methodology is used to rescale the interlayer dielectric (ILD) stack-up and wire dimensions for different combinations of CNT and copper interconnects and vias; the stack-ups are then examined in an on-chip network application. The results of changing the ILD and wire sizing for a conservative estimate assuming a CNT bundle with 1/3 contacted metallic CNTs showed 30% improvement in delay and energy over copper at the 22 nm node and a 50% increase in total system throughput for a power constrained on-chip network application.

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Cited By

Mahabadi AKhonsari AKhodabandeloo BNoori HMajidi A(2015)Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systemsIntegration, the VLSI Journal10.1016/j.vlsi.2014.05.00248:C(21-35)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.05.002

Index Terms

Scaling and evaluation of carbon nanotube interconnects for VLSI applications
1. Hardware
  1. Emerging technologies

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Information

Published In

cover image Guide Proceedings

Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks

September 2007

124 pages

ISBN:9789639799103

General Chair:
Salvatore Coffa
STMicroelectronics, Italy

Sponsors

European Nanoelectronics Initiative Advisory Council
IEEE Communications Society
Create-Net

Publisher

ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)

Brussels, Belgium

Publication History

Published: 24 September 2007

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Cited By

Mahabadi AKhonsari AKhodabandeloo BNoori HMajidi A(2015)Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systemsIntegration, the VLSI Journal10.1016/j.vlsi.2014.05.00248:C(21-35)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.05.002

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