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A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
/ Prinzie, Jeffrey (Leuven U. ; CERN) ; Kulis, Szymon (CERN) ; Leitao, Pedro (CERN) ; Francisco, Rui (CERN) ; Smedt, Valentijn De (Leuven U.) ; Moreira, Paulo (CERN) ; Leroux, Paul (Leuven U. ; CERN)
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate for an additional pole in the VCO to harden it against ionizing particles. [...]
2019 - 4 p.
- Published in : 10.1109/LASCAS.2019.8667542
In : Latin American Symposium on Circuits and Systems, Armenia, Colombia, 24 - 27 Feb 2019, pp.63-66
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The lpGBT PLL and CDR Architecture, Performance and SEE Robustness
/ Biereigel, Stefan (Brandenburg Tech. U. ; Leuven U. ; CERN) ; Kulis, Szymon (CERN) ; Francisco, Rui (CERN) ; Leitao, Pedro Vicente (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. [...]
SISSA, 2020 - 5 p.
- Published in : PoS TWEPP2019 (2020) 034
Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.034
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A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology
/ Prinzie, Jeffrey (Leuven U.) ; Christiansen, Jorgen (CERN) ; Moreira, Paulo (CERN) ; Steyaert, Michiel (Leuven U.) ; Leroux, Paul (Leuven U.)
This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated circuit with an optimized voltage controlled oscillator (VCO) for single-event upsets (SEUs). The circuit is designed for high-energy particle physics experiments for low-jitter clock generation and clock recovery. [...]
2017 - 6 p.
- Published in : IEEE Trans. Nucl. Sci. 65 (2018) 407-412
In : 54th Annual IEEE International Nuclear and Space Radiation Effects Conference, New Orleans, LA, USA, 17 - 21 Jul 2017, pp.407-412
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Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade
/ Chen, C. (Hua-Zhong Normal U. ; Southern Methodist U.) ; Gong, D. (Southern Methodist U.) ; Guo, D. (Hua-Zhong Normal U.) ; Huang, G. (Hua-Zhong Normal U.) ; Huang, X. (Southern Methodist U. ; Hua-Zhong Normal U.) ; Kulis, S. (CERN) ; Leroux, P. (Leuven U.) ; Liu, C. (Southern Methodist U.) ; Liu, T. (Southern Methodist U.) ; Moreira, P. (CERN) et al.
We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. [...]
arXiv:2008.09741.-
2020-03-30 - 12 p.
- Published in : JINST 15 (2020) T03005
Fulltext: 2008.09741 - PDF; 10.1088_1748-0221_15_03_T03005 - PDF;
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A Radiation-Tolerant 25.6-Gb/s High-Speed Transmitter in 28-nm CMOS With a Tolerance of 1 Grad
/ Klekotko, A (CERN ; Leuven U.) ; Biereigel, S (CERN) ; Baszczyk, M (CERN) ; Moreira, P (CERN) ; Martina, F (CERN) ; Prinzie, J (Leuven U.) ; Kulis, S (Leuven U.)
This article presents a 25.6-Gbit $\cdot $ s−1 high-speed transmitter (HST) manufactured using 28-nm CMOS technology. The HST macroblock includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and a driver capable of driving the differential 100- $\Omega $ line as well as a silicon photonics (SiPh) ring modulator (RM). [...]
2024 - 9 p.
- Published in : IEEE Trans. Nucl. Sci. 71 (2024) 2124-2132
Fulltext: PDF;
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Radiation-tolerant all-digital clock generators for HEP applications
/ Biereigel, S (CERN ; Geel, Cathol. High Sch. Kempen ; Brandenburg Tech. U.) ; Kulis, S (CERN) ; Mendes, E (CERN) ; Hazell, P (CERN) ; Moreira, P (CERN) ; Prinzie, J (Geel, Cathol. High Sch. Kempen)
The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. [...]
2023 - 8 p.
- Published in : JINST 18 (2023) C01060
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C01060
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The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
/ Leitao, P (CERN) ; Francisco, R (CERN) ; Llopart, X (CERN) ; Tavernier, F (Leuven U.) ; Baron, S (CERN) ; Bonacini, S (CERN) ; Moreira, P (CERN)
A radiation-tolerant CDR/PLL ASIC has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR), showing deterministic phase and low jitter. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs for GBT-FPGA applications or providing 40, 80, 160 and 320 MHz clocks for TTC and e-link applications. [...]
2015
- Published in : JINST 10 (2015) C03024
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2014, Aix En Provence, France, 22 - 26 Sep 2014, pp.C03024
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A low-power low-noise synchronous pixel front-end chain in 65 nm CMOS technology with local fast ToT encoding and autozeroing for extreme rate and radiation at HL-LHC
/ Pacher, Luca (Turin U. ; INFN, Turin) ; Monteil, Ennio (Turin U. ; INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Demaria, Natale (INFN, Turin) ; Da Rocha Rolo, Manuel (INFN, Turin)
A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less Charge-Sensitive Amplifier (CSA) with constant current feedback provides triangular pulse shaping for linear Time-over-Threshold (ToT) charge measurement. [...]
2016 - 4 p.
- Published in : 10.1109/NSSMIC.2015.7581969
In : 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, San Diego, CA, USA, 31 Oct - 7 Nov 2015, pp.7581969
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