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Published Articles
Title Design of large scale sensors in 180 nm CMOS process modified for radiation tolerance
Author(s) Flores Sanz de Acedo, L (CERN ; Glasgow U.) ; Asensi Tortajada, I (CERN ; Valencia U.) ; Barbero, M (Marseille, CPPM) ; Berdalovic, I (Zagreb U.) ; Bespin, C (Bonn U.) ; Bortoletto, D (Oxford U.) ; Buttar, C (Glasgow U.) ; Caicedo, I (Bonn U.) ; Cardella, R (CERN) ; Dachs, F (CERN) ; Dao, V (CERN) ; Degerli, Y (AIM, Saclay) ; Dyndal, M (CERN) ; Freeman, P (CERN ; Birmingham U.) ; Habib, A (Marseille, CPPM) ; Hemperek, T (Bonn U.) ; Hirono, T (Bonn U.) ; Kugathasan, T (CERN) ; Moustakas, K (Bonn U.) ; Munker, M (CERN) ; Pernegger, H (CERN) ; Piro, F (CERN) ; Riedler, P (CERN) ; Rymaszewski, P (Bonn U.) ; Schioppa, E J (CERN) ; Schwemling, P (AIM, Saclay) ; Sharma, A (CERN ; Oxford U.) ; Argemi, L Simon (Glasgow U.) ; Snoeys, W (CERN) ; Sanchez, C Solans (CERN) ; Wang, T (Bonn U.) ; Wermes, N (Bonn U.)
Publication 2020
Number of pages 6
In: Nucl. Instrum. Methods Phys. Res., A 980 (2020) 164403
In: 12th international "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors (HSTD), Hiroshima, Japan, 14 - 18 Dec 2019, pp.164403
DOI 10.1016/j.nima.2020.164403
Subject category Detectors and Experimental Techniques
Abstract The last couple of years have seen the development of Depleted Monolithic Active Pixel Sensors (DMAPS) fabricated with a process modification to increase the radiation tolerance. Two large scale prototypes, Monopix with a column drain synchronous readout, and MALTA with a novel asynchronous architecture, have been fully tested and characterized both in the laboratory and in test beams. This showed that certain aspects have to be improved such as charge collection after irradiation and the output data rate. Some improvements resulting from extensive TCAD simulations were verified on a small test chip, Mini-MALTA. A detailed cluster analysis, using data from laboratory and test beam studies, at different biases, for high and low thresholds and before and after irradiation is presented, followed by detailed simulations showing that the digital architecture for both chips is capable of dealing with data rates of around 80 MHz/cm2 similar to what it is expected in the outer layer of the ATLAS inner tracker upgrade for the HL-LHC. The data rate capability and output bandwidth are studied using realistic hits generated by the ATLAS detector simulation framework.
Copyright/License © 2020 Published by Elsevier B.V.

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 Notice créée le 2020-08-28, modifiée le 2022-12-13