| Preprint | |
| Report number | arXiv:1806.09207 |
| Title | A new high speed, Ultrascale+ based board for the ATLAS jet calorimeter trigger system |
| Author(s) | Bauss, B. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Bücher, V. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Damp, J. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Degele, R. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Herr, H. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Kahra, C. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Rave, S. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Rocco, E. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Schäfer, U. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Souza, J. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Ta, D.B. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Tapprogge, S. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Weirich, M. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) ; Brogna, A. (Darmstadt, GSI ; Mainz U., Inst. Kernphys.) |
| Publication | 2018 |
| Imprint | 2018-06-24 |
| Number of pages | 3 |
| Note | conference record of 21st IEEE RealTime Conference |
| Presented at | 21st IEEE Real Time Conference, Williamsburg, Va, United States Of America, 9 - 15 Jun 2018 |
| Subject category | hep-ex ; Particle Physics - Experiment ; physics.ins-det ; Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Abstract | To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade. As a part of this, the Level 1 trigger based on calorimeter data will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) system is conceived to provide jet identification (including large area jets) and measurements of global variables within a latency budget of less then 400ns. It consists of 6 modules. A single jFEX module is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family, that can digest a total input data rate of 3.6 Tb/s using up to 120 Multi Gigabit Transceiver (MGT), 24 electrical optical devices, board control and power on the mezzanines to allow flexibility in upgrading controls functions and components without affecting the main board. The 24-layers stack-up was carefully designed to preserve the signal integrity in a very densely populated high speed signal board selecting MEGTRON6 as the most suitable PCB material. This contribution reports on the design challenges and the test results of the jFEX prototypes. In particular the fully assembled final prototype has been tested up to 12.8 Gb/s in house and in integrated tests at CERN. The full jFEX system will be produced by the end of 2018 to allow for installation and commissioning to be completed before LHC restarts in March 2021. |
| Other source | Inspire |
| Copyright/License | preprint: (License: CC-BY-4.0) |
Record created 2018-10-04, last modified 2022-10-07