A brief survey of papers on scheduling for pipelined processors
SM Krishnamurthy - ACM SIGPLAN Notices, 1990 - dl.acm.org
SM Krishnamurthy
ACM SIGPLAN Notices, 1990•dl.acm.orgMost microprocessors introduced into the market in the past few years employ pipelining to
enhance execution speed. Moreover, many of these processors use multiple pipelined
functional units. This paper surveys several heuristics reported in the literature on the topic
of code optimization and reordering for exploiting instruction level parallelism in pipelined
processors. Five methods are described in detail and several others are briefly reviewed
enhance execution speed. Moreover, many of these processors use multiple pipelined
functional units. This paper surveys several heuristics reported in the literature on the topic
of code optimization and reordering for exploiting instruction level parallelism in pipelined
processors. Five methods are described in detail and several others are briefly reviewed
Most microprocessors introduced into the market in the past few years employ pipelining to enhance execution speed. Moreover, many of these processors use multiple pipelined functional units. This paper surveys several heuristics reported in the literature on the topic of code optimization and reordering for exploiting instruction level parallelism in pipelined processors. Five methods are described in detail and several others are briefly reviewed