Three-dimensional (3-D) integration provides opportunities in large-scale integration of mixed-signal and general system-on-chip applications with improved performance, through increased density and mixing of different active and passive technologies. This paper reports a novel low-thermal-budget 3-D fabrication technique-multilayers with buried structures (MLBS) and an analysis of its applicability to mixed-signal integration. The MLBS technique uses a low temperature of 450/spl deg/C to transfer a single-crystal silicon layer over a processed wafer consisting of buried in-plane and out-of-plane interconnects obtained through a dual Damascene process. Devices can continue to be processed on this transferred layer. Electrical characteristics of MOS capacitors (D/sub it/=4.7/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/) and 3-D integrated planar CMOS transistors (3-D CMOS), fabricated using MLBS, are consistent with integration requirements. Our analog analysis includes an investigation of thermal effects important to analog applications with continuous operation of transistors in forward active bias, as well as of the coupling isolation derived from use of a ground-plane. Use of high density local interconnectivity improves the thermal properties of 3-D CMOS over that of silicon-on-insulator, and use of a ground plane is shown to lead to an improvement of better than 8 dB in coupling isolation.