Timing driven placement of pads and latches
B Chen, M Marek-Sadowska - [1992] Proceedings. Fifth Annual …, 1992 - ieeexplore.ieee.org
B Chen, M Marek-Sadowska
[1992] Proceedings. Fifth Annual IEEE International ASIC …, 1992•ieeexplore.ieee.orgA heuristic approach to the placement of I/O pads and sequential elements prior to the layout
of a VLSI circuit is presented. The input information for the algorithm is the structure of the
circuit and its path delay constraints. Experimental results suggest that the loss in
performance can be substantial (on the order of 10%) when pads and/or latches are placed
without consideration of performance.<>
of a VLSI circuit is presented. The input information for the algorithm is the structure of the
circuit and its path delay constraints. Experimental results suggest that the loss in
performance can be substantial (on the order of 10%) when pads and/or latches are placed
without consideration of performance.<>
A heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performance.< >
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