CHASE: Accelerating Distributed Pointer-Traversals on Disaggregated Memory
arXiv preprint arXiv:2305.02388, 2023•arxiv.org
Caches at CPU nodes in disaggregated memory architectures amortize the high data
access latency over the network. However, such caches are fundamentally unable to
improve performance for workloads requiring pointer traversals across linked data
structures. We argue for accelerating these pointer traversals closer to disaggregated
memory, in a manner that preserves expressiveness for supporting various linked structures,
ensures energy efficiency and performance, and supports distributed execution. We design …
access latency over the network. However, such caches are fundamentally unable to
improve performance for workloads requiring pointer traversals across linked data
structures. We argue for accelerating these pointer traversals closer to disaggregated
memory, in a manner that preserves expressiveness for supporting various linked structures,
ensures energy efficiency and performance, and supports distributed execution. We design …
Caches at CPU nodes in disaggregated memory architectures amortize the high data access latency over the network. However, such caches are fundamentally unable to improve performance for workloads requiring pointer traversals across linked data structures. We argue for accelerating these pointer traversals closer to disaggregated memory, in a manner that preserves expressiveness for supporting various linked structures, ensures energy efficiency and performance, and supports distributed execution. We design CHASE to meet all the above requirements for pointer-traversal workloads on rack-scale disaggregated memory through the principled use of FPGAbased SmartNICs and programmable network switches. Our evaluation of CHASE shows that it enables low-latency, highthroughput, and energy-efficient execution for a wide range of common pointer traversal workloads on disaggregated memory that fare poorly with caching alone.
arxiv.org