Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable
the estimation of the rise time of the output voltage and that of the power consumption during …

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been
developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and …

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully
operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the …

This paper compares the performance among two-phase switched-capacitor multipliers to
identify the optimum topology with the smallest circuit area. The optimum number of stages is …

Focusing on internal high-voltage (V/sub pp/) switching and generation for low-voltage
NAND flash memories, this paper describes a V/sub (pp)/ switch, row decoder, and charge-pump …

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel
flash memories, a multipage cell architecture has been proposed. This architecture enables …

Accordingly, as silicon technology has been advanced, more and more functionalities have
been integrated into LSIs. On-chip multiple voltage generation is becoming one of big …

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory
density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the …

Two word-line booster circuits, which output a word-line voltage for reading dash memory
data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage …

When quantum mechanical motion of a particle constrained to a curved surface in the Euclidean
space is considered, three different approaches may be adopted to describe the system…