… Lock Cache or simply lock cache.The SoC Lock Cache consists of registers to store lock …
notifying a waiting processor that a lock variable for which it was waiting has been freed.The …

… our previous work on synchronization support for System-on-a-Chip (SoC) [1]. … of lock latency,
lock delay and bandwidth consumption in a shared memory multi-processor SoC. The lock …

… A current-day system on a chip (SoC) consists of several … Major hardware items such as
busses, caches or DRAM … program in lock-step or else have some own local cache to avoid huge …

… In this paper, firstly we review two typical on-chip memory models cache and scratch pad …
cache model called addresslocking cache, which supports an innovative cache locking …

… is neither contention for the lock nor any penalty due to cache invalidation. This is because
… or in the caches, but instead wait for an interrupt. Therefore, in case of a lock release, the …

… Synchronous replication copies flits after reserving all destination ports in a lock-step,
which … in wormhole switching is susceptible to deadlocks because of the small buffer size. …

Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of
best practices for creating reusable designs for use in an SoC design methodology. These …

… between, say, a processor and a cache down to the interaction between the control part and
the … The choice of a DI code in the design of a system on a chip is dictated by a number of …

… caches (besides the rudimentary valid/invalid and clean/dirty states). Our approach exploits
a typical SoC cache hierarchy organization with many local L1 caches … of frequent locking. …

… Additionally, the Cell has on-chip Level 2 (L2) cache memory, interface components to … of
communicating between components in a system-on-a-chip (SoC) design. The simplicity and …