There has been a lot of discussion, and a lot of confusion, about the various existing and new design languages recently. SystemC, SystemVerilog, Verilog-2005, e, Vera, PSL/Sugar, UML, analogue and mixed-signal versions of Verilog and VHDL make the world a veritable alphabet soup. This paper briefly looks at the evolving world of design languages from a SystemC perspective. Although a design "language war" may seem imminent, there are strong prospects for peaceful coexistence between languages, and flows that connect them together. And such flows give tremendous opportunities for users of languages to significantly improve their methodologies. In addition, the needs of advanced system and system-on-chip (SoC) design turn up a number of interesting research opportunities for those involved in language-based design. The paper finishes by covering some of these methodology and research possibilities, including those opened up by further evolution in SystemC to include SW task and OS scheduler modelling.