User profiles for Rimantas Seinauskas
Rimantas SeinauskasKaunas university of technology Verified email at ktu.lt Cited by 375 |
A distance laboratory for computer-aided design
R Seinauskas - Proceedings of International Conference on …, 1997 - ieeexplore.ieee.org
A discussion has been held on the application of distance education at the CAD Laboratory
of the Kaunas University of Technology. Modern capabilities of the Internet open the ways of …
of the Kaunas University of Technology. Modern capabilities of the Internet open the ways of …
[PDF][PDF] Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests
R Seinauskas - Signal Processing, 2016 - researchgate.net
At speed delay testing is important for embedded systems. Attempts to solve the problems of
delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to …
delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to …
[PDF][PDF] Examination of the possibilities for integrated testing of embedded systems
R Seinauskas, V Seinauskas - American journal of embedded …, 2013 - researchgate.net
Separate testing of hardware and software of embedded systems is insufficient. Communication
between hardware and software parts needs to be tested during the integrated testing. …
between hardware and software parts needs to be tested during the integrated testing. …
Generating functional delay fault tests for non-scan sequential circuits
…, V Jusas, L Motiejūnas, R Šeinauskas - Information technology and …, 2010 - itc.ktu.lt
The paper presents two functional fault models that are devoted for functional delay test
generation for non-scan synchronous sequential circuits. These fault models form one joint …
generation for non-scan synchronous sequential circuits. These fault models form one joint …
The use of a software prototype for verification test generation
…, V Jusas, K Motiejūnas, R Šeinauskas - … Technology and Control, 2008 - itc.ktu.lt
The software prototype model can be used for the generation of the verification test. The input
stimuli, which form essential activity vectors, are selected from randomly generated ones …
stimuli, which form essential activity vectors, are selected from randomly generated ones …
Functional delay clock fault models
…, V Jusas, K Motiejūnas, R Šeinauskas - Information technology and …, 2008 - itc.ktu.lt
The test can be developed at the functional level of the circuit. Such an approach allows
developing the test at the early stages of the design process in parallel with other activities of …
developing the test at the early stages of the design process in parallel with other activities of …
The Realization‐Independent Testing Based on the Black Box Fault Models
E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas - Informatica, 2005 - content.iospress.com
The design complexity of systems on a chip drives the need to reuse legacy or intellectual
property cores, whose gate‐level implementation details are unavailable. In this paper we …
property cores, whose gate‐level implementation details are unavailable. In this paper we …
Test generation at the algorithm-level for gate-level fault coverage
…, V Jusas, K Motiejunas, R Seinauskas - Microelectronics …, 2008 - Elsevier
We present a test generation approach that enables to construct functional test patterns at
early stages of the design according to the software prototype of the circuit. The presented …
early stages of the design according to the software prototype of the circuit. The presented …
ASIC design flow and test generation capabilities
R Seinauskas - Радиоэлектроника и информатика, 2003 - cyberleninka.ru
… и информационным наукам, автор научной работы — Rimantas Seinauskas … по
компьютерным и информационным наукам , автор научной работы — Rimantas Seinauskas …
компьютерным и информационным наукам , автор научной работы — Rimantas Seinauskas …
Functional delay test generation based on software prototype
…, V Jusas, K Motiejunas, R Seinauskas - Microelectronics …, 2009 - Elsevier
The paper presents two methods of functional delay test development based on the software
prototype as well as the results of their application to benchmark circuits. The first method is …
prototype as well as the results of their application to benchmark circuits. The first method is …