Conventional serial connection of internal scan chains brings the power and time penalty. A
parallel core wrapper design (pCWD) approach is presented in this paper for reducing test
power and test application time. The pCWD utilizes overlapping scan slices to reduce the
number of scan slices loading. Experimental results on d695 of ITC2002 benchmark
demonstrated that, about 2/spl times/shift time and 20/spl times/test power reduction can be
achieved.