A multi-TOPS AI core is presented for acceleration of deep learning training and inference in
systems from edge devices to data centers. With a programmable architecture and custom …

The growing prevalence and computational demands of Artificial Intelligence (AI) workloads
has led to widespread use of hardware accelerators in their execution. Scaling the …

Low-precision computation is the key enabling factor to achieve high compute densities (TOPS/W
and TOPS/mm 2 ) in AI hardware accelerators across cloud and edge platforms. …

Advances in deep neural networks (DNNs) and the availability of massive real-world data
have enabled superhuman levels of accuracy on many AI tasks and ushered the explosive …

The organization and circuit design of a 1.0 GHz integer processor built in 0.25 /spl mu/m
CMOS technology are presented, a microarchitecture emphasizing parallel computation with a …

A processor core is presented for AI training and inference products. Leading-edge compute
efficiency is achieved for robust fp16 training via efficient heterogeneous 2-D systolic array-…

This letter presents a multi-TOPS AI accelerator core for deep learning training and inference.
With a programmable architecture and custom ISA, this engine achieves >90% sustained …

Reduced precision computation is a key enabling factor for energy-efficient acceleration of
deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision …

This paper presents a fast 64-bit parallel carry look-ahead binary adder implemented in a 1
GHz research prototype 64-bit PowerPC microprocessor. Efficient use of dynamic compound …

3D integration (3DI) holds promise for improved performance of integrated systems by
increasing interconnect bandwidth [1]. A processor stacked with cache memory is one potential …