With the ever-increasing degrees of integration, design of communication architectures for
big systems on chip (SoCs) is a challenge. The communication requirements of these large
multi processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC)
paradigm. To become a viable alternative IC design methodology, the NoC paradigm must
address system-level reliability issues, which are among the dominant concerns for SoC
design. The basic operations of NoCs are governed by on-chip packet switched networks …

Abstract Network on Chip (NoC) is an enabling methodology of integrating a very high
number of intellectual property (IP) blocks in a single System on Chip (SoC). A major
challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect
infrastructure under technology limitations. Research must address the combination of new
device-level defects or error-prone technologies within systems that must deliver high levels
of reliability and dependability while satisfying other hard constraints such as low energy …