| Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ... IEEE transactions on very large scale integration (VLSI) systems 25 (10 …, 2017 | 508 | 2017 |
| YodaNN: An architecture for ultralow power binary-weight CNN acceleration R Andri, L Cavigelli, D Rossi, L Benini IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 328 | 2017 |
| YodaNN: An ultra-low power convolutional neural network accelerator based on binary weights R Andri, L Cavigelli, D Rossi, L Benini 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 236-241, 2016 | 272 | 2016 |
| Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 263 | 2017 |
| GAP-8: A RISC-V SoC for AI at the Edge of the IoT E Flamand, D Rossi, F Conti, I Loi, A Pullini, F Rotenberg, L Benini 2018 IEEE 29th International Conference on Application-specific Systems …, 2018 | 248 | 2018 |
| PULP-NN: Accelerating quantized neural networks on parallel ultra-low-power RISC-V processors A Garofalo, M Rusci, F Conti, D Rossi, L Benini Philosophical Transactions of the Royal Society A 378 (2164), 20190155, 2020 | 174 | 2020 |
| Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing A Pullini, D Rossi, I Loi, G Tagliavini, L Benini IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019 | 173 | 2019 |
| An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ... IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017 | 159 | 2017 |
| PULP: A parallel ultra low power platform for next generation IoT applications D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015 | 154 | 2015 |
| Neurostream: Scalable and energy efficient deep learning with smart memory cubes E Azarkhish, D Rossi, I Loi, L Benini IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017 | 142 | 2017 |
| A transprecision floating-point platform for ultra-low power computing G Tagliavini, S Mach, D Rossi, A Marongiu, L Benini 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 132 | 2018 |
| Dory: Automatic end-to-end deployment of real-world dnns on low-cost iot mcus A Burrello, A Garofalo, N Bruschi, G Tagliavini, D Rossi, F Conti IEEE Transactions on Computers 70 (8), 1253-1268, 2021 | 128 | 2021 |
| PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision F Conti, D Rossi, A Pullini, I Loi, L Benini Journal of Signal Processing Systems 84, 339-354, 2016 | 115 | 2016 |
| Quentin: an ultra-low-power pulpissimo soc in 22nm fdx PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 95 | 2018 |
| NEURAghe Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs P Meloni, A Capotondi, G Deriu, M Brian, F Conti, D Rossi, L Raffo, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-24, 2018 | 91 | 2018 |
| Online learning and classification of EMG-based gestures on a parallel ultra-low power platform using hyperdimensional computing S Benatti, F Montagna, V Kartsch, A Rahimi, D Rossi, L Benini IEEE transactions on biomedical circuits and systems 13 (3), 516-528, 2019 | 90 | 2019 |
| Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ... IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021 | 87 | 2021 |
| PULP-HD: Accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform F Montagna, A Rahimi, S Benatti, D Rossi, L Benini Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 83 | 2018 |
| A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ... Solid-State Electronics 117, 170-184, 2016 | 79 | 2016 |
| Power, area, and performance optimization of standard cell memory arrays through controlled placement A Teman, D Rossi, P Meinerzhagen, L Benini, A Burg ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (4 …, 2016 | 77 | 2016 |
Luca BeniniETH Zürich, Università di BolognaVerified email at unibo.it
