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WO2022202936A1 - Silicon carbide semiconductor device, inverter circuit using same, and method for manufacturing silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device, inverter circuit using same, and method for manufacturing silicon carbide semiconductor device Download PDF

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Publication number
WO2022202936A1
WO2022202936A1 PCT/JP2022/013713 JP2022013713W WO2022202936A1 WO 2022202936 A1 WO2022202936 A1 WO 2022202936A1 JP 2022013713 W JP2022013713 W JP 2022013713W WO 2022202936 A1 WO2022202936 A1 WO 2022202936A1
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Prior art keywords
layer
semiconductor device
silicon carbide
deep
conductivity type
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PCT/JP2022/013713
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French (fr)
Japanese (ja)
Inventor
準市 上原
優介 羽山
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株式会社デンソー
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Priority claimed from JP2022045676A external-priority patent/JP7521553B2/en
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN202280023731.0A priority Critical patent/CN117083719A/en
Publication of WO2022202936A1 publication Critical patent/WO2022202936A1/en
Priority to US18/366,002 priority patent/US20230378292A1/en

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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

Definitions

  • the present disclosure relates to a silicon carbide (hereinafter also simply referred to as SiC) semiconductor device having a trench gate structure, an inverter circuit using the same, and a method for manufacturing the SiC semiconductor device.
  • SiC silicon carbide
  • a SiC semiconductor device in which a MOSFET (abbreviation for metal oxide semiconductor field effect transistor) having a trench gate structure is formed has been proposed (see, for example, Patent Document 1).
  • MOSFET abbreviation for metal oxide semiconductor field effect transistor
  • an n ⁇ -type buffer layer having an impurity concentration lower than that of the substrate is formed on an n + -type substrate, and an impurity concentration lower than that of the buffer layer is formed on the buffer layer.
  • a low-concentration layer is formed.
  • a p-type first deep layer extending in one direction as a longitudinal direction and an n-type JFET portion are formed on the low-concentration layer.
  • the first deep layers and the JFET portions are alternately arranged along the direction intersecting the longitudinal direction of the first deep layers and the JFET portions so that the JFET portions are arranged between adjacent first deep layers. It is An n-type current spreading layer and a p-type second deep layer are disposed on the first deep layer and the JFET portion. A p-type base layer is disposed on the current spreading layer and the second deep layer. The second deep layer is arranged to connect the first deep layer and the base layer.
  • n + -type source region is formed in the surface layer portion of the base layer.
  • a plurality of trenches are formed through the source region and the base layer to reach the current spreading layer, and a gate insulating film and a gate electrode are sequentially formed in each trench.
  • a trench gate structure is thus formed.
  • a parasitic diode is formed by a pn junction between the base layer and the like and the current spreading layer and the like. Therefore, it is conceivable that such a SiC semiconductor device utilizes a parasitic diode when reverse conduction occurs.
  • basal plane dislocations (hereinafter simply referred to as BPDs) may exist in the substrate.
  • BPDs basal plane dislocations
  • SFs stacking faults
  • An object of the present disclosure is to provide a SiC semiconductor device capable of suppressing an increase in on-voltage, an inverter circuit using the SiC semiconductor device, and a method for manufacturing the SiC semiconductor device.
  • a SiC semiconductor device has a cell portion in which a switching element is formed and an outer peripheral portion surrounding the cell portion, and the cell portion is a substrate of a first conductivity type made of SiC. a buffer layer of the first conductivity type formed on the substrate and having an impurity concentration lower than that of the substrate; and a low concentration layer of the first conductivity type formed on the buffer layer and having an impurity concentration lower than that of the substrate.
  • a first deep layer of a second conductivity type formed on the low-concentration layer and having a plurality of linear portions having a longitudinal direction in one direction in the surface direction of the substrate; a first conductivity type JFET portion having a linear portion sandwiched between deep layers; a first conductivity type current spreading layer disposed on the JFET portion and having an impurity concentration higher than that of the low concentration layer; a second conductive type second deep layer disposed on the deep layer; a second conductive type base layer disposed on the current spreading layer and the second deep layer; A trench gate having an impurity region of a first conductivity type, a gate insulating film formed on a wall surface of the trench penetrating the impurity region and the base layer and reaching the current spreading layer, and a gate electrode formed on the gate insulating film.
  • a defective portion is formed in the JFET portion.
  • the SiC semiconductor device when the SiC semiconductor device is in reverse conduction, it is possible to prevent carriers (for example, holes) from reaching the BPD due to being trapped in the defect. Therefore, it is possible to suppress the expansion of BPD to SF, and to suppress the on-voltage from increasing.
  • carriers for example, holes
  • an inverter circuit having an arm in which a MOSFET and a freewheeling diode are connected in parallel includes the SiC semiconductor device described above, the MOSFET is composed of a switching element, and the freewheeling diode is a switching It is composed of a parasitic diode configured within the element.
  • a parasitic diode configured in the SiC semiconductor device is used as the freewheeling diode provided in the inverter circuit. Therefore, there is no need to prepare a separate member that constitutes the free wheel diode separately from the MOSFET, and the configuration can be simplified.
  • the above-described manufacturing method for a SiC semiconductor device configures the JFET section by arranging the low-concentration layer as an epitaxial layer and performing ion implantation on the surface layer of the low-concentration layer. Then, ion implantation is performed to form a defective portion in the JFET portion.
  • FIG. 1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment
  • FIG. FIG. 2 is a perspective view showing a cell portion in FIG. 1
  • 2 is a diagram showing an inverter circuit configured using the SiC semiconductor device shown in FIG. 1
  • FIG. FIG. 4 is a diagram showing the relationship between forward voltage and current density when the SiC semiconductor device is in reverse conduction; It is a figure which shows the relationship between a forward current and an SF area occupation ratio.
  • FIG. 4 is a diagram showing the relationship between the impurity concentration of the JFET portion and the SF area occupation ratio; It is a figure which shows the relationship between channel length and SF area occupation ratio.
  • FIG. 4 is a diagram showing the relationship between the width of the first deep layer and the hole current density;
  • FIG. 4 is a diagram showing the relationship between trench spacing and hole current density;
  • FIG. 4 is a diagram showing the relationship between the interval of the first deep layer and the ON voltage;
  • FIG. 4 is a diagram showing the relationship between the interval of the first deep layer and the electric field applied to the gate insulating film;
  • FIG. 4 is a diagram showing the relationship between the spacing of the first deep layer and the feedback capacitance; It is a perspective view showing a cell portion of the SiC semiconductor device in the second embodiment.
  • FIG. 4 is a diagram showing the relationship between the width of the first deep layer and the hole current density;
  • FIG. 4 is a diagram showing the relationship between trench spacing and hole current density;
  • FIG. 4 is a diagram showing the relationship between the interval of the first deep layer and the ON voltage;
  • FIG. 4 is a diagram showing the relationship between the interval of the first deep layer and the electric field applied to the gate insulating film
  • FIG. 11 is a perspective view showing a cell portion of a SiC semiconductor device according to a third embodiment; It is a figure which shows the relationship between the depth and the impurity concentration of a p-type. It is sectional drawing which shows the manufacturing process of the SiC semiconductor device in 3rd Embodiment. 17B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 17A; FIG.
  • FIG. 1 A first embodiment will be described with reference to FIGS. 1 and 2.
  • FIG. 1 of the present embodiment an inverted MOSFET having a trench gate structure is formed as a switching element.
  • the SiC semiconductor device S1 has a cell portion 1 in which a MOSFET having a trench gate structure is formed, and an outer peripheral portion 2 surrounding the cell portion 1 .
  • the outer peripheral portion 2 has a guard ring portion 2a and a connecting portion 2b arranged inside the guard ring portion 2a.
  • the outer peripheral portion 2 has a guard ring portion 2a and a connecting portion 2b arranged between the cell portion 1 and the guard ring portion 2a.
  • one direction in the surface direction of the substrate 11 to be described later is defined as the X-axis direction
  • a direction intersecting one direction in the surface direction of the substrate is defined as the Y-axis direction
  • a direction orthogonal to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. described as a direction.
  • the X-axis direction and the Y-axis direction are orthogonal.
  • the horizontal direction on the page corresponds to the X-axis direction
  • the depth direction on the page corresponds to the Y-axis direction
  • the vertical direction on the page corresponds to the Z-axis direction.
  • the SiC semiconductor device S1 is configured using semiconductor substrate 10 .
  • the SiC semiconductor device S1 includes an n + -type substrate 11 made of SiC.
  • the substrate 11 has, for example, an off angle of 0 to 8° with respect to the (0001) Si plane, and the concentration of n-type impurities such as nitrogen and phosphorus is 1.0 ⁇ 10 19 /cm 3 . and a thickness of about 300 ⁇ m is used.
  • the substrate 11 constitutes a drain region in this embodiment.
  • n ⁇ -type buffer layer 12 made of SiC is formed on the surface of the substrate 11 .
  • the buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11 .
  • the buffer layer 12 has an n-type impurity concentration between the substrate 11 and the low-concentration layer 13 described later, and has a thickness of about 1 ⁇ m.
  • an n.sup.--type silicon nitride film made of SiC having an n - type impurity concentration of 5.0 to 10.0.times.10.sup.15/ cm.sup.3 and a thickness of about 10 to 15 .mu.m is formed on the surface of the buffer layer 12.
  • a density layer 13 is formed on the surface of the buffer layer 12.
  • the impurity concentration of the low-concentration layer 13 may be constant in the Z-axis direction, but the concentration distribution is inclined so that the low-concentration layer 13 on the substrate 11 side is closer to the substrate 11 than on the side away from the substrate 11 . It is also preferred that the concentration is also high.
  • the low-concentration layer 13 preferably has an impurity concentration of about 2.0 ⁇ 10 15 /cm 3 in a portion about 3 to 5 ⁇ m from the surface of the substrate 11 higher than that in other portions. With such a configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced. Also, the low-concentration layer 13 is composed of an epitaxial layer formed by epitaxial growth.
  • a JFET portion 14 and a first deep layer 15 are formed in the surface layer portion of the low-concentration layer 13 at the connecting portion 2 b between the cell portion 1 and the outer peripheral portion 2 .
  • the JFET portion 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions alternately and repeatedly arranged in the Y-axis direction.
  • the JFET portion 14 and the first deep layer 15 each have a stripe shape extending along the X-axis direction in the direction normal to the surface of the substrate 11 (hereinafter also simply referred to as the normal direction).
  • the layout is such that they are alternately arranged along the Y-axis direction.
  • the normal direction to the surface of the substrate 11 in other words, when viewed from the normal direction to the surface of the substrate 11.
  • the JFET portion 14 is of n-type with a higher impurity concentration than the low-concentration layer 13 and has a depth of 0.3 to 1.5 ⁇ m.
  • the JFET portion 14 has an n-type impurity concentration of 7.0 ⁇ 10 16 to 5.0 ⁇ 10 17 /cm 3 .
  • the JFET portion 14 of the present embodiment is an ion-implanted layer formed by ion-implanting n-type impurities into the low-concentration layer 13, and the defect portion D formed by ion-implanting is formed.
  • the first deep layer 15 has, for example, a p-type impurity concentration such as boron of 2.0 ⁇ 10 17 to 2.0 ⁇ 10 18 /cm 3 .
  • the first deep layer 15 of this embodiment extends from the JFET section 14 to the side of the guard ring section 2a.
  • the first deep layer 15 of this embodiment is formed shallower than the JFET section 14 .
  • the first deep layer 15 is formed so that the bottom is positioned inside the JFET section 14 .
  • the first deep layer 15 is formed so that the JFET portion 14 is positioned between the low-concentration layer 13 and the first deep layer 15 .
  • the width L1 of the first deep layer 15 of this embodiment is 0.9 ⁇ m or less.
  • the width L1 of the first deep layer 15 is the length in the direction perpendicular to the longitudinal direction of the first deep layer 15 and the length in the plane direction of the semiconductor substrate 10 . That is, the width L1 of the first deep layer 15 is the length of the first deep layer 15 along the Y-axis direction.
  • the interval L2 between adjacent first deep layers 15 is 0.75 to 1.1 ⁇ m.
  • the interval L2 between adjacent first deep layers 15 is the length along the Y-axis direction of the portion sandwiched between the first deep layers 15 in the JFET section 14 .
  • a plurality of p-type guard rings 16 are provided on the surface layer of the low-concentration layer 13 so as to surround the cell section 1 in the guard ring section 2 a of the outer peripheral section 2 .
  • the upper surface layout of the guard ring 16 is in the shape of a rectangle with rounded corners, a circle, or the like in the normal direction.
  • a current spreading layer 17 and a second deep layer 18 are formed on the JFET section 14 and the first deep layer 15 in the cell section 1 .
  • the current spreading layer 17 is composed of an n-type impurity layer and has a thickness of 0.5 to 2 ⁇ m. Further, the n-type impurity concentration of the current spreading layer 17 is, for example, 1.0 ⁇ 10 16 to 5.0 ⁇ 10 17 /cm 3 . Also, the current spreading layer 17 is connected to the JFET section 14 . Therefore, in the present embodiment, the low-concentration layer 13, the JFET section 14, and the current spreading layer 17 are connected, and the drift layer 19 is configured by these.
  • the second deep layer 18 is formed in the cell section 1, and has a p-type impurity concentration of, for example, 2.0 ⁇ 10 17 to 2.0 ⁇ 10 18 /cm 3 and a thickness equal to that of the current spreading layer. 17. Also, the second deep layer 18 is formed so as to be connected to the first deep layer 15 .
  • the current spreading layer 17 and the second deep layer 18 extend in a direction crossing the striped portion of the JFET section 14 and the longitudinal direction of the first deep layer 15 .
  • the current spreading layers 17 and the second deep layers 18 are laid out with the Y-axis direction as the longitudinal direction and arranged alternately in the X-axis direction.
  • the formation pitch of the current spreading layer 17 and the second deep layer 18 is matched with the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed so as to sandwich the trench 24 described later.
  • a current spreading layer 17 and a resurf layer 20 are formed on the low-concentration layer 13 , JFET section 14 , first deep layer 15 , and guard ring 16 in the outer peripheral portion 2 .
  • the resurf layer 20 is formed in the connecting portion 2 b of the outer peripheral portion 2 and is formed so as to be connected to the first deep layer 15 .
  • a P-type base layer 21 is formed on the current spreading layer 17 , the second deep layer 18 , and the RESURF layer 20 .
  • An n + -type source region 22 and a p + -type contact region 23 are formed in the surface layer portion of the base layer 21 in the cell portion 1 .
  • the source region 22 is formed in contact with the side surface of a trench 24 to be described later, and the contact region 23 is formed on the opposite side of the trench 24 with the source region 22 interposed therebetween.
  • the source region 22 corresponds to the impurity region.
  • the base layer 21 has, for example, a p-type impurity concentration of 3.0 ⁇ 10 17 /cm 3 or less. Also, the base layer 21 of the present embodiment is formed by, for example, ion implantation, and the impurity concentration in the cell section 1 is higher than that in the outer peripheral section 2 .
  • the source region 22 has an n-type impurity concentration in the surface layer, ie, a surface concentration of 1.0 ⁇ 10 21 /cm 3 , for example.
  • the contact region 23 has a p-type impurity concentration in the surface layer, ie, a surface concentration of 1.0 ⁇ 10 21 /cm 3 , for example.
  • the thickness of the base layer 21 and the source region 22 are adjusted so that the channel length is 0.4 ⁇ m or less.
  • the channel length is the length of the portion of the base layer 21 along the side surface of the trench 24 in the Z-axis direction (that is, the stacking direction of the substrate 11 and the buffer layer 12). .
  • the channel length is the length between the source region 22 of the base layer 21 and the current spreading layer 17 .
  • the semiconductor substrate 10 is configured by stacking the contact regions 23 and the like.
  • the surface of the semiconductor substrate 10 facing the substrate 11 is referred to as the other surface 10b of the semiconductor substrate 10
  • the surface facing the source region 22 and the contact region 23 is referred to as one surface 10a of the semiconductor substrate 10.
  • FIG. Source region 22 and contact region 23 are exposed from one surface 10 a of semiconductor substrate 10 .
  • the semiconductor substrate 10 has a width of, for example, 1.4 to 2.0 ⁇ m so that it reaches the current spreading layer 17 through the base layer 21 and the like, and the bottom surface is located in the current spreading layer 17. and a trench 24 is formed. Note that the trench 24 is formed so as not to reach the JFET portion 14 and the first deep layer 15 . That is, the trench 24 is formed so that the JFET portion 14 and the first deep layer 15 are located below the bottom surface.
  • a plurality of trenches 24 extend along the Y-axis direction, and are arranged in stripes at equal intervals in the X-axis direction. That is, in this embodiment, the trench 24 is formed so that its longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15 . Also, the trench 24 is formed so as to be sandwiched between the second deep layers 18 in the normal direction.
  • the trenches 24 of the present embodiment are formed such that the distance between the centers of adjacent trenches 24 (that is, the trench pitch) is 3.0 ⁇ m or less.
  • the trench 24 is filled with a gate insulating film 25 formed on the inner wall surface and a gate electrode 26 made of doped Poly-Si formed on the surface of the gate insulating film 25 .
  • a trench gate structure is thus formed.
  • the gate insulating film 25 is formed on the inner wall surface of the trench 24 by thermal oxidation or CVD (abbreviation for chemical vapor deposition).
  • the gate insulating film 25 has a thickness of about 100 nm on both the side and bottom sides of the trench 24 .
  • the gate insulating film 25 is also formed on surfaces other than the inner wall surface of the trench 24 . Specifically, the gate insulating film 25 is formed so as to also partially cover the one surface 10 a of the semiconductor substrate 10 . More specifically, the gate insulating film 25 is formed so as to also partially cover the surface of the source region 22 . In other words, in the gate insulating film 25, a contact hole 25a exposing the remaining portions of the contact region 23 and the source region 22 is formed in a portion different from the portion where the gate electrode 26 is arranged.
  • the gate insulating film 25 is also formed on the surface of the base layer 21 in the connecting portion 2b. Similarly to the gate insulating film 25, the gate electrode 26 also extends to the surface of the gate insulating film 25 at the connecting portion 2b.
  • the trench gate structure of the present embodiment is constructed as described above.
  • a concave portion 10 c is formed in the guard ring portion 2 a of the outer peripheral portion 2 so as to penetrate the base layer 21 and reach the resurf layer 20 and the current spreading layer 17 .
  • a mesa structure is formed in the SiC semiconductor device S1 of the present embodiment.
  • a contact region 23 is formed in the surface layer portion of the base layer 21 in the connecting portion 2b, as in the cell portion 1. As shown in FIG.
  • An interlayer insulating film 27 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 26, the gate insulating film 25, and the like.
  • the interlayer insulating film 27 is made of BPSG (abbreviation for Borophosphosilicate Glass) or the like.
  • a contact hole 27a is formed in the interlayer insulating film 27 to communicate with the contact hole 25a and expose the source region 22 and the contact region 23 .
  • a contact hole 27b is formed in the interlayer insulating film 27 to expose a portion of the gate electrode 26 extending to the connecting portion 2b. That is, the interlayer insulating film 27 has a contact hole 27 a formed in the cell portion 1 and a contact hole 27 b formed in the outer peripheral portion 2 .
  • the contact hole 27a formed in the interlayer insulating film 27 is formed so as to communicate with the contact hole 25a formed in the gate insulating film 25, and functions together with the contact hole 25a as one contact hole. Therefore, hereinafter, the contact hole 25a and the contact hole 27a are collectively referred to as the contact hole 25b.
  • the pattern of the contact holes 25b is arbitrary, and examples thereof include a pattern in which a plurality of square holes are arranged, a pattern in which rectangular linear holes are arranged, a pattern in which linear holes are arranged, and the like. be done. In this embodiment, the contact hole 25b is linear along the longitudinal direction of the trench 24 .
  • a source electrode 28 electrically connected to the source region 22 and the contact region 23 through the contact hole 25b is formed on the interlayer insulating film 27. As shown in FIG. The source electrode 28 of this embodiment is also connected to the contact region 23 formed in the base layer 21 of the outer peripheral portion 2 . A gate wiring 29 electrically connected to the gate electrode 26 through a contact hole 27b is formed on the interlayer insulating film 27. As shown in FIG. Incidentally, in this embodiment, the source electrode 28 corresponds to the first electrode.
  • the source electrode 28 of this embodiment is composed of a plurality of metals such as Ni/Al, for example.
  • a portion of the plurality of metals, which is in contact with the portion forming the n-type SiC (that is, the source region 22), is made of a metal capable of making ohmic contact with the n-type SiC.
  • At least the portion of the plurality of metals that contacts p-type SiC (that is, contact region 23) is made of a metal capable of making ohmic contact with p-type SiC.
  • the gate wiring 29 may have the same structure as the source electrode, or may be made of Al--Si or the like.
  • a protective film 30 made of polyimide or the like is formed so as to cover the connecting portion 2b and the guard ring portion 2a.
  • the protective film 30 is formed from the outer peripheral portion 2 to the outer edge portion of the cell portion 1 in order to suppress creeping discharge from occurring between the source electrode 28 and the drain electrode 31, which will be described later.
  • the protective film 30 is formed so as to cover the portion of the source electrode 28 on the side of the outer peripheral portion 2 while exposing the portion of the source electrode 28 on the inner edge side. .
  • a drain electrode 31 electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10 .
  • the drain electrode 31 corresponds to the second electrode.
  • such a structure constitutes a MOSFET having a trench gate structure, which is an n-channel type inversion type.
  • a parasitic diode is formed by a pn junction between the drift layer 19 and the base layer 21 and the like.
  • n + type, n type, and n ⁇ type correspond to the first conductivity type
  • p ⁇ type, p type, and p + type correspond to the second conductivity type.
  • the SiC semiconductor device S1 is used, for example, to configure an inverter circuit 100 as shown in FIG.
  • the inverter circuit 100 is used, for example, to drive a three-phase motor 101 and is used to supply an alternating current to the three-phase motor 101 using a DC power supply 102 .
  • the inverter circuit 100 connects in parallel a plurality of bridge circuits in which the upper arm and the lower arm are connected in series to the DC power supply 102, and the upper arm and the lower arm of each bridge circuit are alternately turned on and off repeatedly. to supply alternating current to the load.
  • the inverter circuit 100 is configured by connecting a freewheeling diode S12 in parallel to the MOSFET S11.
  • each of the upper arm and the lower arm of each phase is configured with the SiC semiconductor device S1. More specifically, the MOSFET of the SiC semiconductor device S1 constitutes the MOSFET S11 of each arm, and the parasitic diode of the SiC semiconductor device S1 constitutes the free wheel diode S12 of each arm.
  • each bridge circuit of the inverter circuit 100 current is supplied to the load by turning on the MOSFET S11 of the upper arm and turning off the MOSFET S11 of the lower arm. Further, after that, the current supply is stopped by turning off the MOSFET S11 of the upper arm and turning on the MOSFET S11 of the lower arm.
  • the operation of the upper arm SiC semiconductor device S1 is as follows. That is, in this SiC semiconductor device S1, an inversion layer is not formed in the base layer 21 in the OFF state before the gate voltage is applied to the gate electrode 26. FIG. Therefore, even if a positive voltage of, for example, 1600 V is applied to the drain electrode 31, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device S1 is located between the source electrode 28 and the drain electrode 31. becomes an off state in which no current flows through.
  • the SiC semiconductor device S1 when the SiC semiconductor device S1 is in the off state, an electric field is applied between the drain and the gate, and electric field concentration may occur at the bottom of the gate insulating film 25.
  • FIG. 1 in the SiC semiconductor device S ⁇ b>1 described above, the first deep layer 15 and the JFET portion 14 are provided at positions deeper than the trench 24 . Therefore, the depletion layer formed between the first deep layer 15 and the JFET portion 14 suppresses the rising of the equipotential lines due to the influence of the drain voltage, making it difficult for the high electric field to enter the gate insulating film 25 . Therefore, in this embodiment, it is possible to prevent the gate insulating film 25 from being destroyed.
  • a predetermined gate voltage for example 20 V
  • a channel is formed on the surface of the base layer 21 that is in contact with the trench 24.
  • a current flows between the source electrode 28 and the drain electrode 31, and the SiC semiconductor device S1 is turned on.
  • electrons passing through the channel flow to the substrate 11 through the current spreading layer 17, the JFET portion 14 and the lightly doped layer 13. Therefore, the current spreading layer 17, the JFET portion 14 and the lightly doped layer 13 are It can be said that the drift layer 19 having
  • the defect portion D is formed in the JFET portion 14 .
  • the defect portion D functions as a hole trap. Therefore, as shown in FIG. 4, compared to the SiC semiconductor device S1 in which the defect portion D is not formed, the current density during reverse conduction can be reduced, and the holes are suppressed from reaching the low-concentration layer 13. can. As a result, it is possible to suppress the expansion of the BPD to the SF and suppress the increase in the on-voltage.
  • the cell portion 1 of the base layer 21 has a higher impurity concentration than the outer peripheral portion 2 . Therefore, when SiC semiconductor device S1 is in the reverse conducting state, the forward voltage of cell portion 1 tends to be lower than the forward voltage of outer peripheral portion 2 . Therefore, the forward current can easily flow into the cell section 1 in which the defect portion D is formed, and the expansion of the BPD to the SF in the outer peripheral portion 2 can be suppressed.
  • SiC semiconductor device S1 of the present embodiment Further detailed conditions and effects of the SiC semiconductor device S1 of the present embodiment will be described below.
  • the first deep layer 15 is formed shallower than the JFET section 14 .
  • a JFET portion 14 is also arranged between the first deep layer 15 and the low-concentration layer 13 . Therefore, holes can also be trapped by the JFET portion 14 between the first deep layer 15 and the low-concentration layer 13 . Therefore, as shown in FIG. 5, the SF area occupation ratio can be reduced.
  • the JFET portion 14 and the first deep layer 15 have the same depth, and the SiC semiconductor device S1 in which the JFET portion 14 is not arranged between the first deep layer 15 and the low-concentration layer 13 is compared. It is shown as an example. Further, the SF area occupation ratio indicates the ratio of stacking faults in the SiC semiconductor device S1. A small SF area occupation ratio indicates that BPD is difficult to expand to SF.
  • the SiC semiconductor device S1 of this embodiment is configured to satisfy the following conditions.
  • the JFET section 14 of this embodiment is composed of an ion-implanted layer obtained by ion-implanting an n-type impurity into the low-concentration layer 13 . Therefore, as the impurity concentration of the JFET portion 14 increases (that is, the dose amount increases), the number of defect portions D increases, and the function as a hole trap layer increases. Specifically, as shown in FIG. 6, it is confirmed that the SF area occupation ratio of the JFET portion 14 decreases when the impurity concentration is 7.0 ⁇ 10 16 /cm 3 or more. However, it is confirmed that the SF area occupation ratio of the JFET portion 14 increases when the impurity concentration is 5.0 ⁇ 10 17 /cm 3 or more.
  • the JFET section 14 is composed of an ion-implanted layer and has an impurity concentration of 7.0 ⁇ 10 16 to 5.0 ⁇ 10 17 /cm 3 .
  • the ratio of the electron current flowing in the base layer 21 in the punch-through mode can be increased by shortening the channel length, so that the ratio of the hole current can be reduced.
  • the ratio of the hole current By reducing the ratio of the hole current, the number of holes reaching the BPD can also be reduced, so it is possible to suppress the expansion of the BPD to the SF.
  • the SF area occupation ratio may become 0 when the channel length is 0.4 ⁇ m or less, and the SF area occupation ratio decreases as the channel length becomes smaller than 0.4 ⁇ m. It is confirmed that Therefore, in this embodiment, the thickness of the base layer 21 and the depth of the source region 22 are adjusted so that the channel length is 0.4 ⁇ m or less.
  • the impurity concentration of the base layer 21 may be lowered. Specifically, as shown in FIG. 8, when the impurity concentration of the base layer 21 is 3.0 ⁇ 10 17 /cm 3 or less, the SF area occupancy may become zero. Therefore, in this embodiment, the impurity concentration of the base layer 21 is 3.0 ⁇ 10 17 /cm 3 or less.
  • the width L1 of the first deep layer 15 may be defined. Specifically, as shown in FIG. 9, when the width L1 of the first deep layer 15 is 0.9 ⁇ m or less, the hole current density can be 4.5 ⁇ 10 16 /cm 3 or less. Therefore, in this embodiment, the width L1 of the first deep layer 15 is set to 0.9 ⁇ m or less. Note that the hole current density in FIG. 9 indicates the density of the hole current flowing into the buffer layer 12 .
  • the distance between the centers of adjacent trenches 24 may be defined.
  • the hole current density can be reduced to 4.5 ⁇ 10 16 /cm 3 or less by setting the distance between the centers of adjacent trenches 24 to 3.0 ⁇ m or less. Note that the hole current density in FIG. 10 indicates the density of the hole current flowing into the buffer layer 12 .
  • the following characteristics are also important characteristics.
  • the on-voltage that is, Von
  • the SiC semiconductor device S1 when the SiC semiconductor device S1 is in the on-state increases in the first deep layers 15 as the interval L2 between the adjacent first deep layers 15 increases. Since the width of the sandwiched JFET portion 14 is widened, it becomes small. At present, it is desired that the on-voltage be 0.9 V or less when 200 A is applied. Therefore, the interval L2 between adjacent first deep layers 15 is set to 0.75 ⁇ m or more.
  • the electric field (that is, Emax) applied to the gate insulating film 25 in the OFF state is sandwiched between the first deep layers 15 as the distance L2 between the adjacent first deep layers 15 is increased. Since the width of the JFET portion 14 that is connected to the substrate is widened, the height is increased. At present, it is desired that the electric field applied to the gate insulating film 25 in the OFF state is 5 MV/cm or less. Therefore, the interval L2 between adjacent first deep layers 15 is set to 1.2 ⁇ m or less.
  • the feedback capacitance (that is, Crss) increases the width of the JFET portion 14 sandwiched between the first deep layers 15 as the interval L2 between the adjacent first deep layers 15 increases. get higher At present, it is desired to set the feedback capacitance to 50 pF or less. Therefore, the interval L2 between adjacent first deep layers 15 is set to 1.1 ⁇ m or less.
  • the interval L2 between adjacent first deep layers 15 is 0.75 to 1.1 ⁇ m.
  • the defective portion D is formed in the JFET portion 14 . Therefore, it is possible to prevent holes from being trapped in the defect portion D and reaching the BPD during reverse conduction of the SiC semiconductor device S1. Therefore, it is possible to suppress the expansion of BPD to SF, and to suppress the on-voltage from increasing.
  • the impurity concentration of the base layer 21 in the cell section 1 is higher than that in the outer peripheral section 2 . Therefore, when SiC semiconductor device S1 is in the reverse conducting state, the forward voltage of cell portion 1 is lower than the forward voltage of outer peripheral portion 2 . Therefore, the forward current can easily flow into the cell section 1 in which the defect portion D is formed, and the expansion of the BPD to the SF in the outer peripheral portion 2 can be suppressed.
  • the first deep layer 15 is formed shallower than the JFET section 14 .
  • a JFET portion 14 is arranged between the first deep layer 15 and the low-concentration layer 13 . Therefore, holes can also be trapped by the JFET portion 14 between the first deep layer 15 and the low-concentration layer 13 . Therefore, it is possible to further suppress the holes from reaching the BPD, and further suppress the expansion of the BPD to the SF.
  • the JFET portion 14 has an impurity concentration of 7.0 ⁇ 10 16 to 5.0 ⁇ 10 17 /cm 3 . Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5 ⁇ 10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
  • the channel length is 0.4 ⁇ m. Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5 ⁇ 10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
  • the impurity concentration of the base layer 21 is 3.0 ⁇ 10 17 /cm 3 . Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5 ⁇ 10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
  • the first deep layer 15 has a width L1 of 0.9 ⁇ m or less. Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5 ⁇ 10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
  • the first deep layer 15 extends to the outer peripheral portion 2 . Therefore, diode characteristics in the outer peripheral portion 2 can be improved.
  • the distance between the centers of adjacent trenches 24 is 3.0 ⁇ m or less. Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5 ⁇ 10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
  • the interval L2 between adjacent first deep layers 15 is 0.75 ⁇ m or more. Therefore, an increase in ON voltage can be suppressed.
  • the interval L2 between adjacent first deep layers 15 is 1.1 ⁇ m or less. Therefore, it is possible to suppress an increase in the electric field applied to the gate insulating film 25 in the OFF state, and an increase in the feedback capacitance.
  • a parasitic diode configured in the SiC semiconductor device S1 is used as the freewheeling diode S12 provided in the inverter circuit 100.
  • FIG. Therefore, there is no need to prepare a separate member that constitutes the free wheel diode S12 in addition to the MOSFETS11, so that the configuration can be simplified.
  • the linear portions of the first deep layer 15 and the current spreading layer 17 are extended with the Y-axis direction as the longitudinal direction. Also, the first deep layer 15 is formed so as to sandwich the trench 24 in the normal direction.
  • the base layer 21 is formed with the defective portion D1
  • the current spreading layer 17 is formed with the defective portion D2.
  • the defect portion D1 of the base layer 21 is formed by configuring the base layer 21 by ion implantation.
  • the defect portion D2 of the current spreading layer 17 is formed when p-type impurities enter the current spreading layer 17 when the base layer 21 is formed by ion implantation.
  • the base layer 21 and the current spreading layer 17 are configured such that the p-type impurity exists in the current spreading layer 17 in the p-type impurity concentration distribution. .
  • base layer 21 and current spreading layer 17 are formed such that tail portion T in the p-type impurity concentration distribution is located in current spreading layer 17 .
  • the tail portion T in the impurity concentration distribution is the portion on the side of the other surface 10b in the depth direction.
  • the base layer 21 and the current spreading layer 17 are formed by performing ion implantation a plurality of times while changing the acceleration voltage to form the base layer 21, and removing the p-type impurity in forming the base layer 21 with a current. It is formed by penetrating into the dispersion layer 17 .
  • FIG. 16 shows a diagram when ion implantation is performed three times while changing the acceleration voltage.
  • the base layer 21 and the current spreading layer 17 of the present embodiment have a p-type impurity concentration of 1.0 ⁇ 10 in the current spreading layer 17 so that the defect D2 is sufficiently formed in the current spreading layer 17. It is configured to have a portion of 15 /cm 3 or more. According to the studies of the present inventors, when the current spreading layer 17 is configured to have a portion where the p-type impurity concentration is 1.0 ⁇ 10 15 /cm 3 or more, the defect portion is sufficient. It has been confirmed that D2 is formed.
  • the above is the configuration of the SiC semiconductor device S1 in this embodiment.
  • a method for forming the defective portion D1 of the base layer 21 and the defective portion D2 of the current spreading layer 17 in the SiC semiconductor device S1 will be described with reference to FIGS. 17A and 17B.
  • a substrate 11, a buffer layer 12, a low-concentration layer 13, a JFET portion 14, a first deep layer 15, a current spreading layer 17, and a second deep layer 18 are prepared.
  • the base layer constituting layer 210 constituting the base layer 21 is arranged as an epitaxially grown epitaxial layer.
  • the base layer-constituting layer 210 is epitaxially grown so as to have an impurity concentration that is one order of magnitude lower than the impurity concentration when the base layer 21 is formed by ion implantation, which will be described later.
  • the thickness of the base layer-constituting layer 210 of the present embodiment is equal to that of the base layer 21 .
  • the base layer configuration layer 210 may have a thickness equal to the sum of the thickness of the base layer 21 and the thickness of the source region 22 .
  • the base layer 21 is formed by performing ion implantation a plurality of times while changing the acceleration voltage.
  • the current spreading layer 17 includes a portion having a p-type impurity concentration of 1.5 ⁇ 10 15 /cm 3 .
  • the base layer 21 is formed by ion implantation while changing the voltage. Note that FIG. 16 shows a case where ion implantation is performed three times while changing the acceleration voltage. As a result, the base layer 21 is formed with the defective portion D1, and the current spreading layer 17 is formed with the defective portion D2.
  • the defect portion D of the JFET portion 14 is formed by ion implantation.
  • the defect D1 of the base layer 21 and the defect D2 of the current spreading layer 17 are formed by ion implantation.
  • the ion implantation is performed so that a larger number of defects than those which may occur when the low-concentration layer 13 and the base layer-constituting layer 210 for forming the JFET section 14 are epitaxially grown and arranged.
  • the temperature is such that D, D1 and D2 are formed.
  • the temperature at which each ion implantation is performed is from room temperature to 200° C. or less.
  • the room temperature in this embodiment means a temperature of about 1 to 30.degree.
  • the SiC semiconductor device S1 is manufactured by forming the source region 22, the contact region 23, the trench gate structure, and the like.
  • the defective portion D is formed in the JFET portion 14, it is possible to obtain the same effects as in the first embodiment.
  • the defect portion D1 is formed in the base layer 21 and the defect portion D2 is formed in the current spreading layer 17 . Therefore, in the path through which the hole current flows, the portions that become the defective portions D1 and D2 increase, and the holes can be trapped in areas other than the defective portion D of the JFET portion 14, so that the holes can be further suppressed from reaching the BPD. .
  • the current spreading layer 17 is configured to have a portion where the p-type impurity concentration is 1.0 ⁇ 10 15 /cm 3 or more. Therefore, the defect D2 caused by the p-type impurity can be easily formed in the current spreading layer 17 .
  • the base layer 21 is formed by performing ion implantation multiple times. Therefore, the current spreading layer 17 having a portion with a p-type impurity concentration of 1.0 ⁇ 10 15 /cm 3 or more can be easily formed.
  • the base layer 21 is formed by performing ion implantation a plurality of times, the impurity concentration distribution in the depth direction in the base layer 21 varies as compared with the case where the base layer 21 is formed by, for example, one ion implantation. can be suppressed. Therefore, it is possible to suppress the fluctuation of the threshold voltage to the gate electrode 26 required to turn on the SiC semiconductor.
  • the impurity concentration is set to be lower than that of the base layer 21 by one order of magnitude or more.
  • in-plane variations in impurity concentration can be suppressed compared to the case where the base layer 21 having a desired impurity concentration is formed by epitaxial growth.
  • ion implantation is performed at a temperature of 200° C. or less. Therefore, it is possible to prevent the defects D, D1, and D2 from being properly formed at the time of ion implantation.
  • the first conductivity type is the n-type and the second conductivity type is the p-type has been described.
  • At least one of the first deep layer 15 and the second deep layer 18 may have a defective portion D formed therein.
  • the portion that becomes the defective portion D may be increased in the path through which the hole current flows.
  • the defect portion D is to be formed in the first deep layer 15
  • the first deep layer 15 is ion-implanted or the like so that the defect portion D is formed in the first deep layer 15 . It should be formed with According to this, since holes can be trapped in areas other than the defective portion D of the JFET portion 14, it is possible to further suppress the holes from reaching the BPD.
  • the defect portion D does not have to be formed by ion implantation.
  • the defect portion D may be formed by irradiating an electron beam such as helium after forming the JFET portion 14 by epitaxial growth or the like.
  • the defect portion D may be formed by adding p-type impurities such as boron, gallium, and aluminum to increase the total amount of impurities. That is, the defect portion D may be formed at the same time as the epitaxial film is formed, instead of ion implantation or electron beam irradiation.
  • the defect portion D When forming the defect portion D by mixing p-type impurities in this way, it is preferable to adjust the total amount of n-type impurities so that the impurity concentration of the entire JFET portion 14 does not become too low. . Further, when the JFET portion 14 is formed by epitaxial growth, impurities such as vanadium, titanium, iron, etc. having a higher hole capture rate than the electron capture rate may be mixed. According to this, it is possible to further suppress the holes from being discharged from the JFET section 14 .
  • the first deep layer 15 is formed as follows. That is, the first deep layer 15 is formed by forming the JFET portion 14 entirely on the low-concentration layer 13 in the cell portion 1 and then ion-implanting predetermined portions of the JFET portion 14 . In this case, since the defect portion D is formed in the JFET portion 14 arranged entirely on the low-concentration layer 13 , the defect portion D is also formed in the first deep layer 15 . Therefore, the discharge of holes from the first deep layer 15 can also be suppressed.
  • the cell section 1 may be configured to have the same forward voltage as that of the outer peripheral section 2 during reverse conduction.
  • the JFET section 14 and the first deep layer 15 may have the same thickness. That is, the JFET section 14 may not be arranged between the first deep layer 15 and the low concentration layer 13 .
  • the impurity concentration of the JFET portion 14 and the like, the impurity concentration of the base layer 21, the width L1 of the first deep layer 15, and the like may be changed as appropriate. Even in such a SiC semiconductor device S1, since the defective portion D is formed in the JFET portion 14, expansion of the BPD to the SF can be suppressed, and an increase in the ON voltage can be suppressed.

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Abstract

The present invention is provided with: a first-conductivity-type substrate (11) formed of silicon carbide; a first-conductivity-type buffer layer (12) formed on the substrate (11); a low-concentration layer (13) formed on the buffer layer (12); a first deep layer (15) and a JFET section (14) formed on the low-concentration layer (13); a first-conductivity-type current dispersion layer (17) that is disposed on the JFET section (14) and that has a higher impurity concentration than the low-concentration layer (13); a second-conductivity-type second deep layer (18) disposed on the first deep layer (15); a second-conductivity-type base layer (21) disposed on the current dispersion layer (17) and the second deep layer (18); a first-conductivity-type impurity region (22) formed on a surface layer portion of the base layer (21); and a trench gate structure formed so as to pass through the impurity region (22) and the base layer (21) and reach the current dispersion layer (17). Also, defect sections (D) are formed in the JFET section (14).

Description

炭化珪素半導体装置およびそれを用いたインバータ回路、炭化珪素半導体装置の製造方法Silicon carbide semiconductor device, inverter circuit using the same, and method for manufacturing silicon carbide semiconductor device 関連出願への相互参照Cross-references to related applications
　本出願は、２０２１年３月２４日に出願された日本特許出願番号２０２１－０４９８７５号および２０２２年３月２２日に出願された日本特許出願番号２０２２－０４５６７６号に基づくもので、ここにその記載内容が参照により組み入れられる。 This application is based on Japanese Patent Application No. 2021-049875 filed on March 24, 2021 and Japanese Patent Application No. 2022-045676 filed on March 22, 2022, and is described herein. Content is incorporated by reference.
　本開示は、トレンチゲート構造を有する炭化珪素（以下では、単にＳｉＣともいう）半導体装置およびそれを用いたインバータ回路、ＳｉＣ半導体装置の製造方法に関するものである。 The present disclosure relates to a silicon carbide (hereinafter also simply referred to as SiC) semiconductor device having a trench gate structure, an inverter circuit using the same, and a method for manufacturing the SiC semiconductor device.
　従来より、トレンチゲート構造を有するＭＯＳＦＥＴ（metal oxide semiconductor field effect transistorの略）が形成されたＳｉＣ半導体装置が提案されている（例えば、特許文献１参照）。具体的には、このＳｉＣ半導体装置では、ｎ＋型の基板上に、基板よりも低不純物濃度とされたｎ－型のバッファ層が形成され、バッファ層上に、バッファ層よりも低不純物濃度とされた低濃度層が形成されている。そして、低濃度層上には、一方向を長手方向として延設されたｐ型の第１ディープ層と、ｎ型のＪＦＥＴ部とが形成されている。なお、第１ディープ層およびＪＦＥＴ部は、隣合う第１ディープ層の間にＪＦＥＴ部が配置されるように、第１ディープ層とＪＦＥＴ部とが長手方向と交差する方向に沿って交互に配置されている。
　第１ディープ層およびＪＦＥＴ部上には、ｎ型の電流分散層およびｐ型の第２ディープ層が配置されている。電流分散層および第２ディープ層上には、ｐ型のベース層が配置されている。なお、第２ディープ層は、第１ディープ層とベース層とを接続するように配置されている。 Conventionally, a SiC semiconductor device in which a MOSFET (abbreviation for metal oxide semiconductor field effect transistor) having a trench gate structure is formed has been proposed (see, for example, Patent Document 1). Specifically, in this SiC semiconductor device, an n − -type buffer layer having an impurity concentration lower than that of the substrate is formed on an n + -type substrate, and an impurity concentration lower than that of the buffer layer is formed on the buffer layer. A low-concentration layer is formed. A p-type first deep layer extending in one direction as a longitudinal direction and an n-type JFET portion are formed on the low-concentration layer. The first deep layers and the JFET portions are alternately arranged along the direction intersecting the longitudinal direction of the first deep layers and the JFET portions so that the JFET portions are arranged between adjacent first deep layers. It is
An n-type current spreading layer and a p-type second deep layer are disposed on the first deep layer and the JFET portion. A p-type base layer is disposed on the current spreading layer and the second deep layer. The second deep layer is arranged to connect the first deep layer and the base layer.
　ベース層の表層部には、ｎ＋型のソース領域が形成されている。そして、ソース領域およびベース層を貫通して電流分散層に達するように複数のトレンチが形成されており、各トレンチには、ゲート絶縁膜およびゲート電極が順に形成されている。これにより、トレンチゲート構造が形成されている。 An n + -type source region is formed in the surface layer portion of the base layer. A plurality of trenches are formed through the source region and the base layer to reach the current spreading layer, and a gate insulating film and a gate electrode are sequentially formed in each trench. A trench gate structure is thus formed.
特開２０１９－０１６７７５号公報JP 2019-016775 A
　ところで、上記のようなＳｉＣ半導体装置は、ベース層等と電流分散層等とのｐｎ接合によって寄生ダイオードが構成される。このため、このようなＳｉＣ半導体装置は、逆導通した際に寄生ダイオードを利用することが考えられる。 By the way, in the SiC semiconductor device as described above, a parasitic diode is formed by a pn junction between the base layer and the like and the current spreading layer and the like. Therefore, it is conceivable that such a SiC semiconductor device utilizes a parasitic diode when reverse conduction occurs.
　しかしながら、上記のようなＳｉＣ半導体装置では、基板に基底面転位（すなわち、basal plane dislocation：以下では、単にＢＰＤともいう）が存在する場合がある。そして、上記のようなＳｉＣ半導体装置では、逆導通時に注入されるホールが基底面転位に達することにより、基底面転位が積層欠陥（stacking fault：以下では、単にＳＦともいう）に拡張してしまう可能性がある。この場合、ＢＰＤは、線状欠陥であるために素子動作に及ぼす影響が小さいが、ＳＦは、面状欠陥となるために素子動作に及ぼす影響が大きくなる。したがって、上記のようなＳｉＣ半導体装置では、オン電圧が高くなる可能性がある。 However, in the SiC semiconductor device as described above, basal plane dislocations (hereinafter simply referred to as BPDs) may exist in the substrate. In the SiC semiconductor device as described above, holes injected at the time of reverse conduction reach the basal plane dislocations, causing the basal plane dislocations to expand into stacking faults (hereinafter simply referred to as SFs). there is a possibility. In this case, since BPD is a linear defect, it has little effect on the device operation, whereas SF becomes a planar defect, so it has a large effect on device operation. Therefore, the SiC semiconductor device as described above may have a high on-state voltage.
　本開示は、オン電圧が高くなることを抑制できるＳｉＣ半導体装置およびそれを用いたインバータ回路、ＳｉＣ半導体装置の製造方法を提供することを目的とする。 An object of the present disclosure is to provide a SiC semiconductor device capable of suppressing an increase in on-voltage, an inverter circuit using the SiC semiconductor device, and a method for manufacturing the SiC semiconductor device.
　本開示の１つの観点によれば、ＳｉＣ半導体装置は、スイッチング素子が形成されるセル部と、セル部を囲む外周部と、を有し、セル部は、ＳｉＣからなる第１導電型の基板と、基板上に形成され、基板よりも低不純物濃度とされた第１導電型のバッファ層と、バッファ層上に形成され、基板よりも低不純物濃度とされた第１導電型の低濃度層と、低濃度層上に形成され、基板の面方向における一方向を長手方向とする複数の線状部分を有する第２導電型の第１ディープ層と、低濃度層上に配置され、第１ディープ層に挟まれた線状部分を有する第１導電型のＪＦＥＴ部と、ＪＦＥＴ部上に配置され、低濃度層よりも高不純物濃度とされた第１導電型の電流分散層と、第１ディープ層上に配置された第２導電型の第２ディープ層と、電流分散層および第２ディープ層の上に配置された第２導電型のベース層と、ベース層の表層部に形成された第１導電型の不純物領域と、不純物領域およびベース層を貫通して電流分散層に達するトレンチの壁面に形成されたゲート絶縁膜と、ゲート絶縁膜上に形成されたゲート電極とを有するトレンチゲート構造と、不純物領域およびベース層と電気的に接続される第１電極と、基板と電気的に接続される第２電極と、を備えている。そして、ＪＦＥＴ部には、欠陥部が形成されている。 According to one aspect of the present disclosure, a SiC semiconductor device has a cell portion in which a switching element is formed and an outer peripheral portion surrounding the cell portion, and the cell portion is a substrate of a first conductivity type made of SiC. a buffer layer of the first conductivity type formed on the substrate and having an impurity concentration lower than that of the substrate; and a low concentration layer of the first conductivity type formed on the buffer layer and having an impurity concentration lower than that of the substrate. a first deep layer of a second conductivity type formed on the low-concentration layer and having a plurality of linear portions having a longitudinal direction in one direction in the surface direction of the substrate; a first conductivity type JFET portion having a linear portion sandwiched between deep layers; a first conductivity type current spreading layer disposed on the JFET portion and having an impurity concentration higher than that of the low concentration layer; a second conductive type second deep layer disposed on the deep layer; a second conductive type base layer disposed on the current spreading layer and the second deep layer; A trench gate having an impurity region of a first conductivity type, a gate insulating film formed on a wall surface of the trench penetrating the impurity region and the base layer and reaching the current spreading layer, and a gate electrode formed on the gate insulating film. A structure, a first electrode electrically connected to the impurity region and the base layer, and a second electrode electrically connected to the substrate. A defective portion is formed in the JFET portion.
　これによれば、ＳｉＣ半導体装置の逆導通時において、キャリア（例えば、ホール）が欠陥部にトラップされることでＢＰＤに到達することを抑制できる。したがって、ＢＰＤがＳＦに拡張することを抑制でき、オン電圧が高くなることを抑制できる。 According to this, when the SiC semiconductor device is in reverse conduction, it is possible to prevent carriers (for example, holes) from reaching the BPD due to being trapped in the defect. Therefore, it is possible to suppress the expansion of BPD to SF, and to suppress the on-voltage from increasing.
　本開示の別の観点によれば、ＭＯＳＦＥＴと還流ダイオードとが並列に接続されたアームを有するインバータ回路は、上記のＳｉＣ半導体装置を備え、ＭＯＳＦＥＴは、スイッチング素子で構成され、還流ダイオードは、スイッチング素子内に構成される寄生ダイオードによって構成されている。 According to another aspect of the present disclosure, an inverter circuit having an arm in which a MOSFET and a freewheeling diode are connected in parallel includes the SiC semiconductor device described above, the MOSFET is composed of a switching element, and the freewheeling diode is a switching It is composed of a parasitic diode configured within the element.
　これによれば、インバータ回路に備えられる還流ダイオードとして、ＳｉＣ半導体装置に構成される寄生ダイオードを利用している。このため、ＭＯＳＦＥＴとは別に還流ダイオードを構成する別部材を用意する必要がなく、構成の簡略化を図ることができる。 According to this, a parasitic diode configured in the SiC semiconductor device is used as the freewheeling diode provided in the inverter circuit. Therefore, there is no need to prepare a separate member that constitutes the free wheel diode separately from the MOSFET, and the configuration can be simplified.
　本開示の別の観点によれば、上記のＳｉＣ半導体装置に関する製造方法は、低濃度層をエピタキシャル層で配置することと、低濃度層の表層部にイオン注入を行うことでＪＦＥＴ部を構成することを行い、イオン注入を行うことでＪＦＥＴ部に欠陥部を形成する。 According to another aspect of the present disclosure, the above-described manufacturing method for a SiC semiconductor device configures the JFET section by arranging the low-concentration layer as an epitaxial layer and performing ion implantation on the surface layer of the low-concentration layer. Then, ion implantation is performed to form a defective portion in the JFET portion.
　これによれば、逆導通時にキャリア（例えば、ホール）をトラップする欠陥部が形成されたＳｉＣ半導体装置を容易に製造できる。 According to this, it is possible to easily manufacture a SiC semiconductor device having a defective portion that traps carriers (for example, holes) during reverse conduction.
　なお、各構成要素等に付された括弧付きの参照符号は、その構成要素等と後述する実施形態に記載の具体的な構成要素等との対応関係の一例を示すものである。 It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific component etc. described in the embodiment described later.
第１実施形態におけるＳｉＣ半導体装置の断面図である。1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment; FIG. 図１中のセル部を示す斜視図である。FIG. 2 is a perspective view showing a cell portion in FIG. 1; 図１に示すＳｉＣ半導体装置を用いて構成したインバータ回路を示す図である。2 is a diagram showing an inverter circuit configured using the SiC semiconductor device shown in FIG. 1; FIG. ＳｉＣ半導体装置が逆導通時である際の順方向電圧と電流密度との関係を示す図である。FIG. 4 is a diagram showing the relationship between forward voltage and current density when the SiC semiconductor device is in reverse conduction; 順方向電流とＳＦ面積占有率との関係を示す図である。It is a figure which shows the relationship between a forward current and an SF area occupation ratio. ＪＦＥＴ部の不純物濃度とＳＦ面積占有率との関係を示す図である。FIG. 4 is a diagram showing the relationship between the impurity concentration of the JFET portion and the SF area occupation ratio; チャネル長とＳＦ面積占有率との関係を示す図である。It is a figure which shows the relationship between channel length and SF area occupation ratio. ベース層の不純物濃度とＳＦ面積占有率との関係を示す図である。It is a figure which shows the relationship between the impurity concentration of a base layer, and an SF area occupation ratio. 第１ディープ層の幅とホール電流密度との関係を示す図である。FIG. 4 is a diagram showing the relationship between the width of the first deep layer and the hole current density; トレンチの間隔とホール電流密度との関係を示す図である。FIG. 4 is a diagram showing the relationship between trench spacing and hole current density; 第１ディープ層の間隔とオン電圧との関係を示す図である。FIG. 4 is a diagram showing the relationship between the interval of the first deep layer and the ON voltage; 第１ディープ層の間隔とゲート絶縁膜に印加される電界との関係を示す図である。FIG. 4 is a diagram showing the relationship between the interval of the first deep layer and the electric field applied to the gate insulating film; 第１ディープ層の間隔と帰還容量との関係を示す図である。FIG. 4 is a diagram showing the relationship between the spacing of the first deep layer and the feedback capacitance; 第２実施形態におけるＳｉＣ半導体装置のセル部を示す斜視図である。It is a perspective view showing a cell portion of the SiC semiconductor device in the second embodiment. 第３実施形態におけるＳｉＣ半導体装置のセル部を示す斜視図である。FIG. 11 is a perspective view showing a cell portion of a SiC semiconductor device according to a third embodiment; 深さとｐ型の不純物濃度との関係を示す図である。It is a figure which shows the relationship between the depth and the impurity concentration of a p-type. 第３実施形態におけるＳｉＣ半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the SiC semiconductor device in 3rd Embodiment. 図１７Ａに続くＳｉＣ半導体装置の製造工程を示す断面図である。17B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 17A; FIG.
　以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。 Hereinafter, embodiments of the present disclosure will be described based on the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.
　（第１実施形態）
　第１実施形態について、図１および図２を参照しつつ説明する。本実施形態のＳｉＣ半導体装置Ｓ１は、スイッチング素子として、トレンチゲート構造の反転型のＭＯＳＦＥＴが形成されている。 (First embodiment)
A first embodiment will be described with reference to FIGS. 1 and 2. FIG. In the SiC semiconductor device S1 of the present embodiment, an inverted MOSFET having a trench gate structure is formed as a switching element.
　ＳｉＣ半導体装置Ｓ１は、トレンチゲート構造のＭＯＳＦＥＴが形成されるセル部１と、このセル部１を囲む外周部２とを有する構成とされている。外周部２は、ガードリング部２ａと、ガードリング２ａ部よりも内側に配置される繋ぎ部２ｂとを有する構成とされている。言い換えると、外周部２は、ガードリング部２ａと、セル部１とガードリング部２ａとの間に配置される繋ぎ部２ｂとを有する構成とされている。以下では、後述する基板１１の面方向における一方向をＸ軸方向とし、基板の面方向における一方向と交差する方向をＹ軸方向とし、Ｘ軸方向およびＹ軸方向と直交する方向をＺ軸方向として説明する。なお、本実施形態では、Ｘ軸方向とＹ軸方向とは直交している。また、図１では、紙面左右方向がＸ軸方向に相当し、紙面奥行き方向がＹ軸方向に相当し、紙面上下方向がＺ軸方向に相当している。 The SiC semiconductor device S1 has a cell portion 1 in which a MOSFET having a trench gate structure is formed, and an outer peripheral portion 2 surrounding the cell portion 1 . The outer peripheral portion 2 has a guard ring portion 2a and a connecting portion 2b arranged inside the guard ring portion 2a. In other words, the outer peripheral portion 2 has a guard ring portion 2a and a connecting portion 2b arranged between the cell portion 1 and the guard ring portion 2a. Hereinafter, one direction in the surface direction of the substrate 11 to be described later is defined as the X-axis direction, a direction intersecting one direction in the surface direction of the substrate is defined as the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. described as a direction. In addition, in this embodiment, the X-axis direction and the Y-axis direction are orthogonal. In addition, in FIG. 1, the horizontal direction on the page corresponds to the X-axis direction, the depth direction on the page corresponds to the Y-axis direction, and the vertical direction on the page corresponds to the Z-axis direction.
　ＳｉＣ半導体装置Ｓ１は、半導体基板１０を用いて構成されている。具体的には、ＳｉＣ半導体装置Ｓ１は、ＳｉＣからなるｎ＋型の基板１１を備えている。本実施形態では、基板１１として、例えば、（０００１）Ｓｉ面に対して０～８°のオフ角を有し、窒素やリン等のｎ型不純物濃度が１．０×１０１９／ｃｍ３とされ、厚さが３００μｍ程度とされたものが用いられる。なお、基板１１は、本実施形態ではドレイン領域を構成するものである。 SiC semiconductor device S1 is configured using semiconductor substrate 10 . Specifically, the SiC semiconductor device S1 includes an n + -type substrate 11 made of SiC. In this embodiment, the substrate 11 has, for example, an off angle of 0 to 8° with respect to the (0001) Si plane, and the concentration of n-type impurities such as nitrogen and phosphorus is 1.0×10 19 /cm 3 . and a thickness of about 300 μm is used. The substrate 11 constitutes a drain region in this embodiment.
　基板１１の表面上には、ＳｉＣからなるｎ－型のバッファ層１２が形成されている。バッファ層１２は、基板１１の表面にエピタキシャル成長を行うことによって構成される。そして、バッファ層１２は、ｎ型不純物濃度が、基板１１と、後述する低濃度層１３との間の不純物濃度とされ、厚さが１μｍ程度とされている。 An n − -type buffer layer 12 made of SiC is formed on the surface of the substrate 11 . The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11 . The buffer layer 12 has an n-type impurity concentration between the substrate 11 and the low-concentration layer 13 described later, and has a thickness of about 1 μm.
　バッファ層１２の表面上には、例えば、ｎ型不純物濃度が５．０～１０．０×１０１５／ｃｍ３とされ、厚さが１０～１５μｍ程度とされたＳｉＣからなるｎ－型の低濃度層１３が形成されている。この低濃度層１３は、不純物濃度がＺ軸方向において一定とされていてもよいが、濃度分布に傾斜が付けられ、低濃度層１３のうちの基板１１側の方が基板１１から離れる側よりも高濃度となるようにされると好ましい。例えば、低濃度層１３は、基板１１の表面から３～５μｍ程度の部分の不純物濃度が２．０×１０１５／ｃｍ３程度他の部分よりも高くされるのが好ましい。このような構成にすることにより、低濃度層１３の内部抵抗を低減でき、オン抵抗を低減することができる。また、低濃度層１３は、エピタキシャル成長によるエピタキシャル層で構成される。 On the surface of the buffer layer 12, for example, an n.sup.--type silicon nitride film made of SiC having an n - type impurity concentration of 5.0 to 10.0.times.10.sup.15/ cm.sup.3 and a thickness of about 10 to 15 .mu.m is formed. A density layer 13 is formed. The impurity concentration of the low-concentration layer 13 may be constant in the Z-axis direction, but the concentration distribution is inclined so that the low-concentration layer 13 on the substrate 11 side is closer to the substrate 11 than on the side away from the substrate 11 . It is also preferred that the concentration is also high. For example, the low-concentration layer 13 preferably has an impurity concentration of about 2.0×10 15 /cm 3 in a portion about 3 to 5 μm from the surface of the substrate 11 higher than that in other portions. With such a configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced. Also, the low-concentration layer 13 is composed of an epitaxial layer formed by epitaxial growth.
　低濃度層１３の表層部には、セル部１および外周部２の繋ぎ部２ｂにおいて、ＪＦＥＴ部１４および第１ディープ層１５が形成されている。本実施形態では、ＪＦＥＴ部１４および第１ディープ層１５は、それぞれＸ軸方向に沿って延設されると共に、Ｙ軸方向において交互に繰り返し並べて配置された線状部分を有している。つまり、ＪＦＥＴ部１４および第１ディープ層１５は、基板１１の表面に対する法線方向（以下では、単に法線方向ともいう）において、それぞれＸ軸方向に沿って延設されたストライプ状とされ、それらがＹ軸方向に沿って交互に並べられたレイアウトとなる構成とされている。なお、基板１１の表面に対する法線方向においてとは、言い換えると、基板１１の表面に対する法線方向から視たときということもできる。 A JFET portion 14 and a first deep layer 15 are formed in the surface layer portion of the low-concentration layer 13 at the connecting portion 2 b between the cell portion 1 and the outer peripheral portion 2 . In the present embodiment, the JFET portion 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions alternately and repeatedly arranged in the Y-axis direction. In other words, the JFET portion 14 and the first deep layer 15 each have a stripe shape extending along the X-axis direction in the direction normal to the surface of the substrate 11 (hereinafter also simply referred to as the normal direction). The layout is such that they are alternately arranged along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, in other words, when viewed from the normal direction to the surface of the substrate 11. FIG.
　ＪＦＥＴ部１４は、低濃度層１３よりも高不純物濃度とされたｎ型とされており、深さが０．３～１．５μｍとされている。本実施形態では、ＪＦＥＴ部１４は、ｎ型不純物濃度が７．０×１０１６～５．０×１０１７／ｃｍ３とされている。また、本実施形態のＪＦＥＴ部１４は、低濃度層１３に対してｎ型不純物をイオン注入することによって形成されたイオン注入層とされており、イオン注入することで構成される欠陥部Ｄが形成されている。 The JFET portion 14 is of n-type with a higher impurity concentration than the low-concentration layer 13 and has a depth of 0.3 to 1.5 μm. In this embodiment, the JFET portion 14 has an n-type impurity concentration of 7.0×10 16 to 5.0×10 17 /cm 3 . Further, the JFET portion 14 of the present embodiment is an ion-implanted layer formed by ion-implanting n-type impurities into the low-concentration layer 13, and the defect portion D formed by ion-implanting is formed.
　第１ディープ層１５は、例えば、ボロン等のｐ型不純物濃度が２．０×１０１７～２．０×１０１８／ｃｍ３とされている。なお、本実施形態の第１ディープ層１５は、ＪＦＥＴ部１４よりもガードリング部２ａ側まで延設されている。 The first deep layer 15 has, for example, a p-type impurity concentration such as boron of 2.0×10 17 to 2.0×10 18 /cm 3 . The first deep layer 15 of this embodiment extends from the JFET section 14 to the side of the guard ring section 2a.
　そして、本実施形態の第１ディープ層１５は、ＪＦＥＴ部１４より浅く形成されている。つまり、第１ディープ層１５は、底部がＪＦＥＴ部１４内に位置するように形成されている。言い換えると、第１ディープ層１５は、低濃度層１３との間にＪＦＥＴ部１４が位置するように形成されている。 The first deep layer 15 of this embodiment is formed shallower than the JFET section 14 . In other words, the first deep layer 15 is formed so that the bottom is positioned inside the JFET section 14 . In other words, the first deep layer 15 is formed so that the JFET portion 14 is positioned between the low-concentration layer 13 and the first deep layer 15 .
　また、本実施形態の第１ディープ層１５は、幅Ｌ１が０．９μｍ以下とされている。なお、第１ディープ層１５の幅Ｌ１とは、第１ディープ層１５の長手方向と直交する方向の長さであって、半導体基板１０の面方向に沿った方向の長さである。すなわち、第１ディープ層１５の幅Ｌ１とは、第１ディープ層１５のＹ軸方向に沿った長さのことである。 Further, the width L1 of the first deep layer 15 of this embodiment is 0.9 μm or less. The width L1 of the first deep layer 15 is the length in the direction perpendicular to the longitudinal direction of the first deep layer 15 and the length in the plane direction of the semiconductor substrate 10 . That is, the width L1 of the first deep layer 15 is the length of the first deep layer 15 along the Y-axis direction.
　さらに、第１ディープ層１５は、隣合う第１ディープ層１５の間隔Ｌ２が０．７５～１．１μｍとされている。なお、隣合う第１ディープ層１５の間隔Ｌ２とは、ＪＦＥＴ部１４のうちの第１ディープ層１５で挟まれる部分のＹ軸方向に沿った長さのことである。 Furthermore, in the first deep layers 15, the interval L2 between adjacent first deep layers 15 is 0.75 to 1.1 μm. The interval L2 between adjacent first deep layers 15 is the length along the Y-axis direction of the portion sandwiched between the first deep layers 15 in the JFET section 14 .
　また、低濃度層１３の表層部には、外周部２のガードリング部２ａにおいて、セル部１を囲むように、複数本のｐ型のガードリング１６が備えられている。本実施形態では、ガードリング１６の上面レイアウトは、法線方向において、四隅が丸められた四角形状や円形状等とされている。 In addition, a plurality of p-type guard rings 16 are provided on the surface layer of the low-concentration layer 13 so as to surround the cell section 1 in the guard ring section 2 a of the outer peripheral section 2 . In the present embodiment, the upper surface layout of the guard ring 16 is in the shape of a rectangle with rounded corners, a circle, or the like in the normal direction.
　セル部１におけるＪＦＥＴ部１４および第１ディープ層１５上には、電流分散層１７および第２ディープ層１８が形成されている。 A current spreading layer 17 and a second deep layer 18 are formed on the JFET section 14 and the first deep layer 15 in the cell section 1 .
　電流分散層１７は、ｎ型不純物層で構成され、厚さが０．５～２μｍとされている。また、電流分散層１７のｎ型不純物濃度は、例えば、１．０×１０１６～５．０×１０１７／ｃｍ３とされている。また、電流分散層１７は、ＪＦＥＴ部１４と繋がっている。このため、本実施形態では、低濃度層１３、ＪＦＥＴ部１４、および電流分散層１７が繋がり、これらによってドリフト層１９が構成されている。 The current spreading layer 17 is composed of an n-type impurity layer and has a thickness of 0.5 to 2 μm. Further, the n-type impurity concentration of the current spreading layer 17 is, for example, 1.0×10 16 to 5.0×10 17 /cm 3 . Also, the current spreading layer 17 is connected to the JFET section 14 . Therefore, in the present embodiment, the low-concentration layer 13, the JFET section 14, and the current spreading layer 17 are connected, and the drift layer 19 is configured by these.
　第２ディープ層１８は、セル部１に形成されており、例えば、ｐ型不純物濃度が２．０×１０１７～２．０×１０１８／ｃｍ３とされており、厚さが電流分散層１７と等しくされている。また、第２ディープ層１８は、第１ディープ層１５と接続されるように形成されている。 The second deep layer 18 is formed in the cell section 1, and has a p-type impurity concentration of, for example, 2.0×10 17 to 2.0×10 18 /cm 3 and a thickness equal to that of the current spreading layer. 17. Also, the second deep layer 18 is formed so as to be connected to the first deep layer 15 .
　電流分散層１７および第２ディープ層１８は、ＪＦＥＴ部１４のうちのストライプ状とされた部分や、第１ディープ層１５の長手方向に対して交差する方向に延設されている。本実施形態では、電流分散層１７および第２ディープ層１８は、Ｙ軸方向を長手方向として延設されると共に、Ｘ軸方向において交互に複数本並べたレイアウトとされている。なお、電流分散層１７および第２ディープ層１８の形成ピッチは、後述するトレンチゲート構造の形成ピッチに合わせてあり、第２ディープ層１８は、後述するトレンチ２４を挟むように形成されている。 The current spreading layer 17 and the second deep layer 18 extend in a direction crossing the striped portion of the JFET section 14 and the longitudinal direction of the first deep layer 15 . In the present embodiment, the current spreading layers 17 and the second deep layers 18 are laid out with the Y-axis direction as the longitudinal direction and arranged alternately in the X-axis direction. The formation pitch of the current spreading layer 17 and the second deep layer 18 is matched with the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed so as to sandwich the trench 24 described later.
　また、外周部２における低濃度層１３、ＪＦＥＴ部１４、第１ディープ層１５、ガードリング１６上には、電流分散層１７およびリサーフ層２０が形成されている。リサーフ層２０は、外周部２のうちの繋ぎ部２ｂに形成されており、第１ディープ層１５と接続されるように形成されている。 A current spreading layer 17 and a resurf layer 20 are formed on the low-concentration layer 13 , JFET section 14 , first deep layer 15 , and guard ring 16 in the outer peripheral portion 2 . The resurf layer 20 is formed in the connecting portion 2 b of the outer peripheral portion 2 and is formed so as to be connected to the first deep layer 15 .
　電流分散層１７、第２ディープ層１８、リサーフ層２０上には、Ｐ型のベース層２１が形成されている。そして、セル部１におけるベース層２１の表層部には、ｎ＋型のソース領域２２およびｐ＋型のコンタクト領域２３が形成されている。ソース領域２２は、後述するトレンチ２４の側面に接するように形成され、コンタクト領域２３は、ソース領域２２を挟んでトレンチ２４と反対側に形成されている。なお、本実施形態では、ソース領域２２が不純物領域に相当している。 A P-type base layer 21 is formed on the current spreading layer 17 , the second deep layer 18 , and the RESURF layer 20 . An n + -type source region 22 and a p + -type contact region 23 are formed in the surface layer portion of the base layer 21 in the cell portion 1 . The source region 22 is formed in contact with the side surface of a trench 24 to be described later, and the contact region 23 is formed on the opposite side of the trench 24 with the source region 22 interposed therebetween. Incidentally, in this embodiment, the source region 22 corresponds to the impurity region.
　ベース層２１は、例えば、ｐ型不純物濃度が３．０×１０１７／ｃｍ３以下とされている。また、本実施形態のベース層２１は、例えば、イオン注入等で形成され、セル部１の方が外周部２よりも不純物濃度が高くなっている。ソース領域２２は、表層部におけるｎ型不純物濃度、すなわち表面濃度が例えば１．０×１０２１／ｃｍ３とされている。コンタクト領域２３は、表層部におけるｐ型不純物濃度、すなわち表面濃度が例えば１．０×１０２１／ｃｍ３とされている。 The base layer 21 has, for example, a p-type impurity concentration of 3.0×10 17 /cm 3 or less. Also, the base layer 21 of the present embodiment is formed by, for example, ion implantation, and the impurity concentration in the cell section 1 is higher than that in the outer peripheral section 2 . The source region 22 has an n-type impurity concentration in the surface layer, ie, a surface concentration of 1.0×10 21 /cm 3 , for example. The contact region 23 has a p-type impurity concentration in the surface layer, ie, a surface concentration of 1.0×10 21 /cm 3 , for example.
　また、ベース層２１およびソース領域２２は、チャネル長が０．４μｍ以下となるように、厚さが調整されている。なお、ここでのチャネル長とは、Ｚ軸方向（すなわち、基板１１とバッファ層１２との積層方向）において、ベース層２１のうちのトレンチ２４の側面に沿った部分の長さのことである。言い換えると、チャネル長とは、ベース層２１のうちのソース領域２２と電流分散層１７との間の長さのことである。 The thickness of the base layer 21 and the source region 22 are adjusted so that the channel length is 0.4 μm or less. Here, the channel length is the length of the portion of the base layer 21 along the side surface of the trench 24 in the Z-axis direction (that is, the stacking direction of the substrate 11 and the buffer layer 12). . In other words, the channel length is the length between the source region 22 of the base layer 21 and the current spreading layer 17 .
　本実施形態では、このように、基板１１、バッファ層１２、低濃度層１３、ＪＦＥＴ部１４、第１ディープ層１５、電流分散層１７、第２ディープ層１８、ベース層２１、ソース領域２２、コンタクト領域２３等が積層されて半導体基板１０が構成されている。以下、半導体基板１０のうちの基板１１側の面を半導体基板１０の他面１０ｂとし、ソース領域２２およびコンタクト領域２３側の面を半導体基板１０の一面１０ａとする。そして、ソース領域２２およびコンタクト領域２３は、半導体基板１０の一面１０ａから露出した状態となっている。 In this embodiment, the substrate 11, the buffer layer 12, the low concentration layer 13, the JFET section 14, the first deep layer 15, the current spreading layer 17, the second deep layer 18, the base layer 21, the source region 22, The semiconductor substrate 10 is configured by stacking the contact regions 23 and the like. Hereinafter, the surface of the semiconductor substrate 10 facing the substrate 11 is referred to as the other surface 10b of the semiconductor substrate 10, and the surface facing the source region 22 and the contact region 23 is referred to as one surface 10a of the semiconductor substrate 10. FIG. Source region 22 and contact region 23 are exposed from one surface 10 a of semiconductor substrate 10 .
　半導体基板１０には、セル部１において、ベース層２１等を貫通して電流分散層１７に達すると共に、底面が電流分散層１７内に位置するように、例えば幅が１．４～２．０μｍとされたトレンチ２４が形成されている。なお、トレンチ２４は、ＪＦＥＴ部１４および第１ディープ層１５に達しないように形成されている。つまり、トレンチ２４は、底面よりも下方にＪＦＥＴ部１４および第１ディープ層１５が位置するように形成されている。 In the cell section 1, the semiconductor substrate 10 has a width of, for example, 1.4 to 2.0 μm so that it reaches the current spreading layer 17 through the base layer 21 and the like, and the bottom surface is located in the current spreading layer 17. and a trench 24 is formed. Note that the trench 24 is formed so as not to reach the JFET portion 14 and the first deep layer 15 . That is, the trench 24 is formed so that the JFET portion 14 and the first deep layer 15 are located below the bottom surface.
　また、トレンチ２４は、Ｙ軸方向に沿って延びるように複数本が延設されていると共に、Ｘ軸方向に等間隔で並べられてストライプ状に形成されている。つまり、本実施形態では、トレンチ２４は、長手方向が第１ディープ層１５の長手方向と直交するように形成されている。また、トレンチ２４は、法線方向において、第２ディープ層１８に挟まれるように形成されている。そして、本実施形態のトレンチ２４は、隣合うトレンチ２４の中心間の距離（すなわち、トレンチピッチ）が３．０μｍ以下となるように形成されている。 A plurality of trenches 24 extend along the Y-axis direction, and are arranged in stripes at equal intervals in the X-axis direction. That is, in this embodiment, the trench 24 is formed so that its longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15 . Also, the trench 24 is formed so as to be sandwiched between the second deep layers 18 in the normal direction. The trenches 24 of the present embodiment are formed such that the distance between the centers of adjacent trenches 24 (that is, the trench pitch) is 3.0 μm or less.
　トレンチ２４は、内壁面に形成されたゲート絶縁膜２５と、ゲート絶縁膜２５の表面に形成されたドープトＰｏｌｙ－Ｓｉによって構成されるゲート電極２６によって埋め込まれている。これにより、トレンチゲート構造が構成されている。特に限定されるものではないが、ゲート絶縁膜２５は、トレンチ２４の内壁面を熱酸化またはＣＶＤ（chemical vapor depositionの略）で形成される。そして、ゲート絶縁膜２５は、厚さがトレンチ２４の側面側および底面側で共に１００ｎｍ程度とされている。 The trench 24 is filled with a gate insulating film 25 formed on the inner wall surface and a gate electrode 26 made of doped Poly-Si formed on the surface of the gate insulating film 25 . A trench gate structure is thus formed. Although not particularly limited, the gate insulating film 25 is formed on the inner wall surface of the trench 24 by thermal oxidation or CVD (abbreviation for chemical vapor deposition). The gate insulating film 25 has a thickness of about 100 nm on both the side and bottom sides of the trench 24 .
　なお、ゲート絶縁膜２５は、トレンチ２４の内壁面以外の表面にも形成されている。具体的には、ゲート絶縁膜２５は、半導体基板１０の一面１０ａの一部も覆うように形成されている。より詳しくは、ゲート絶縁膜２５は、ソース領域２２の表面の一部も覆うように形成されている。言い換えると、ゲート絶縁膜２５には、ゲート電極２６が配置される部分と異なる部分において、コンタクト領域２３およびソース領域２２の残部を露出させるコンタクトホール２５ａが形成されている。 The gate insulating film 25 is also formed on surfaces other than the inner wall surface of the trench 24 . Specifically, the gate insulating film 25 is formed so as to also partially cover the one surface 10 a of the semiconductor substrate 10 . More specifically, the gate insulating film 25 is formed so as to also partially cover the surface of the source region 22 . In other words, in the gate insulating film 25, a contact hole 25a exposing the remaining portions of the contact region 23 and the source region 22 is formed in a portion different from the portion where the gate electrode 26 is arranged.
　また、ゲート絶縁膜２５は、繋ぎ部２ｂにおけるベース層２１の表面にも形成されている。ゲート電極２６についても、ゲート絶縁膜２５と同様に、繋ぎ部２ｂにおけるゲート絶縁膜２５の表面上まで延設されている。以上のようにして、本実施形態のトレンチゲート構造が構成されている。 The gate insulating film 25 is also formed on the surface of the base layer 21 in the connecting portion 2b. Similarly to the gate insulating film 25, the gate electrode 26 also extends to the surface of the gate insulating film 25 at the connecting portion 2b. The trench gate structure of the present embodiment is constructed as described above.
　また、半導体基板１０には、外周部２のうちのガードリング部２ａにおいて、ベース層２１を貫通してリサーフ層２０および電流分散層１７に達するように凹部１０ｃが形成されている。本実施形態のＳｉＣ半導体装置Ｓ１は、このような構造とされたメサ構造が形成されている。そして、繋ぎ部２ｂには、セル部１と同様に、ベース層２１の表層部にコンタクト領域２３が形成されている。 Also, in the semiconductor substrate 10 , a concave portion 10 c is formed in the guard ring portion 2 a of the outer peripheral portion 2 so as to penetrate the base layer 21 and reach the resurf layer 20 and the current spreading layer 17 . In the SiC semiconductor device S1 of the present embodiment, such a mesa structure is formed. A contact region 23 is formed in the surface layer portion of the base layer 21 in the connecting portion 2b, as in the cell portion 1. As shown in FIG.
　半導体基板１０の一面１０ａ上には、ゲート電極２６やゲート絶縁膜２５等を覆うように、層間絶縁膜２７が形成されている。層間絶縁膜２７は、ＢＰＳＧ（Borophosphosilicate Glassの略）等で構成されている。 An interlayer insulating film 27 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 26, the gate insulating film 25, and the like. The interlayer insulating film 27 is made of BPSG (abbreviation for Borophosphosilicate Glass) or the like.
　層間絶縁膜２７には、コンタクトホール２５ａと連通してソース領域２２およびコンタクト領域２３を露出させるコンタクトホール２７ａが形成されている。また、層間絶縁膜２７には、ゲート電極２６のうちの繋ぎ部２ｂまで延設された部分を露出させるコンタクトホール２７ｂが形成されている。つまり、層間絶縁膜２７には、セル部１にコンタクトホール２７ａが形成され、外周部２にコンタクトホール２７ｂが形成されている。 A contact hole 27a is formed in the interlayer insulating film 27 to communicate with the contact hole 25a and expose the source region 22 and the contact region 23 . A contact hole 27b is formed in the interlayer insulating film 27 to expose a portion of the gate electrode 26 extending to the connecting portion 2b. That is, the interlayer insulating film 27 has a contact hole 27 a formed in the cell portion 1 and a contact hole 27 b formed in the outer peripheral portion 2 .
　なお、層間絶縁膜２７に形成されたコンタクトホール２７ａは、ゲート絶縁膜２５に形成されたコンタクトホール２５ａと連通するように形成されており、当該コンタクトホール２５ａと共に１つのコンタクトホールとして機能する。このため、以下では、コンタクトホール２５ａおよびコンタクトホール２７ａを纏めてコンタクトホール２５ｂともいう。そして、コンタクトホール２５ｂのパターンは、任意であり、例えば複数の正方形のものを配列させたパターン、長方形のライン状のものを配列させたパターン、または、ライン状のものを並べたパターン等が挙げられる。本実施形態では、コンタクトホール２５ｂは、トレンチ２４の長手方向に沿ったライン状とされている。 The contact hole 27a formed in the interlayer insulating film 27 is formed so as to communicate with the contact hole 25a formed in the gate insulating film 25, and functions together with the contact hole 25a as one contact hole. Therefore, hereinafter, the contact hole 25a and the contact hole 27a are collectively referred to as the contact hole 25b. The pattern of the contact holes 25b is arbitrary, and examples thereof include a pattern in which a plurality of square holes are arranged, a pattern in which rectangular linear holes are arranged, a pattern in which linear holes are arranged, and the like. be done. In this embodiment, the contact hole 25b is linear along the longitudinal direction of the trench 24 .
　層間絶縁膜２７上には、コンタクトホール２５ｂを通じてソース領域２２およびコンタクト領域２３と電気的に接続されるソース電極２８が形成されている。なお、本実施形態のソース電極２８は、外周部２のベース層２１に形成されたコンタクト領域２３とも接続されている。また、層間絶縁膜２７上には、コンタクトホール２７ｂを通じてゲート電極２６と電気的に接続されるゲート配線２９が形成されている。なお、本実施形態では、ソース電極２８が第１電極に相当している。 A source electrode 28 electrically connected to the source region 22 and the contact region 23 through the contact hole 25b is formed on the interlayer insulating film 27. As shown in FIG. The source electrode 28 of this embodiment is also connected to the contact region 23 formed in the base layer 21 of the outer peripheral portion 2 . A gate wiring 29 electrically connected to the gate electrode 26 through a contact hole 27b is formed on the interlayer insulating film 27. As shown in FIG. Incidentally, in this embodiment, the source electrode 28 corresponds to the first electrode.
　本実施形態のソース電極２８は、例えば、Ｎｉ／Ａｌ等の複数の金属にて構成されている。そして、複数の金属のうちのｎ型ＳｉＣ（すなわち、ソース領域２２）を構成する部分と接触する部分は、ｎ型ＳｉＣとオーミック接触可能な金属で構成されている。また、複数の金属のうちの少なくともｐ型ＳｉＣ（すなわち、コンタクト領域２３）と接触する部分は、ｐ型ＳｉＣとオーミック接触可能な金属で構成されている。なお、ゲート配線２９は、ソース電極と同様の構成とされていてもよいし、Ａｌ－Ｓｉ等で構成されていてもよい。 The source electrode 28 of this embodiment is composed of a plurality of metals such as Ni/Al, for example. A portion of the plurality of metals, which is in contact with the portion forming the n-type SiC (that is, the source region 22), is made of a metal capable of making ohmic contact with the n-type SiC. At least the portion of the plurality of metals that contacts p-type SiC (that is, contact region 23) is made of a metal capable of making ohmic contact with p-type SiC. The gate wiring 29 may have the same structure as the source electrode, or may be made of Al--Si or the like.
　さらに、繋ぎ部２ｂおよびガードリング部２ａを覆うように、ポリイミド等によって構成される保護膜３０が形成されている。本実施形態では、保護膜３０は、ソース電極２８と後述するドレイン電極３１との間で沿面放電が発生することを抑制するため、外周部２からセル部１の外縁部上まで形成されている。具体的には、保護膜３０は、セル部１において、ソース電極２８のうちの外周部２側の部分を覆いつつ、ソース電極２８のうちの内縁側の部分を露出させるように形成されている。 Furthermore, a protective film 30 made of polyimide or the like is formed so as to cover the connecting portion 2b and the guard ring portion 2a. In this embodiment, the protective film 30 is formed from the outer peripheral portion 2 to the outer edge portion of the cell portion 1 in order to suppress creeping discharge from occurring between the source electrode 28 and the drain electrode 31, which will be described later. . Specifically, in the cell section 1, the protective film 30 is formed so as to cover the portion of the source electrode 28 on the side of the outer peripheral portion 2 while exposing the portion of the source electrode 28 on the inner edge side. .
　半導体基板１０の他面１０ｂ側には、基板１１と電気的に接続されるドレイン電極３１が形成されている。なお、本実施形態では、ドレイン電極３１が第２電極に相当している。本実施形態のＳｉＣ半導体装置Ｓ１では、このような構造により、ｎチャネルタイプの反転型であるトレンチゲート構造のＭＯＳＦＥＴが構成されている。また、本実施形態のＳｉＣ半導体装置Ｓ１では、このような構造により、ドリフト層１９とベース層２１等とのｐｎ接合によって寄生ダイオードが構成される。 A drain electrode 31 electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10 . In addition, in this embodiment, the drain electrode 31 corresponds to the second electrode. In the SiC semiconductor device S1 of the present embodiment, such a structure constitutes a MOSFET having a trench gate structure, which is an n-channel type inversion type. In addition, in the SiC semiconductor device S1 of the present embodiment, with such a structure, a parasitic diode is formed by a pn junction between the drift layer 19 and the base layer 21 and the like.
　以上が本実施形態におけるＳｉＣ半導体装置Ｓ１の構成である。なお、本実施形態では、ｎ＋型、ｎ型、ｎ－型が第１導電型に相当しており、ｐ－型、ｐ型、ｐ＋型が第２導電型に相当している。次に、上記ＳｉＣ半導体装置Ｓ１の作動および効果について説明する。 The above is the configuration of the SiC semiconductor device S1 in this embodiment. In this embodiment, n + type, n type, and n − type correspond to the first conductivity type, and p − type, p type, and p + type correspond to the second conductivity type. Next, the operation and effects of the SiC semiconductor device S1 will be described.
　上記ＳｉＣ半導体装置Ｓ１は、例えば、図３に示されるようなインバータ回路１００を構成するのに用いられる。インバータ回路１００は、例えば、三相モータ１０１の駆動等に用いられ、直流電源１０２を用いて三相モータ１０１に対して交流電流を供給する際に用いられる。 The SiC semiconductor device S1 is used, for example, to configure an inverter circuit 100 as shown in FIG. The inverter circuit 100 is used, for example, to drive a three-phase motor 101 and is used to supply an alternating current to the three-phase motor 101 using a DC power supply 102 .
　具体的には、インバータ回路１００は、直流電源１０２に対して上アームと下アームを直列接続したブリッジ回路を複数個並列接続し、各ブリッジ回路の上アームと下アームを交互に繰り返しオンオフさせることで、負荷に対して交流電流を供給する。インバータ回路１００は、ＭＯＳＦＥＴＳ１１に対して還流ダイオードＳ１２が並列接続されることで構成される。そして、本実施形態のＳｉＣ半導体装置Ｓ１を用いてインバータ回路１００を構成する場合、各相の上アームと下アームのそれぞれが上記ＳｉＣ半導体装置Ｓ１で構成される。さらに詳しくは、ＳｉＣ半導体装置Ｓ１のＭＯＳＦＥＴによって各アームのＭＯＳＦＥＴＳ１１が構成され、ＳｉＣ半導体装置Ｓ１の寄生ダイオードによって各アームの還流ダイオードＳ１２が構成される。 Specifically, the inverter circuit 100 connects in parallel a plurality of bridge circuits in which the upper arm and the lower arm are connected in series to the DC power supply 102, and the upper arm and the lower arm of each bridge circuit are alternately turned on and off repeatedly. to supply alternating current to the load. The inverter circuit 100 is configured by connecting a freewheeling diode S12 in parallel to the MOSFET S11. When the inverter circuit 100 is configured using the SiC semiconductor device S1 of the present embodiment, each of the upper arm and the lower arm of each phase is configured with the SiC semiconductor device S1. More specifically, the MOSFET of the SiC semiconductor device S1 constitutes the MOSFET S11 of each arm, and the parasitic diode of the SiC semiconductor device S1 constitutes the free wheel diode S12 of each arm.
　そして、このようなインバータ回路１００の各ブリッジ回路では、上アームのＭＯＳＦＥＴＳ１１をオン、下アームのＭＯＳＦＥＴＳ１１をオフすることで負荷に対して電流供給を行う。また、その後に、上アームのＭＯＳＦＥＴＳ１１をオフ、下アームのＭＯＳＦＥＴＳ１１をオンすることで電流供給を停止する。 In each bridge circuit of the inverter circuit 100, current is supplied to the load by turning on the MOSFET S11 of the upper arm and turning off the MOSFET S11 of the lower arm. Further, after that, the current supply is stopped by turning off the MOSFET S11 of the upper arm and turning on the MOSFET S11 of the lower arm.
　この際、例えば、上アームのＳｉＣ半導体装置Ｓ１の作動は次のようになる。すなわち、このＳｉＣ半導体装置Ｓ１では、ゲート電極２６にゲート電圧が印加される前のオフ状態では、ベース層２１に反転層が形成されない。このため、ドレイン電極３１に正の電圧、例えば１６００Ｖが印加されたとしても、ソース領域２２からベース層２１内に電子が流れず、ＳｉＣ半導体装置Ｓ１は、ソース電極２８とドレイン電極３１との間に電流が流れないオフ状態となる。 At this time, for example, the operation of the upper arm SiC semiconductor device S1 is as follows. That is, in this SiC semiconductor device S1, an inversion layer is not formed in the base layer 21 in the OFF state before the gate voltage is applied to the gate electrode 26. FIG. Therefore, even if a positive voltage of, for example, 1600 V is applied to the drain electrode 31, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device S1 is located between the source electrode 28 and the drain electrode 31. becomes an off state in which no current flows through.
　また、ＳｉＣ半導体装置Ｓ１がオフ状態である場合には、ドレイン－ゲート間に電界がかかり、ゲート絶縁膜２５の底部に電界集中が発生し得る。しかしながら、上記ＳｉＣ半導体装置Ｓ１では、トレンチ２４よりも深い位置に、第１ディープ層１５およびＪＦＥＴ部１４が備えられている。このため、第１ディープ層１５およびＪＦＥＴ部１４との間に構成される空乏層により、ドレイン電圧の影響による等電位線のせり上がりが抑制され、高電界がゲート絶縁膜２５に入り込み難くなる。したがって、本実施形態では、ゲート絶縁膜２５が破壊されることを抑制できる。 Also, when the SiC semiconductor device S1 is in the off state, an electric field is applied between the drain and the gate, and electric field concentration may occur at the bottom of the gate insulating film 25. FIG. However, in the SiC semiconductor device S<b>1 described above, the first deep layer 15 and the JFET portion 14 are provided at positions deeper than the trench 24 . Therefore, the depletion layer formed between the first deep layer 15 and the JFET portion 14 suppresses the rising of the equipotential lines due to the influence of the drain voltage, making it difficult for the high electric field to enter the gate insulating film 25 . Therefore, in this embodiment, it is possible to prevent the gate insulating film 25 from being destroyed.
　そして、ゲート電極２６に所定のゲート電圧、例えば２０Ｖが印加されると、ベース層２１のうちのトレンチ２４に接している表面にチャネルが形成される。これにより、ソース電極２８とドレイン電極３１との間に電流が流れ、ＳｉＣ半導体装置Ｓ１がオン状態となる。なお、本実施形態では、チャネルを通過した電子が電流分散層１７、ＪＦＥＴ部１４および低濃度層１３を通過して基板１１へ流れるため、電流分散層１７、ＪＦＥＴ部１４および低濃度層１３を有するドリフト層１９が構成されているといえる。 Then, when a predetermined gate voltage, for example 20 V, is applied to the gate electrode 26, a channel is formed on the surface of the base layer 21 that is in contact with the trench 24. Thereby, a current flows between the source electrode 28 and the drain electrode 31, and the SiC semiconductor device S1 is turned on. In the present embodiment, electrons passing through the channel flow to the substrate 11 through the current spreading layer 17, the JFET portion 14 and the lightly doped layer 13. Therefore, the current spreading layer 17, the JFET portion 14 and the lightly doped layer 13 are It can be said that the drift layer 19 having
　その後、ＳｉＣ半導体装置Ｓ１は、オン状態からオフ状態になると、逆バイアスが印加されて逆導通状態となるため、寄生ダイオードが還流ダイオードＳ１２として機能し、寄生ダイオードを通じて還流電流が流れる。そして、寄生ダイオードを構成するｐｎ接合のｐ型層側からｎ型層側に拡散したホールとｎ型層中の電子が再結合する。この際、再結合エネルギーが大きいために、基板１１やバッファ層１２内の基底面転位（以下、ＢＰＤという）が拡張して積層欠陥になる可能性がある。 After that, when the SiC semiconductor device S1 changes from the ON state to the OFF state, a reverse bias is applied and the SiC semiconductor device S1 enters a reverse conductive state, so the parasitic diode functions as a freewheeling diode S12, and a freewheeling current flows through the parasitic diode. Then, the holes diffused from the p-type layer side to the n-type layer side of the pn junction that constitutes the parasitic diode recombine with the electrons in the n-type layer. At this time, since the recombination energy is large, basal plane dislocations (hereinafter referred to as BPDs) in the substrate 11 and the buffer layer 12 may expand to form stacking faults.
　このため、本実施形態では、ＪＦＥＴ部１４に欠陥部Ｄを形成している。これにより、ＳｉＣ半導体装置Ｓ１が逆導通時である場合、欠陥部Ｄがホールトラップとして機能する。したがって、図４に示されるように、欠陥部Ｄが形成されていないＳｉＣ半導体装置Ｓ１と比較すると、逆導通時である際の電流密度を低減でき、ホールが低濃度層１３に達することを抑制できる。これにより、ＢＰＤがＳＦに拡張することを抑制でき、オン電圧が高くなることを抑制できる。 Therefore, in the present embodiment, the defect portion D is formed in the JFET portion 14 . As a result, when the SiC semiconductor device S1 is in reverse conduction, the defect portion D functions as a hole trap. Therefore, as shown in FIG. 4, compared to the SiC semiconductor device S1 in which the defect portion D is not formed, the current density during reverse conduction can be reduced, and the holes are suppressed from reaching the low-concentration layer 13. can. As a result, it is possible to suppress the expansion of the BPD to the SF and suppress the increase in the on-voltage.
　また、本実施形態では、ベース層２１は、セル部１の方が外周部２よりも不純物濃度が高くされている。このため、ＳｉＣ半導体装置Ｓ１が逆導通状態である際、セル部１の順方向電圧が外周部２の順方向電圧よりも低くなり易い。したがって、順方向電流は、欠陥部Ｄが形成されているセル部１に流れ易くなり、外周部２にてＢＰＤがＳＦに拡張することを抑制できる。 In addition, in the present embodiment, the cell portion 1 of the base layer 21 has a higher impurity concentration than the outer peripheral portion 2 . Therefore, when SiC semiconductor device S1 is in the reverse conducting state, the forward voltage of cell portion 1 tends to be lower than the forward voltage of outer peripheral portion 2 . Therefore, the forward current can easily flow into the cell section 1 in which the defect portion D is formed, and the expansion of the BPD to the SF in the outer peripheral portion 2 can be suppressed.
　以下、本実施形態のＳｉＣ半導体装置Ｓ１におけるさらなる詳細な条件および効果について説明する。 Further detailed conditions and effects of the SiC semiconductor device S1 of the present embodiment will be described below.
　まず、上記ＳｉＣ半導体装置Ｓ１では、第１ディープ層１５がＪＦＥＴ部１４よりも浅く形成されている。そして、第１ディープ層１５と低濃度層１３との間にもＪＦＥＴ部１４が配置されている。このため、第１ディープ層１５と低濃度層１３との間のＪＦＥＴ部１４によってもホールをトラップすることができる。したがって、図５に示されるように、ＳＦ面積占有率を小さくすることができる。 First, in the SiC semiconductor device S<b>1 , the first deep layer 15 is formed shallower than the JFET section 14 . A JFET portion 14 is also arranged between the first deep layer 15 and the low-concentration layer 13 . Therefore, holes can also be trapped by the JFET portion 14 between the first deep layer 15 and the low-concentration layer 13 . Therefore, as shown in FIG. 5, the SF area occupation ratio can be reduced.
　なお、図５中では、ＪＦＥＴ部１４と第１ディープ層１５とを同じ深さとし、第１ディープ層１５と低濃度層１３との間にＪＦＥＴ部１４を配置していないＳｉＣ半導体装置Ｓ１を比較例として示してある。また、ＳＦ面積占有率とは、ＳｉＣ半導体装置Ｓ１における積層欠陥の割合を示している。そして、ＳＦ面積占有率が小さいとは、ＢＰＤがＳＦに拡張し難くなっていることを示している。 In addition, in FIG. 5, the JFET portion 14 and the first deep layer 15 have the same depth, and the SiC semiconductor device S1 in which the JFET portion 14 is not arranged between the first deep layer 15 and the low-concentration layer 13 is compared. It is shown as an example. Further, the SF area occupation ratio indicates the ratio of stacking faults in the SiC semiconductor device S1. A small SF area occupation ratio indicates that BPD is difficult to expand to SF.
　また、ＳｉＣ半導体装置Ｓ１では、逆導通時にバッファ層１２へ流れるホールのホール密度が４．５×１０１６／ｃｍ３以上になると、ＢＰＤがＳＦに拡張し易いことが報告されている。そして、本発明者らにおいても、バッファ層１２へ流れるホールのホール密度が４．５×１０１６／ｃｍ３以上になると、ＢＰＤがＳＦに拡張し易いことを確認している。このため、本実施形態のＳｉＣ半導体装置Ｓ１では、以下の条件を満たすように構成されている。 Also, in the SiC semiconductor device S1, it has been reported that BPD easily expands to SF when the hole density of holes flowing into the buffer layer 12 at the time of reverse conduction is 4.5×10 16 /cm 3 or more. Also, the inventors of the present invention have confirmed that when the hole density of holes flowing into the buffer layer 12 is 4.5×10 16 /cm 3 or more, the BPD easily expands to the SF. Therefore, the SiC semiconductor device S1 of this embodiment is configured to satisfy the following conditions.
　まず、本実施形態のＪＦＥＴ部１４は、低濃度層１３にｎ型不純物がイオン注入されたイオン注入層で構成されている。このため、ＪＦＥＴ部１４は、不純物濃度が高くなる（すなわち、ドーズ量が多くなる）につれて欠陥部Ｄが多くなり、ホールトラップ層としての機能が大きくなる。具体的には、図６に示されるように、ＪＦＥＴ部１４は、不純物濃度が７．０×１０１６／ｃｍ３以上になると、ＳＦ面積占有率が小さくなることが確認される。但し、ＪＦＥＴ部１４は、不純物濃度が５．０×１０１７／ｃｍ３以上になると、ＳＦ面積占有率が増加することが確認される。これは、ＪＦＥＴ部１４に形成される欠陥部Ｄが多くなり過ぎることにより、ＢＰＤがＳＦに拡張するのではなく、当該欠陥部Ｄに起因してＳＦが形成されるためであると推定される。したがって、本実施形態では、ＪＦＥＴ部１４は、イオン注入層で構成され、不純物濃度が７．０×１０１６～５．０×１０１７／ｃｍ３とされている。 First, the JFET section 14 of this embodiment is composed of an ion-implanted layer obtained by ion-implanting an n-type impurity into the low-concentration layer 13 . Therefore, as the impurity concentration of the JFET portion 14 increases (that is, the dose amount increases), the number of defect portions D increases, and the function as a hole trap layer increases. Specifically, as shown in FIG. 6, it is confirmed that the SF area occupation ratio of the JFET portion 14 decreases when the impurity concentration is 7.0×10 16 /cm 3 or more. However, it is confirmed that the SF area occupation ratio of the JFET portion 14 increases when the impurity concentration is 5.0×10 17 /cm 3 or more. This is presumed to be due to the formation of SFs due to the defects D rather than the BPD expanding into SFs due to the excessive number of defects D formed in the JFET portion 14. . Therefore, in the present embodiment, the JFET section 14 is composed of an ion-implanted layer and has an impurity concentration of 7.0×10 16 to 5.0×10 17 /cm 3 .
　そして、ＳｉＣ半導体装置Ｓ１における逆導通時においては、チャネル長さを短くすることにより、ベース層２１内をパンチスルーモードによって流れる電子電流の割合を増加できるため、ホール電流の割合を低減できる。そして、ホール電流の割合を低減することにより、ＢＰＤに達するホールも低減できるため、ＢＰＤがＳＦに拡張することを抑制できる。具体的には、図７に示されるように、チャネル長が０．４μｍ以下になるとＳＦ面積占有率が０となる場合があり、チャネル長が０．４μｍより小さくなるについてＳＦ面積占有率が小さくなることが確認される。したがって、本実施形態では、チャネル長が０．４μｍ以下となるように、ベース層２１の厚さやソース領域２２の深さが調整されている。 During reverse conduction in the SiC semiconductor device S1, the ratio of the electron current flowing in the base layer 21 in the punch-through mode can be increased by shortening the channel length, so that the ratio of the hole current can be reduced. By reducing the ratio of the hole current, the number of holes reaching the BPD can also be reduced, so it is possible to suppress the expansion of the BPD to the SF. Specifically, as shown in FIG. 7, the SF area occupation ratio may become 0 when the channel length is 0.4 μm or less, and the SF area occupation ratio decreases as the channel length becomes smaller than 0.4 μm. It is confirmed that Therefore, in this embodiment, the thickness of the base layer 21 and the depth of the source region 22 are adjusted so that the channel length is 0.4 μm or less.
　また、電子電流の割合を増加してホール電流の割合を低減する構造としては、ベース層２１の不純物濃度を低くするようにしてもよい。具体的には、図８に示されるように、ベース層２１の不純物濃度を３．０×１０１７／ｃｍ３以下とすると、ＳＦ面積占有率が０となる場合がある。したがって、本実施形態では、ベース層２１の不純物濃度が３．０×１０１７／ｃｍ３以下とされている。 As a structure for increasing the electron current ratio and decreasing the hole current ratio, the impurity concentration of the base layer 21 may be lowered. Specifically, as shown in FIG. 8, when the impurity concentration of the base layer 21 is 3.0×10 17 /cm 3 or less, the SF area occupancy may become zero. Therefore, in this embodiment, the impurity concentration of the base layer 21 is 3.0×10 17 /cm 3 or less.
　さらに、電子電流の割合を増加してホール電流の割合を低減する構造としては、第１ディープ層１５の幅Ｌ１を規定するようにしてもよい。具体的には、図９に示されるように、第１ディープ層１５の幅Ｌ１は、０．９μｍ以下であると、ホール電流密度を４．５×１０１６／ｃｍ３以下とできる。したがって、本実施形態では、第１ディープ層１５の幅Ｌ１は、０．９μｍ以下とされている。なお、図９のホール電流密度は、バッファ層１２へ流れるホール電流の密度を示している。 Furthermore, as a structure for increasing the proportion of electron current and decreasing the proportion of hole current, the width L1 of the first deep layer 15 may be defined. Specifically, as shown in FIG. 9, when the width L1 of the first deep layer 15 is 0.9 μm or less, the hole current density can be 4.5×10 16 /cm 3 or less. Therefore, in this embodiment, the width L1 of the first deep layer 15 is set to 0.9 μm or less. Note that the hole current density in FIG. 9 indicates the density of the hole current flowing into the buffer layer 12 .
　また、電子電流の割合を増加してホール電流の割合を低減する構造としては、隣合うトレンチ２４の中心間の距離（すなわち、トレンチピッチ）を規定するようにしてもよい。具体的には、図１０に示されるように、隣合うトレンチ２４の中心間の距離を３．０μｍ以下とすることにより、ホール電流密度を４．５×１０１６／ｃｍ３以下とできる。なお、図１０のホール電流密度は、バッファ層１２へ流れるホール電流の密度を示している。 As a structure for increasing the proportion of electron current and decreasing the proportion of hole current, the distance between the centers of adjacent trenches 24 (that is, trench pitch) may be defined. Specifically, as shown in FIG. 10, the hole current density can be reduced to 4.5×10 16 /cm 3 or less by setting the distance between the centers of adjacent trenches 24 to 3.0 μm or less. Note that the hole current density in FIG. 10 indicates the density of the hole current flowing into the buffer layer 12 .
　そして、上記のようなＳｉＣ半導体装置Ｓ１では、以下の特性も重要な特性となる。 In the SiC semiconductor device S1 as described above, the following characteristics are also important characteristics.
　まず、図１１に示されるように、ＳｉＣ半導体装置Ｓ１がオン状態である際のオン電圧（すなわち、Ｖｏｎ）は、隣合う第１ディープ層１５の間隔Ｌ２を長くするほど第１ディープ層１５で挟まれるＪＦＥＴ部１４の幅が広がるため、小さくなる。そして、現状では、２００Ａを流す場合において、オン電圧を０．９Ｖ以下とすることが望まれている。したがって、隣合う第１ディープ層１５の間隔Ｌ２は、０．７５μｍ以上とされている。 First, as shown in FIG. 11, the on-voltage (that is, Von) when the SiC semiconductor device S1 is in the on-state increases in the first deep layers 15 as the interval L2 between the adjacent first deep layers 15 increases. Since the width of the sandwiched JFET portion 14 is widened, it becomes small. At present, it is desired that the on-voltage be 0.9 V or less when 200 A is applied. Therefore, the interval L2 between adjacent first deep layers 15 is set to 0.75 μm or more.
　また、図１２に示されるように、オフ状態においてゲート絶縁膜２５に印加される電界（すなわち、Ｅｍａｘ）は、隣合う第１ディープ層１５の間隔Ｌ２を長くするほど第１ディープ層１５で挟まれるＪＦＥＴ部１４の幅が広がるため、高くなる。そして、現状では、オフ状態においてゲート絶縁膜２５に印加される電界を５ＭＶ／ｃｍ以下とすることが望まれている。したがって、隣合う第１ディープ層１５の間隔Ｌ２は、１．２μｍ以下とされている。 In addition, as shown in FIG. 12, the electric field (that is, Emax) applied to the gate insulating film 25 in the OFF state is sandwiched between the first deep layers 15 as the distance L2 between the adjacent first deep layers 15 is increased. Since the width of the JFET portion 14 that is connected to the substrate is widened, the height is increased. At present, it is desired that the electric field applied to the gate insulating film 25 in the OFF state is 5 MV/cm or less. Therefore, the interval L2 between adjacent first deep layers 15 is set to 1.2 μm or less.
　さらに、図１３に示されるように、帰還容量（すなわち、Ｃｒｓｓ）は、隣合う第１ディープ層１５の間隔Ｌ２を長くするほど第１ディープ層１５で挟まれるＪＦＥＴ部１４の幅が広がるため、高くなる。そして、現状では、帰還容量を５０ｐＦ以下とすることが望まれている。したがって、隣合う第１ディープ層１５の間隔Ｌ２は、１．１μｍ以下とされている。 Furthermore, as shown in FIG. 13, the feedback capacitance (that is, Crss) increases the width of the JFET portion 14 sandwiched between the first deep layers 15 as the interval L2 between the adjacent first deep layers 15 increases. get higher At present, it is desired to set the feedback capacitance to 50 pF or less. Therefore, the interval L2 between adjacent first deep layers 15 is set to 1.1 μm or less.
　つまり、本実施形態では、隣合う第１ディープ層１５の間隔Ｌ２が０．７５～１．１μｍとされている。 That is, in the present embodiment, the interval L2 between adjacent first deep layers 15 is 0.75 to 1.1 μm.
　以上説明した本実施形態によれば、ＪＦＥＴ部１４には、欠陥部Ｄが形成されている。このため、ＳｉＣ半導体装置Ｓ１の逆導通時において、ホールが欠陥部ＤにトラップされることでＢＰＤに到達することを抑制できる。したがって、ＢＰＤがＳＦに拡張することを抑制でき、オン電圧が高くなることを抑制できる。 According to the present embodiment described above, the defective portion D is formed in the JFET portion 14 . Therefore, it is possible to prevent holes from being trapped in the defect portion D and reaching the BPD during reverse conduction of the SiC semiconductor device S1. Therefore, it is possible to suppress the expansion of BPD to SF, and to suppress the on-voltage from increasing.
　（１）本実施形態では、セル部１は、外周部２よりも、ベース層２１の不純物濃度が高くされている。このため、ＳｉＣ半導体装置Ｓ１が逆導通状態である際、セル部１の順方向電圧が外周部２の順方向電圧よりも低くなる。したがって、順方向電流は、欠陥部Ｄが形成されているセル部１に流れ易くなり、外周部２にてＢＰＤがＳＦに拡張することを抑制できる。 (1) In the present embodiment, the impurity concentration of the base layer 21 in the cell section 1 is higher than that in the outer peripheral section 2 . Therefore, when SiC semiconductor device S1 is in the reverse conducting state, the forward voltage of cell portion 1 is lower than the forward voltage of outer peripheral portion 2 . Therefore, the forward current can easily flow into the cell section 1 in which the defect portion D is formed, and the expansion of the BPD to the SF in the outer peripheral portion 2 can be suppressed.
　（２）本実施形態では、第１ディープ層１５は、ＪＦＥＴ部１４よりも浅く形成されている。そして、第１ディープ層１５と低濃度層１３との間には、ＪＦＥＴ部１４が配置されている。このため、第１ディープ層１５と低濃度層１３との間のＪＦＥＴ部１４によってもホールをトラップすることができる。したがって、さらにホールがＢＰＤに到達することを抑制でき、さらにＢＰＤがＳＦに拡張することを抑制できる。 (2) In this embodiment, the first deep layer 15 is formed shallower than the JFET section 14 . A JFET portion 14 is arranged between the first deep layer 15 and the low-concentration layer 13 . Therefore, holes can also be trapped by the JFET portion 14 between the first deep layer 15 and the low-concentration layer 13 . Therefore, it is possible to further suppress the holes from reaching the BPD, and further suppress the expansion of the BPD to the SF.
　（３）本実施形態では、ＪＦＥＴ部１４は、不純物濃度が７．０×１０１６～５．０×１０１７／ｃｍ３とされている。このため、バッファ層１２に流れ込むホール電流の密度を４．５×１０１６／ｃｍ３以下とでき、ＢＰＤがＳＦに拡張することを抑制できる。 (3) In this embodiment, the JFET portion 14 has an impurity concentration of 7.0×10 16 to 5.0×10 17 /cm 3 . Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5×10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
　（４）本実施形態では、チャネル長が０．４μｍとされている。このため、バッファ層１２に流れ込むホール電流の密度を４．５×１０１６／ｃｍ３以下とでき、ＢＰＤがＳＦに拡張することを抑制できる。 (4) In this embodiment, the channel length is 0.4 μm. Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5×10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
　（５）本実施形態では、ベース層２１の不純物濃度が３．０×１０１７／ｃｍ３とされている。このため、バッファ層１２に流れ込むホール電流の密度を４．５×１０１６／ｃｍ３以下とでき、ＢＰＤがＳＦに拡張することを抑制できる。 (5) In this embodiment, the impurity concentration of the base layer 21 is 3.0×10 17 /cm 3 . Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5×10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
　（６）本実施形態では、第１ディープ層１５は、幅Ｌ１が０．９μｍ以下とされている。このため、バッファ層１２に流れ込むホール電流の密度を４．５×１０１６／ｃｍ３以下とでき、ＢＰＤがＳＦに拡張することを抑制できる。 (6) In the present embodiment, the first deep layer 15 has a width L1 of 0.9 μm or less. Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5×10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
　（７）本実施形態では、第１ディープ層１５が外周部２まで延設されている。このため、外周部２でのダイオード特性を向上できる。 (7) In this embodiment, the first deep layer 15 extends to the outer peripheral portion 2 . Therefore, diode characteristics in the outer peripheral portion 2 can be improved.
　（８）本実施形態では、隣合うトレンチ２４の中心間の距離は、３．０μｍ以下とされている。このため、バッファ層１２に流れ込むホール電流の密度を４．５×１０１６／ｃｍ３以下とでき、ＢＰＤがＳＦに拡張することを抑制できる。 (8) In this embodiment, the distance between the centers of adjacent trenches 24 is 3.0 μm or less. Therefore, the density of the hole current flowing into the buffer layer 12 can be reduced to 4.5×10 16 /cm 3 or less, and expansion of BPD to SF can be suppressed.
　（９）本実施形態では、隣合う第１ディープ層１５の間隔Ｌ２が０．７５μｍ以上とされている。このため、オン電圧が増加することを抑制できる。 (9) In the present embodiment, the interval L2 between adjacent first deep layers 15 is 0.75 μm or more. Therefore, an increase in ON voltage can be suppressed.
　（１０）本実施形態では、隣合う第１ディープ層１５の間隔Ｌ２が１．１μｍ以下とされている。このため、オフ状態である際にゲート絶縁膜２５に印加される電界が大きくなることを抑制できると共に、帰還容量が大きくなることを抑制できる。 (10) In the present embodiment, the interval L2 between adjacent first deep layers 15 is 1.1 μm or less. Therefore, it is possible to suppress an increase in the electric field applied to the gate insulating film 25 in the OFF state, and an increase in the feedback capacitance.
　（１１）本実施形態では、インバータ回路１００に備えられる還流ダイオードＳ１２として、ＳｉＣ半導体装置Ｓ１に構成される寄生ダイオードを利用している。このため、ＭＯＳＦＥＴＳ１１とは別に還流ダイオードＳ１２を構成する別部材を用意する必要がなく、構成の簡略化を図ることができる。 (11) In the present embodiment, a parasitic diode configured in the SiC semiconductor device S1 is used as the freewheeling diode S12 provided in the inverter circuit 100. FIG. Therefore, there is no need to prepare a separate member that constitutes the free wheel diode S12 in addition to the MOSFETS11, so that the configuration can be simplified.
　（第２実施形態）
　第２実施形態について説明する。本実施形態は、第１実施形態に対し、第１ディープ層１５の長手方向を変更したものである。その他に関しては、第１実施形態と同様であるため、ここでは説明を省略する。 (Second embodiment)
A second embodiment will be described. In this embodiment, the longitudinal direction of the first deep layer 15 is changed from the first embodiment. Others are the same as those of the first embodiment, so description thereof is omitted here.
　本実施形態では、図１４に示されるように、セル部１において、第１ディープ層１５および電流分散層１７は、線状部分がＹ軸方向を長手方向として延設されている。また、第１ディープ層１５は、法線方向において、トレンチ２４を挟むように形成されている。 In the present embodiment, as shown in FIG. 14, in the cell section 1, the linear portions of the first deep layer 15 and the current spreading layer 17 are extended with the Y-axis direction as the longitudinal direction. Also, the first deep layer 15 is formed so as to sandwich the trench 24 in the normal direction.
　以上説明した本実施形態のように、第１ディープ層１５および電流分散層１７をＹ軸方向に沿って延設するようにしても、ＪＦＥＴ部１４に欠陥部Ｄが形成されていることにより、上記第１実施形態と同様に、オン電圧が高くなることを抑制できる。 Even if the first deep layer 15 and the current spreading layer 17 are extended along the Y-axis direction as in the present embodiment described above, since the defect portion D is formed in the JFET portion 14, As in the first embodiment, it is possible to prevent the ON voltage from increasing.
　（第３実施形態）
　第３実施形態について説明する。本実施形態は、第１実施形態に対し、ベース層２１および電流分散層１７に欠陥部を形成したものである。その他に関しては、第１実施形態と同様であるため、ここでは説明を省略する。 (Third embodiment)
A third embodiment will be described. In this embodiment, defects are formed in the base layer 21 and the current spreading layer 17 in contrast to the first embodiment. Others are the same as those of the first embodiment, so description thereof is omitted here.
　本実施形態では、図１５に示されるように、ベース層２１に欠陥部Ｄ１が形成されていると共に、電流分散層１７に欠陥部Ｄ２が形成されている。ベース層２１の欠陥部Ｄ１は、ベース層２１をイオン注入によって構成することで形成される。電流分散層１７の欠陥部Ｄ２は、ベース層２１をイオン注入で形成する際のｐ型の不純物が電流分散層１７に入り込むことで形成される。 In this embodiment, as shown in FIG. 15, the base layer 21 is formed with the defective portion D1, and the current spreading layer 17 is formed with the defective portion D2. The defect portion D1 of the base layer 21 is formed by configuring the base layer 21 by ion implantation. The defect portion D2 of the current spreading layer 17 is formed when p-type impurities enter the current spreading layer 17 when the base layer 21 is formed by ion implantation.
　具体的には、図１６に示されるように、ベース層２１および電流分散層１７は、ｐ型の不純物濃度分布において、電流分散層１７にもｐ型の不純物が存在するように構成されている。言い換えると、ベース層２１および電流分散層１７は、ｐ型の不純物濃度分布におけるテール部Ｔが電流分散層１７内に位置するように形成されている。不純物濃度分布におけるテール部Ｔとは、深さ方向における他面１０ｂ側の部分のことである。なお、このようなベース層２１および電流分散層１７は、加速電圧を変更しながら複数回のイオン注入を行ってベース層２１を形成し、ベース層２１を形成する際のｐ型の不純物を電流分散層１７に入り込ませることで形成される。図１６は、加速電圧を変更しながら３回のイオン注入を行った場合の図を示している。 Specifically, as shown in FIG. 16, the base layer 21 and the current spreading layer 17 are configured such that the p-type impurity exists in the current spreading layer 17 in the p-type impurity concentration distribution. . In other words, base layer 21 and current spreading layer 17 are formed such that tail portion T in the p-type impurity concentration distribution is located in current spreading layer 17 . The tail portion T in the impurity concentration distribution is the portion on the side of the other surface 10b in the depth direction. Note that the base layer 21 and the current spreading layer 17 are formed by performing ion implantation a plurality of times while changing the acceleration voltage to form the base layer 21, and removing the p-type impurity in forming the base layer 21 with a current. It is formed by penetrating into the dispersion layer 17 . FIG. 16 shows a diagram when ion implantation is performed three times while changing the acceleration voltage.
　また、本実施形態のベース層２１および電流分散層１７は、電流分散層１７に欠陥部Ｄ２が十分に形成されるように、電流分散層１７内にｐ型の不純物濃度が１．０×１０１５／ｃｍ３以上となる部分を有するように構成されている。なお、本発明者らの検討によれば、ｐ型の不純物濃度が１．０×１０１５／ｃｍ３以上となる部分を有するように電流分散層１７が構成されている場合、十分に欠陥部Ｄ２が形成されることが確認されている。 Further, the base layer 21 and the current spreading layer 17 of the present embodiment have a p-type impurity concentration of 1.0×10 in the current spreading layer 17 so that the defect D2 is sufficiently formed in the current spreading layer 17. It is configured to have a portion of 15 /cm 3 or more. According to the studies of the present inventors, when the current spreading layer 17 is configured to have a portion where the p-type impurity concentration is 1.0×10 15 /cm 3 or more, the defect portion is sufficient. It has been confirmed that D2 is formed.
　以上が本実施形態におけるＳｉＣ半導体装置Ｓ１の構成である。次に、上記ＳｉＣ半導体装置Ｓ１におけるベース層２１の欠陥部Ｄ１および電流分散層１７の欠陥部Ｄ２の形成方法について、図１７Ａ、図１７Ｂを参照しつつ説明する。 The above is the configuration of the SiC semiconductor device S1 in this embodiment. Next, a method for forming the defective portion D1 of the base layer 21 and the defective portion D2 of the current spreading layer 17 in the SiC semiconductor device S1 will be described with reference to FIGS. 17A and 17B.
　まず、図１７Ａに示されるように、基板１１、バッファ層１２、低濃度層１３、ＪＦＥＴ部１４、第１ディープ層１５、電流分散層１７、第２ディープ層１８が形成されたものを用意する。そして、電流分散層１７および第２ディープ層１８上に、ベース層２１を構成するベース層構成層２１０をエピタキシャル成長させたエピタキシャル層で配置する。本実施形態では、ベース層構成層２１０は、後述するイオン注入を行ってベース層２１を構成した際の不純物濃度よりも１桁以上小さい不純物濃度となるように、エピタキシャル成長で構成される。これにより、所望の不純物濃度を有するベース層２１をエピタキシャル成長によって形成する場合と比較して、不純物濃度の面内ばらつきを抑制できる。なお、本実施形態のベース層構成層２１０は、厚さがベース層２１と等しくされている。但し、ベース層構成層２１０は、厚さがベース層２１の厚さおよびソース領域２２の厚さの和と等しくされていてもよい。 First, as shown in FIG. 17A, a substrate 11, a buffer layer 12, a low-concentration layer 13, a JFET portion 14, a first deep layer 15, a current spreading layer 17, and a second deep layer 18 are prepared. . Then, on the current spreading layer 17 and the second deep layer 18, the base layer constituting layer 210 constituting the base layer 21 is arranged as an epitaxially grown epitaxial layer. In this embodiment, the base layer-constituting layer 210 is epitaxially grown so as to have an impurity concentration that is one order of magnitude lower than the impurity concentration when the base layer 21 is formed by ion implantation, which will be described later. As a result, in-plane variations in impurity concentration can be suppressed compared to the case where the base layer 21 having a desired impurity concentration is formed by epitaxial growth. Note that the thickness of the base layer-constituting layer 210 of the present embodiment is equal to that of the base layer 21 . However, the base layer configuration layer 210 may have a thickness equal to the sum of the thickness of the base layer 21 and the thickness of the source region 22 .
　次に、図１７Ｂに示されるように、加速電圧を変更しながら複数回のイオン注入を行うことでベース層２１を構成する。例えば、ベース層２１を構成する際には、図１６に示されるように、電流分散層１７にｐ型の不純物濃度が１．５×１０１５／ｃｍ３となる部分が含まれるように、加速電圧を変更しながらイオン注入を行ってベース層２１を構成する。なお、図１６では、加速電圧を変更しながら３回のイオン注入を行った場合の図が示されている。これにより、ベース層２１に欠陥部Ｄ１が構成されると共に、電流分散層１７に欠陥部Ｄ２が構成される。 Next, as shown in FIG. 17B, the base layer 21 is formed by performing ion implantation a plurality of times while changing the acceleration voltage. For example, when forming the base layer 21, as shown in FIG. 16, the current spreading layer 17 includes a portion having a p-type impurity concentration of 1.5×10 15 /cm 3 . The base layer 21 is formed by ion implantation while changing the voltage. Note that FIG. 16 shows a case where ion implantation is performed three times while changing the acceleration voltage. As a result, the base layer 21 is formed with the defective portion D1, and the current spreading layer 17 is formed with the defective portion D2.
　また、上記のように、ＪＦＥＴ部１４の欠陥部Ｄは、イオン注入を行うことによって形成される。ベース層２１の欠陥部Ｄ１および電流分散層１７の欠陥部Ｄ２は、イオン注入を行うことによって形成される。ここで、ＳｉＣにイオン注入を行う場合、高温でイオン注入すると欠陥部が発生し難くなることが報告されている。このため、本実施形態では、イオン注入は、ＪＦＥＴ部１４を構成するための低濃度層１３やベース層構成層２１０をエピタキシャル成長させて配置する際に発生し得る欠陥部よりも、多量の欠陥部Ｄ、Ｄ１、Ｄ２が形成される温度で行う。具体的には、本実施形態では、各イオン注入を行う際の温度を室温から２００℃以下の温度とする。これにより、イオン注入時に各欠陥部Ｄ、Ｄ１、Ｄ２が形成されないことを抑制できる。なお、本発明者らの検討によれば、２００℃以下の温度でイオン注入を行うことにより、各欠陥部Ｄ、Ｄ１、Ｄ２が適切に形成されることが確認されている。また、本実施形態における室温とは、１～３０℃程度の温度のことである。 Also, as described above, the defect portion D of the JFET portion 14 is formed by ion implantation. The defect D1 of the base layer 21 and the defect D2 of the current spreading layer 17 are formed by ion implantation. Here, it has been reported that when ions are implanted into SiC, defects are less likely to occur if the ions are implanted at a high temperature. For this reason, in the present embodiment, the ion implantation is performed so that a larger number of defects than those which may occur when the low-concentration layer 13 and the base layer-constituting layer 210 for forming the JFET section 14 are epitaxially grown and arranged. The temperature is such that D, D1 and D2 are formed. Specifically, in this embodiment, the temperature at which each ion implantation is performed is from room temperature to 200° C. or less. Thereby, it is possible to prevent the defect portions D, D1, and D2 from not being formed at the time of ion implantation. According to studies by the present inventors, it has been confirmed that the defects D, D1, and D2 are appropriately formed by ion implantation at a temperature of 200° C. or less. Further, the room temperature in this embodiment means a temperature of about 1 to 30.degree.
　その後は、特に図示しないが、ソース領域２２、コンタクト領域２３、トレンチゲート構造等を形成することにより、上記ＳｉＣ半導体装置Ｓ１が製造される。 After that, although not shown, the SiC semiconductor device S1 is manufactured by forming the source region 22, the contact region 23, the trench gate structure, and the like.
　以上説明した本実施形態によれば、ＪＦＥＴ部１４に欠陥部Ｄが形成されているため、上記第１実施形態と同様の効果を得ることができる。 According to the present embodiment described above, since the defective portion D is formed in the JFET portion 14, it is possible to obtain the same effects as in the first embodiment.
　（１）本実施形態では、ベース層２１に欠陥部Ｄ１を形成すると共に電流分散層１７に欠陥部Ｄ２を形成している。このため、ホール電流が流れる経路において、欠陥部Ｄ１、Ｄ２となる部分が増加し、ＪＦＥＴ部１４の欠陥部Ｄ以外でもホールをトラップすることができるため、さらにＢＰＤにホールが達することを抑制できる。 (1) In the present embodiment, the defect portion D1 is formed in the base layer 21 and the defect portion D2 is formed in the current spreading layer 17 . Therefore, in the path through which the hole current flows, the portions that become the defective portions D1 and D2 increase, and the holes can be trapped in areas other than the defective portion D of the JFET portion 14, so that the holes can be further suppressed from reaching the BPD. .
　（２）本実施形態では、電流分散層１７は、ｐ型の不純物濃度が１．０×１０１５／ｃｍ３以上となる部分を有するように構成されている。このため、電流分散層１７にｐ型の不純物に起因する欠陥部Ｄ２を容易に形成できる。 (2) In this embodiment, the current spreading layer 17 is configured to have a portion where the p-type impurity concentration is 1.0×10 15 /cm 3 or more. Therefore, the defect D2 caused by the p-type impurity can be easily formed in the current spreading layer 17 .
　（３）本実施形態では、複数回のイオン注入を行ってベース層２１を形成している。このため、ｐ型の不純物濃度が１．０×１０１５／ｃｍ３以上となる部分を有する電流分散層１７を容易に形成できる。また、複数回のイオン注入行ってベース層２１を形成するため、例えば、１回のイオン注入でベース層２１を形成する場合と比較とすると、ベース層２１における深さ方向の不純物濃度分布がばらつくことを抑制できる。したがって、ＳｉＣ半導体をオン状態とするのに必要なゲート電極２６への閾値電圧が変動することも抑制できる。 (3) In this embodiment, the base layer 21 is formed by performing ion implantation multiple times. Therefore, the current spreading layer 17 having a portion with a p-type impurity concentration of 1.0×10 15 /cm 3 or more can be easily formed. In addition, since the base layer 21 is formed by performing ion implantation a plurality of times, the impurity concentration distribution in the depth direction in the base layer 21 varies as compared with the case where the base layer 21 is formed by, for example, one ion implantation. can be suppressed. Therefore, it is possible to suppress the fluctuation of the threshold voltage to the gate electrode 26 required to turn on the SiC semiconductor.
　（４）本実施形態では、ベース層構成層２１０を構成する際には、不純物濃度がベース層２１の不純物濃度よりも１桁以上小さくなるようにしている。これにより、所望の不純物濃度を有するベース層２１をエピタキシャル成長によって形成する場合と比較して、不純物濃度の面内ばらつきを抑制できる。 (4) In the present embodiment, when the base layer-constituting layer 210 is formed, the impurity concentration is set to be lower than that of the base layer 21 by one order of magnitude or more. As a result, in-plane variations in impurity concentration can be suppressed compared to the case where the base layer 21 having a desired impurity concentration is formed by epitaxial growth.
　（５）本実施形態では、イオン注入を２００℃以下の温度で行っている。このため、イオン注入時に各欠陥部Ｄ、Ｄ１、Ｄ２が適切に形成されないことを抑制できる。 (5) In this embodiment, ion implantation is performed at a temperature of 200° C. or less. Therefore, it is possible to prevent the defects D, D1, and D2 from being properly formed at the time of ion implantation.
　（他の実施形態）
　本開示は、実施形態に準拠して記述されたが、本開示は当該実施形態や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 (Other embodiments)
Although the present disclosure has been described with reference to embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.
　例えば、上記各実施形態では、第１導電型をｎ型とすると共に第２導電型をｐ型とした例について説明したが、第１導電型をｐ型とすると共に第２導電型をｎ型としてもよい。 For example, in each of the above embodiments, an example in which the first conductivity type is the n-type and the second conductivity type is the p-type has been described. may be
　また、上記各実施形態において、第１ディープ層１５および第２ディープ層１８の少なくとも一方において、内部に欠陥部Ｄが形成されるようにしてもよい。つまり、ホール電流が流れる経路において、欠陥部Ｄとなる部分が増えるようにしてもよい。この場合、例えば、第１ディープ層１５に欠陥部Ｄが形成されるようにする場合には、第１ディープ層１５に欠陥部Ｄが形成されるように、第１ディープ層１５をイオン注入等で形成すればよい。これによれば、ＪＦＥＴ部１４の欠陥部Ｄ以外でもホールをトラップすることができるため、さらにＢＰＤにホールが達することを抑制できる。 Further, in each of the above-described embodiments, at least one of the first deep layer 15 and the second deep layer 18 may have a defective portion D formed therein. In other words, the portion that becomes the defective portion D may be increased in the path through which the hole current flows. In this case, for example, when the defect portion D is to be formed in the first deep layer 15 , the first deep layer 15 is ion-implanted or the like so that the defect portion D is formed in the first deep layer 15 . It should be formed with According to this, since holes can be trapped in areas other than the defective portion D of the JFET portion 14, it is possible to further suppress the holes from reaching the BPD.
　さらに、上記各実施形態において、欠陥部Ｄは、イオン注入で形成されていなくてもよい。例えば、欠陥部Ｄは、ＪＦＥＴ部１４をエピタキシャル成長等で構成した後、ヘリウム等の電子線を照射することで形成されるようにしてもよい。また、ＪＦＥＴ部１４をエピタキシャル成長等で構成する場合には、ボロン、ガリウム、アルミニウム等のｐ型の不純物を混入し、不純物の総量を増加させることによって欠陥部Ｄを構成するようにしてもよい。つまり、欠陥部Ｄは、イオン注入や電子線等の照射ではなく、エピタキシャル膜を形成する際に同時に形成されるようにしてもよい。なお、このようにｐ型の不純物を混入させて欠陥部Ｄを構成する場合には、ＪＦＥＴ部１４の全体の不純物濃度が低くなり過ぎないように、ｎ型不純物の総量を調整することが好ましい。また、ＪＦＥＴ部１４をエピタキシャル成長で構成する場合には、バナジウム、チタン、鉄等のホール捕獲率が電子捕獲率よりも高い不純物を混入させるようにしてもよい。これによれば、さらにＪＦＥＴ部１４からホールが排出されることを抑制できる。 Furthermore, in each of the above embodiments, the defect portion D does not have to be formed by ion implantation. For example, the defect portion D may be formed by irradiating an electron beam such as helium after forming the JFET portion 14 by epitaxial growth or the like. When the JFET portion 14 is formed by epitaxial growth or the like, the defect portion D may be formed by adding p-type impurities such as boron, gallium, and aluminum to increase the total amount of impurities. That is, the defect portion D may be formed at the same time as the epitaxial film is formed, instead of ion implantation or electron beam irradiation. When forming the defect portion D by mixing p-type impurities in this way, it is preferable to adjust the total amount of n-type impurities so that the impurity concentration of the entire JFET portion 14 does not become too low. . Further, when the JFET portion 14 is formed by epitaxial growth, impurities such as vanadium, titanium, iron, etc. having a higher hole capture rate than the electron capture rate may be mixed. According to this, it is possible to further suppress the holes from being discharged from the JFET section 14 .
　また、エピタキシャル成長でＪＦＥＴ部１４を構成しつつＪＦＥＴ部１４に欠陥部Ｄを構成する場合、第１ディープ層１５は次のように形成される。すなわち、第１ディープ層１５は、セル部１において低濃度層１３上の全体にＪＦＥＴ部１４を形成した後、ＪＦＥＴ部１４の所定箇所にイオン注入等をすることによって形成される。この場合、低濃度層１３上の全体に配置されたＪＦＥＴ部１４には欠陥部Ｄが形成されているため、第１ディープ層１５にも欠陥部Ｄが形成された状態となる。したがって、第１ディープ層１５からホールが排出されることも抑制できる。 Also, when forming the JFET portion 14 by epitaxial growth and forming the defect portion D in the JFET portion 14, the first deep layer 15 is formed as follows. That is, the first deep layer 15 is formed by forming the JFET portion 14 entirely on the low-concentration layer 13 in the cell portion 1 and then ion-implanting predetermined portions of the JFET portion 14 . In this case, since the defect portion D is formed in the JFET portion 14 arranged entirely on the low-concentration layer 13 , the defect portion D is also formed in the first deep layer 15 . Therefore, the discharge of holes from the first deep layer 15 can also be suppressed.
　また、上記各実施形態において、セル部１は、逆導通時において、外周部２と同じ順方向電圧となるように構成されていてもよい。上記各実施形態において、ＪＦＥＴ部１４と第１ディープ層１５とが同じ厚さとされていてもよい。すなわち、第１ディープ層１５と低濃度層１３との間にＪＦＥＴ部１４が配置されていなくてもよい。また、上記各実施形態において、ＪＦＥＴ部１４等の不純物濃度、ベース層２１の不純物濃度、第１ディープ層１５の幅Ｌ１等は、適宜変更してもよい。このようなＳｉＣ半導体装置Ｓ１としても、ＪＦＥＴ部１４に欠陥部Ｄが形成されていることにより、ＢＰＤがＳＦに拡張することを抑制でき、オン電圧が高くなることを抑制できる。 In addition, in each of the above embodiments, the cell section 1 may be configured to have the same forward voltage as that of the outer peripheral section 2 during reverse conduction. In each of the above embodiments, the JFET section 14 and the first deep layer 15 may have the same thickness. That is, the JFET section 14 may not be arranged between the first deep layer 15 and the low concentration layer 13 . Further, in each of the above-described embodiments, the impurity concentration of the JFET portion 14 and the like, the impurity concentration of the base layer 21, the width L1 of the first deep layer 15, and the like may be changed as appropriate. Even in such a SiC semiconductor device S1, since the defective portion D is formed in the JFET portion 14, expansion of the BPD to the SF can be suppressed, and an increase in the ON voltage can be suppressed.

Claims (18)

  1. 　トレンチゲート構造を有するＭＯＳ構造のスイッチング素子が形成された炭化珪素半導体装置であって、
    　前記スイッチング素子が形成されるセル部（１）と、
    　前記セル部を囲む外周部（２）と、を有し、
    　前記セル部は、
    　炭化珪素からなる第１導電型の基板（１１）と、
    　前記基板上に形成され、前記基板よりも低不純物濃度とされた第１導電型のバッファ層（１２）と、
    　前記バッファ層上に形成され、前記基板よりも低不純物濃度とされた第１導電型の低濃度層（１３）と、
    　前記低濃度層上に形成され、前記基板の面方向における一方向を長手方向とする複数の線状部分を有する第２導電型の第１ディープ層（１５）と、
    　前記低濃度層上に配置され、前記第１ディープ層に挟まれた線状部分を有する第１導電型のＪＦＥＴ部（１４）と、
    　前記ＪＦＥＴ部上に配置され、前記低濃度層よりも高不純物濃度とされた第１導電型の電流分散層（１７）と、
    　前記第１ディープ層上に配置された第２導電型の第２ディープ層（１８）と、
    　前記電流分散層および前記第２ディープ層の上に配置された第２導電型のベース層（２１）と、
    　前記ベース層の表層部に形成された第１導電型の不純物領域（２２）と、
    　前記不純物領域および前記ベース層を貫通して前記電流分散層に達するトレンチ（２４）の壁面に形成されたゲート絶縁膜（２５）と、前記ゲート絶縁膜上に形成されたゲート電極（２６）とを有する前記トレンチゲート構造と、
    　前記不純物領域および前記ベース層と電気的に接続される第１電極（２８）と、
    　前記基板と電気的に接続される第２電極（３１）と、を備え、
    　前記ＪＦＥＴ部には、欠陥部（Ｄ）が形成されている炭化珪素半導体装置。     A silicon carbide semiconductor device formed with a switching element of a MOS structure having a trench gate structure,
    a cell portion (1) in which the switching element is formed;
    and an outer peripheral portion (2) surrounding the cell portion,
    The cell part is
    a first conductivity type substrate (11) made of silicon carbide;
    a buffer layer (12) of a first conductivity type formed on the substrate and having an impurity concentration lower than that of the substrate;
    a first conductivity type low concentration layer (13) formed on the buffer layer and having an impurity concentration lower than that of the substrate;
    a first deep layer (15) of a second conductivity type formed on the low-concentration layer and having a plurality of linear portions having a longitudinal direction in one direction in the surface direction of the substrate;
    a first conductivity type JFET portion (14) disposed on the low-concentration layer and having a linear portion sandwiched between the first deep layers;
    a first conductivity type current spreading layer (17) disposed on the JFET portion and having an impurity concentration higher than that of the low concentration layer;
    a second deep layer (18) of a second conductivity type disposed on the first deep layer;
    a second conductivity type base layer (21) disposed over the current spreading layer and the second deep layer;
    a first conductivity type impurity region (22) formed in a surface layer portion of the base layer;
    a gate insulating film (25) formed on a wall surface of a trench (24) penetrating the impurity region and the base layer and reaching the current spreading layer; and a gate electrode (26) formed on the gate insulating film. the trench gate structure having
    a first electrode (28) electrically connected to the impurity region and the base layer;
    a second electrode (31) electrically connected to the substrate;
    A silicon carbide semiconductor device, wherein a defective portion (D) is formed in the JFET portion.
  2. 　前記セル部は、前記外周部より、前記スイッチング素子が逆導通状態である際の順方向電圧が低くされている請求項１に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1, wherein the cell portion has a lower forward voltage than the outer peripheral portion when the switching element is in the reverse conducting state.
  3. 　前記ＪＦＥＴ部は、前記第１ディープ層と前記低濃度層との間にも配置されている請求項１または２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1 or 2, wherein said JFET portion is also arranged between said first deep layer and said low concentration layer.
  4. 　前記ＪＦＥＴ部は、イオン注入層で構成され、不純物濃度が７．０×１０１６～５．０×１０１７／ｃｍ３とされている請求項１ないし３のいずれか１つに記載の炭化珪素半導体装置。 The silicon carbide according to any one of claims 1 to 3, wherein the JFET portion is composed of an ion-implanted layer and has an impurity concentration of 7.0 × 10 16 to 5.0 × 10 17 /cm 3 . semiconductor device.
  5. 　前記ベース層は、前記基板と前記バッファ層との積層方向において、前記トレンチと接する部分の長さが０．４μｍ以下とされている請求項１ないし４のいずれか１つに記載の炭化珪素半導体装置。 The silicon carbide semiconductor according to any one of claims 1 to 4, wherein the base layer has a length of 0.4 µm or less at a portion in contact with the trench in a stacking direction of the substrate and the buffer layer. Device.
  6. 　前記ベース層は、不純物濃度が３．０×１０１７／ｃｍ３以下とされている請求項１ないし５のいずれか１つに記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the base layer has an impurity concentration of 3.0 x 1017 / cm3 or less.
  7. 　前記第１ディープ層は、前記長手方向と交差する方向であって、前記基板の面方向に沿った幅（Ｌ１）が０．９μｍ以下とされている請求項１ないし６のいずれか１つに記載の炭化珪素半導体装置。 7. The method according to any one of claims 1 to 6, wherein the first deep layer has a width (L1) of 0.9 μm or less in a direction intersecting the longitudinal direction and along a surface direction of the substrate. The silicon carbide semiconductor device described.
  8. 　前記第１ディープ層は、前記セル部から前記外周部まで延設されている請求項７に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 7, wherein said first deep layer extends from said cell portion to said outer peripheral portion.
  9. 　隣合う前記トレンチの中心間の距離は、３．０μｍ以下とされている請求項１ないし８のいずれか１つに記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein the distance between the centers of said adjacent trenches is 3.0 µm or less.
  10. 　隣合う前記第１ディープ層の間隔（Ｌ２）は、０．７５～１．１μｍとされている請求項１ないし９のいずれか１つに記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 9, wherein an interval (L2) between said first deep layers adjacent to each other is 0.75 to 1.1 µm.
  11. 　前記ベース層、前記第１ディープ層、および前記第２ディープ層の少なくとも１つには、欠陥部が形成されている請求項１ないし１０のいずれか１つに記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 10, wherein a defect portion is formed in at least one of said base layer, said first deep layer and said second deep layer.
  12. 　前記ベース層に欠陥部（Ｄ１）が形成されており、
    　前記電流分散層は、第２導電型の不純物を含む構成とされ、欠陥部（Ｄ２）が形成されている請求項１１に記載の炭化珪素半導体装置。     A defect portion (D1) is formed in the base layer,
    12. The silicon carbide semiconductor device according to claim 11, wherein said current spreading layer includes impurities of the second conductivity type, and a defect portion (D2) is formed.
  13. 　前記電流分散層は、第２導電型の不純物濃度が１．０×１０１５／ｃｍ３以上とされている部分を有している請求項１２に記載の炭化珪素半導体装置。 13. The silicon carbide semiconductor device according to claim 12, wherein said current spreading layer has a portion having a second conductivity type impurity concentration of 1.0*10< 15 >/cm< 3 > or higher.
  14. 　ＭＯＳＦＥＴ（Ｓ１１）と還流ダイオード（Ｓ１２）とが並列に接続されたアームを有するインバータ回路であって、
    　請求項１ないし１３のいずれか１つに記載の炭化珪素半導体装置を備え、
    　前記ＭＯＳＦＥＴは、前記スイッチング素子で構成され、
    　前記還流ダイオードは、前記スイッチング素子内に構成される寄生ダイオードによって構成されているインバータ回路。     An inverter circuit having an arm in which a MOSFET (S11) and a freewheeling diode (S12) are connected in parallel,
    A silicon carbide semiconductor device according to any one of claims 1 to 13,
    The MOSFET is composed of the switching element,
    The inverter circuit, wherein the free-wheeling diode is formed by a parasitic diode formed in the switching element.
  15. 　ＭＯＳ構造のスイッチング素子が形成されるセル部（１）と、
    　前記セル部を囲む外周部（２）と、を有し、
    　前記セル部は、
    　炭化珪素からなる第１導電型の基板（１１）と、
    　前記基板上に形成され、前記基板よりも低不純物濃度とされた第１導電型のバッファ層（１２）と、
    　前記バッファ層上に形成され、前記基板よりも低不純物濃度とされた第１導電型の低濃度層（１３）と、
    　前記低濃度層上に形成され、前記基板の面方向における一方向を長手方向とする複数の線状部分を有する第２導電型の第１ディープ層（１５）と、
    　前記低濃度層上に配置され、前記第１ディープ層に挟まれた線状部分を有する第１導電型のＪＦＥＴ部（１４）と、
    　前記ＪＦＥＴ部上に配置され、前記低濃度層よりも高不純物濃度とされた第１導電型の電流分散層（１７）と、
    　前記第１ディープ層上に配置された第２導電型の第２ディープ層（１８）と、
    　前記電流分散層および前記第２ディープ層の上に配置された第２導電型のベース層（２１）と、
    　前記ベース層の表層部に形成された第１導電型の不純物領域（２２）と、
    　前記不純物領域および前記ベース層を貫通して前記電流分散層に達するトレンチ（２４）の壁面に形成されたゲート絶縁膜（２５）と、前記ゲート絶縁膜上に形成されたゲート電極（２６）とを有するトレンチゲート構造と、
    　前記不純物領域および前記ベース層と電気的に接続される第１電極（２８）と、
    　前記基板と電気的に接続される第２電極（３１）と、を備え、
    　前記ＪＦＥＴ部には、欠陥部（Ｄ）が形成されている炭化珪素半導体装置の製造方法であって、
    　前記低濃度層をエピタキシャル層で配置することと、
    　前記低濃度層の表層部にイオン注入を行うことで前記ＪＦＥＴ部を構成することを行い、
    　前記イオン注入を行うことで前記ＪＦＥＴ部に前記欠陥部を形成する炭化珪素半導体装置の製造方法。     a cell portion (1) in which switching elements of a MOS structure are formed;
    and an outer peripheral portion (2) surrounding the cell portion,
    The cell part is
    a first conductivity type substrate (11) made of silicon carbide;
    a buffer layer (12) of a first conductivity type formed on the substrate and having an impurity concentration lower than that of the substrate;
    a first conductivity type low concentration layer (13) formed on the buffer layer and having an impurity concentration lower than that of the substrate;
    a first deep layer (15) of a second conductivity type formed on the low-concentration layer and having a plurality of linear portions having a longitudinal direction in one direction in the surface direction of the substrate;
    a first conductivity type JFET portion (14) disposed on the low-concentration layer and having a linear portion sandwiched between the first deep layers;
    a first conductivity type current spreading layer (17) disposed on the JFET portion and having an impurity concentration higher than that of the low concentration layer;
    a second deep layer (18) of a second conductivity type disposed on the first deep layer;
    a second conductivity type base layer (21) disposed over the current spreading layer and the second deep layer;
    a first conductivity type impurity region (22) formed in a surface layer portion of the base layer;
    a gate insulating film (25) formed on a wall surface of a trench (24) penetrating the impurity region and the base layer and reaching the current spreading layer; and a gate electrode (26) formed on the gate insulating film. a trench gate structure having
    a first electrode (28) electrically connected to the impurity region and the base layer;
    a second electrode (31) electrically connected to the substrate;
    A method for manufacturing a silicon carbide semiconductor device in which a defective portion (D) is formed in the JFET portion,
    disposing the lightly doped layer as an epitaxial layer;
    forming the JFET portion by implanting ions into the surface layer portion of the low-concentration layer;
    A method of manufacturing a silicon carbide semiconductor device, wherein the defective portion is formed in the JFET portion by performing the ion implantation.
  16. 　前記電流分散層上に、前記ベース層を構成するベース層構成層（２１０）をエピタキシャル層で配置することと、
    　前記ベース層構成層に加速電圧を変更しながら複数回のイオン注入を行い、前記ベース層を構成すると共に前記ベース層に欠陥部（Ｄ１）を形成し、さらに前記ベース層を構成する際の不純物を前記電流分散層に入り込ませて前記電流分散層に欠陥部（Ｄ２）を形成する請求項１５に記載の炭化珪素半導体装置の製造方法。     disposing a base layer constituting layer (210) constituting the base layer as an epitaxial layer on the current spreading layer;
    Implanting ions into the base layer-constituting layer a plurality of times while changing the acceleration voltage to form the base layer, forming a defect portion (D1) in the base layer, and further forming impurities for forming the base layer. 16. The method of manufacturing a silicon carbide semiconductor device according to claim 15, wherein the defect portion (D2) is formed in the current spreading layer by causing the to enter into the current spreading layer.
  17. 　前記ベース層構成層を配置することでは、前記ベース層を構成した際の不純物濃度よりも１桁以上小さい不純物濃度とされた前記ベース層構成層を配置する請求項１５または１６に記載の炭化珪素半導体装置の製造方法。 17. The silicon carbide according to claim 15, wherein disposing the base layer-constituting layer has an impurity concentration lower by one order of magnitude or more than an impurity concentration when forming the base layer. A method of manufacturing a semiconductor device.
  18. 　前記イオン注入を行うことでは、前記エピタキシャル層を配置する際に発生し得る欠陥部よりも多量の前記欠陥部が形成される温度で行う請求項１５ないし１７のいずれか１つに記載の炭化珪素半導体装置の製造方法。 18. The silicon carbide according to any one of claims 15 to 17, wherein the ion implantation is performed at a temperature at which a larger amount of defects than those which may occur when arranging the epitaxial layer is formed. A method of manufacturing a semiconductor device.
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