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WO2020114462A1 - 基板及其制备方法、显示面板及其制备方法、显示装置 - Google Patents

基板及其制备方法、显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2020114462A1
WO2020114462A1 PCT/CN2019/123336 CN2019123336W WO2020114462A1 WO 2020114462 A1 WO2020114462 A1 WO 2020114462A1 CN 2019123336 W CN2019123336 W CN 2019123336W WO 2020114462 A1 WO2020114462 A1 WO 2020114462A1
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WO
WIPO (PCT)
Prior art keywords
substrate
groove
insulating layer
pixel
base substrate
Prior art date
Application number
PCT/CN2019/123336
Other languages
English (en)
French (fr)
Inventor
孙力
侯文军
罗程远
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/765,984 priority Critical patent/US11335879B2/en
Publication of WO2020114462A1 publication Critical patent/WO2020114462A1/zh
Priority to US17/715,270 priority patent/US11737308B2/en
Priority to US18/337,197 priority patent/US20230337459A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour

Definitions

  • the embodiments of the present disclosure relate to a substrate, a method of manufacturing the same, a display panel, a method of manufacturing the same, and a display device.
  • the display panel may include an array substrate and a counter substrate for packaging and protection opposite to the array substrate.
  • the array substrate includes functional structures such as a plurality of pixel units for display and a driving circuit that drives the pixel units to emit light.
  • the opposite substrate is combined with the array substrate through a frame sealant to provide packaging and protection for the pixel unit on the array substrate, the driving circuit and other functional structures.
  • At least one embodiment of the present disclosure provides a substrate including a display area and a peripheral area for sealing located at the periphery of the display area, the substrate includes: a base substrate; an insulating layer, a substrate provided on the base substrate Side, and located in the display area and the peripheral area for sealing; a plurality of pixel units are located on the insulating layer corresponding to the display area, wherein in the peripheral area, the insulating layer is away from the At least one groove is provided on one side of the base substrate, and the side of the groove away from the base substrate is open, and the depth direction of the groove is perpendicular to the base substrate.
  • the peripheral area for sealing is a frame sealant setting area
  • the pixel unit includes: a light emitting element layer, which is disposed on the insulating layer away from the base substrate One side, and includes a light-emitting layer.
  • the extending direction of the groove is parallel to the plane where the base substrate is located, and on a plane perpendicular to the base substrate, the longitudinal section of the groove It has a positive trapezoidal shape or an inverted trapezoidal shape.
  • the substrate provided by at least one embodiment of the present disclosure further includes a pixel defining layer on the insulating layer corresponding to the display area, and includes a plurality of pixel openings for defining the plurality of pixel units, the The light emitting layer covers at least the plurality of pixel openings, and the extending direction of the groove is the same as the extending direction of the pixel openings.
  • the shape and size of the end of the groove away from the base substrate and the shape and size of the end of the plurality of pixel openings away from the base substrate The same; or the shape of the end of the groove away from the base substrate is the same as the shape of the end of the plurality of pixel openings away from the base substrate, The size of one end is larger than the size of the end of the plurality of pixel openings away from the base substrate.
  • the insulating layer includes a plurality of the grooves in the peripheral area, the extending directions of the plurality of grooves are the same, and the plurality of grooves are located in the The periphery of the display area is arranged in multiple rows and columns, the row direction of the grooves is the same as the row direction of the plurality of pixel openings, the column direction of the grooves is the same as the column direction of the pixel openings,
  • the shape of the end of the groove away from the base substrate is the same as the shape of the end of the plurality of pixel openings away from the base substrate,
  • the size of one end is equal to the size of the end of the plurality of pixel openings away from the base substrate or the size of at least a part of the plurality of grooves away from the base substrate is larger than that of the plurality of pixel openings The size of the end away from the base substrate.
  • the size of the end of the plurality of grooves away from the base substrate is equal to the size of the end of the plurality of pixel openings away from the base substrate, so
  • the plurality of grooves have the same shape and size, the pitch of the row direction of the groove is the same as the pitch of the row direction of the pixel opening, and/or the pitch of the column direction of the groove is the same as the pixel
  • the pitch in the column direction of the opening is the same.
  • the plurality of grooves are divided into two groups according to length, the width of the plurality of grooves is equal to the width of the pixel opening, and the length of one of the two groups Is equal to the sum of the pitches of the plurality of pixel openings in the column direction, and is arranged on both sides of the display area in the row direction of the pixel openings, and the length of the groove of the other of the two groups is equal to the The length of the plurality of pixel openings, the other group is arranged on both sides of the display area in the column direction, the pitch of the plurality of grooves in the row direction and the row direction of the plurality of pixel openings Has the same pitch.
  • the surface of the insulating layer located in the peripheral region has a liquid-repellent property.
  • At least a part of the light-emitting layer is located in the groove.
  • the insulating layer includes: a first sub-insulating layer having a first groove portion, and a second sub-insulating layer stacked on the first sub-insulating layer, having An opening communicating with the first groove portion, the first groove portion and the opening constitute the groove.
  • the longitudinal section of the first groove portion is a regular trapezoid
  • the longitudinal section of the opening is an inverted trapezoid or a rectangle.
  • the material of the first sub-insulating layer includes a negative photoresist material
  • the material of the second sub-insulating layer includes a positive photoresist material or an inorganic material.
  • the substrate provided by at least one embodiment of the present disclosure further includes: a driving circuit, located on the base substrate in the display area, for driving the plurality of pixel units, wherein the insulating layer covers the Drive circuit.
  • At least one embodiment of the present disclosure provides a display panel, including: any of the above-mentioned substrates; an opposite substrate, which is arranged to face the substrate; and a frame sealant, which is arranged between the substrate and the opposite substrate In the meantime, the frame sealant covers the groove and combines the opposite substrate with the substrate.
  • At least one embodiment of the present disclosure provides a method for preparing a substrate, the substrate including a display area and a peripheral area for sealing located around the display area, the preparation method includes: providing a base substrate; Forming an insulating layer in the region and the peripheral region and on the side of the base substrate, forming at least one groove in the peripheral region and on the side of the insulating layer facing away from the base substrate, so The side of the groove away from the base substrate is open, and the depth direction of the groove is perpendicular to the base substrate, wherein the substrate includes a plurality of pixel units, and the plurality of pixel units are located in the The insulating layer corresponding to the display area.
  • the insulating layer is formed to have a liquid-repellent property at least on the surface of the peripheral region.
  • the manufacturing method provided by at least one embodiment of the present disclosure further includes: forming a pixel defining layer, the pixel defining layer includes a plurality of pixel openings for the plurality of pixel units, respectively; forming a light emitting layer, the light emitting layer At least covering the plurality of pixel openings; wherein the light emitting layer is formed by inkjet printing, spin coating or spray coating, and at least a part of the light emitting layer is formed in the groove.
  • forming the insulating layer includes: forming a first sub-insulating layer, the first sub-insulating layer having a first groove portion, and the first sub-insulating layer A second sub-insulating layer is formed thereon, the second sub-insulating layer having an opening communicating with the first groove portion, wherein the first groove portion and the opening constitute the groove.
  • the second sub-insulating layer is formed of a material having a liquid-repellent property, or the surface of the second sub-insulating layer located in the peripheral region is subjected to surface treatment , So that the surface of the second sub-insulation layer located in the peripheral region has a liquid-repellent property.
  • the surface treatment is performed using plasma of Ar, N 2 , CF 4 or O 2.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display panel, including: manufacturing the substrate, the substrate is prepared by any of the above-described manufacturing methods; providing an opposing substrate, and sealing the opposing substrate through a frame The glue is bonded to the display panel, wherein the frame sealing glue covers the groove.
  • At least one embodiment of the present disclosure provides a display device including any of the above display panels.
  • 1A is a schematic cross-sectional view of a display panel
  • 1B is a schematic plan view of a display panel
  • Figure 2 is a schematic diagram showing the entry route of impurities such as water and oxygen in the display panel
  • 3A is a schematic cross-sectional view of another display panel
  • 3B is a schematic plan view of another display panel
  • FIG. 4 is a schematic diagram of another type of entry routes for impurities such as water and oxygen in the display panel;
  • 5A is a schematic cross-sectional view of a substrate provided by some embodiments of the present disclosure.
  • 5B is a schematic cross-sectional view of a display panel provided by some embodiments of the present disclosure.
  • 5C is a schematic plan view of a display panel provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic plan view of another display panel provided by some embodiments of the present disclosure.
  • FIG. 7A is a schematic cross-sectional view of yet another substrate provided by some embodiments of the present disclosure.
  • FIG. 7B is a schematic cross-sectional view of yet another display panel provided by some embodiments of the present disclosure.
  • FIG. 7C is a schematic plan view of yet another display panel provided by some embodiments of the present disclosure.
  • FIGS 8A-8D are schematic cross-sectional views of the display panel during the preparation process provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic plan view of forming multiple display panels simultaneously according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device provided by some embodiments of the present disclosure.
  • FIGS. 1A and 1B show an ideal display panel structure.
  • the display panel 1 has a display area 1A and a peripheral area 1B for sealing the display area 1A.
  • the display panel 1 includes an array substrate 17 and a counter substrate 15, the array substrate 17 including a substrate
  • the substrate 11 and the driving circuit 12, the insulating layer 13, and the light-emitting element layer 14 on the base substrate 11, and the opposite substrate 15 are bonded to the insulating layer 13 through the frame sealant 16, thereby bonding to the array substrate and the display area 1A is sealed.
  • the frame sealant 16 completely surrounds the light emitting element layer 14, so the opposite substrate 15 and the frame sealant 16 completely isolate the light emitting element layer 14 from the external environment.
  • the light emitting element layer 14 includes a first electrode 141, a pixel defining layer 142 having a plurality of pixel openings, a light emitting layer 143 formed at least in the plurality of pixel openings, a second electrode 144, and a passivation layer 145.
  • the structure of the light-emitting layer 143 in the light-emitting element layer 14 is formed over the entire surface, as shown in FIG. 3A, so that the light-emitting layer 143 is also formed in the peripheral region 2 for sealing, resulting in the formation of the frame sealant 16 later
  • the sealant 16 is formed (for example, coated) on the light-emitting layer 143 without directly contacting the insulating layer 103.
  • the light-emitting layer 143 located in the peripheral area 1B and the upper and lower sides of the light-emitting layer 143 also form a route for impurities such as water and oxygen to enter the display area 1A, thereby reducing the display The encapsulation effect of the panel.
  • At least one embodiment of the present disclosure provides a substrate including a display area and a peripheral area for sealing located at the periphery of the display area, the substrate includes: a base substrate; an insulating layer, a substrate provided on the base substrate Side, and located in the display area and the peripheral area for sealing; a plurality of pixel units are located on the insulating layer corresponding to the display area, wherein in the peripheral area, the insulating layer is away from the At least one groove is provided on one side of the base substrate, and the side of the groove away from the base substrate is open, and the depth direction of the groove is perpendicular to the base substrate.
  • At least one embodiment of the present disclosure provides a method for preparing a substrate, the substrate including a display area and a peripheral area for sealing located at the periphery of the display area, the preparation method includes: providing a base substrate in the display area Forming an insulating layer in the peripheral region and on the side of the base substrate, forming at least one groove in the peripheral region and on the side of the insulating layer facing away from the base substrate, the The side of the groove away from the base substrate is open, and the depth direction of the groove is perpendicular to the base substrate, wherein the substrate includes a plurality of pixel units, and the plurality of pixel units are located in the display Area corresponding to the insulating layer.
  • At least one embodiment of the present disclosure provides a display panel including the above substrate.
  • At least one embodiment of the present disclosure provides a display device including the above display panel.
  • the substrate, the manufacturing method thereof, the display panel, the manufacturing method thereof, and the display device of the present disclosure will be described below through several specific embodiments.
  • FIG. 5A is a schematic cross-sectional view of the substrate 1000
  • FIG. 5C is a schematic plan view of the display panel
  • FIG. 5B is a schematic cross-sectional view of the display panel of FIG. 5C along line A-A.
  • the display panel includes an array substrate and a counter substrate.
  • the array substrate includes a base substrate, a drive circuit formed on the base substrate, an insulating layer covering the drive circuit, a light emitting element layer on the insulating layer, and the counter substrate passes
  • the frame sealant is combined with the insulating layer of the array substrate in the peripheral area to seal the display area.
  • the display area includes a plurality of pixel units.
  • the driving circuit includes a pixel driving circuit
  • the light emitting element layer includes a light emitting element
  • the pixel driving circuit drives the light emitting element electrically connected thereto to emit light.
  • the substrate 1000 includes a display area 10 and a peripheral area 11 for sealing located at the periphery of the display area.
  • the substrate 1000 includes a base substrate 101 and an insulating layer 103 provided on the substrate One side of the base substrate 101, and located in the display area and the peripheral area for sealing; a plurality of pixel units are located on the insulating layer 103 corresponding to the display area, wherein in the peripheral area, the The insulating layer is provided with at least one groove 103A on the side facing away from the base substrate, the groove 103A is open on the side away from the base substrate 101, and the depth direction of the groove 103A is perpendicular to the The base substrate is described.
  • the peripheral area for sealing is a frame sealant setting area
  • each of the plurality of pixel units includes: a light emitting element layer 104 provided on the insulating The side of the layer 103 facing away from the substrate, and includes a light emitting layer 1043.
  • the substrate 1000 further includes a pixel defining layer 1042.
  • the pixel defining layer 1042 includes a plurality of pixel openings 1042A for a plurality of pixel units.
  • the light emitting layer 1043 covers at least the plurality of pixel openings 1042A, that is, a plurality of The pixel unit shares the light-emitting layer 1043, or a plurality of pixel units are provided with respective light-emitting layers, which is not limited by the embodiments of the present disclosure.
  • the light-emitting element layer 104 corresponding to each pixel unit further includes a first electrode 1041 and a second electrode 1044 for driving the light-emitting layer 1043 to emit light, that is, the first electrode 1041 and the second electrode 1044 are sandwiched between them
  • the light emitting layer 1043 constitutes a light emitting element
  • the light emitting layer may be an organic light emitting layer or a quantum dot light emitting layer
  • the light emitting element obtained therefrom may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • the light emitting element layer 104 may further include a passivation layer 1045 covering the light emitting layer 1043 to form encapsulation and protection.
  • the extending direction of the groove is parallel to the plane where the base is located, and on a plane perpendicular to the base, the longitudinal cross section of the groove is in a normal trapezoidal shape or an inverted trapezoidal shape.
  • the longitudinal section of the groove 103A may have a positive trapezoid shape with a narrow upper width and a lower wide width (a trapezoid whose bottom side is longer than the top side), so that the groove 103A may have a larger capacity.
  • the longitudinal cross-section of the groove 103A may also be an inverted trapezoid with an upper width and a lower width (a trapezoid with a shorter bottom edge than the top edge), which facilitates liquid inflow.
  • the groove 103A may also be a rectangle with the same upper and lower widths, which is not specifically limited in the embodiments of the present disclosure.
  • the light emitting layer 1043 is formed on the entire surface, for example, by inkjet printing, spin coating, spray coating, etc. Therefore, the light emitting layer 1043 The material will flow to the peripheral area 11 for sealing.
  • the groove 103A in the insulating layer 103 can collect the material flowing to the light-emitting layer 1043 of the peripheral area 11 so that the residual light on the insulating layer 103 located in the peripheral area 11
  • the material of the layer 1043 is reduced, and the material of the light-emitting layer 1043 is not left, or the remaining parts of the material of the light-emitting layer 1043 are spaced apart from each other, so that the route of impurities such as water and oxygen into the display region 10 is cut off, and no light emission is left below
  • the material of the layer will be described as an example.
  • the light emitting layer 1043 extends at least partially into the groove 103A.
  • the surface of the insulating layer 103 located in the peripheral region 11 has liquid repellent properties.
  • the insulating layer 103 is formed of a material having a liquid-repellent property, or the surface of the insulating layer 103 located in the peripheral region 11 has a hydrophobic property by surface treatment.
  • the liquid-repellent surface of the insulating layer 103 will promote the material of the light-emitting layer 1043 to flow into the groove 103A, so that the material flowing to the light-emitting layer 1043 of the peripheral region 11 fully flows into the groove 103A and is accommodated in the groove 103A In order to ensure that no material of the light emitting layer 1043 remains on the insulating layer 103 located in the peripheral region 11.
  • the planar shape and size of the groove 103A and the pixel opening 1042A are the same, where the planar shape refers to the shape of the uppermost part of the groove and the pixel opening, that is, the concave The end of the groove away from the base and the end of the plurality of pixel openings away from the base, that is, the planar shape and size of the upper ends of the two.
  • the planar shape refers to the shape of the uppermost part of the groove and the pixel opening, that is, the concave The end of the groove away from the base and the end of the plurality of pixel openings away from the base, that is, the planar shape and size of the upper ends of the two.
  • the shape of the end of the groove away from the substrate is the same as the shape of the end of the plurality of pixel openings away from the substrate, and the plane size of the groove 103A is larger than the plane of the pixel opening 1042A
  • the size, for example, the length and/or width of the groove 103A is larger than the length and/or width of the pixel opening 1042A.
  • the planar shapes of the groove 103A and the pixel opening 1042A refer to the shapes of the groove 103A and the pixel opening 1042A shown in their plan views, that is, the shapes of the uppermost parts of the two, such as FIG. 5C and FIG. 6 shows a rectangle.
  • the planar shapes of the groove 103A and the pixel opening 1042A may also be a circle, an ellipse, or an irregular shape, which is not specifically limited in the embodiments of the present disclosure.
  • the planar dimensions of the groove 103A and the pixel opening 1042A refer to the shapes of the groove 103A and the pixel opening 1042A shown in their plan views, that is, the dimensions of the uppermost shapes of the two in the same dimension (such as length, width, etc.) ), such as the length and width dimensions or the area of the rectangle shown in FIGS. 5C and 6.
  • the plane shape and plane size of the groove 103A and the pixel opening 1042A can be selected according to actual needs.
  • the plane size of the groove 103A may also be smaller than the plane size of the pixel opening 1042A. This disclosure The embodiment does not specifically limit this.
  • the insulating layer 103 includes a plurality of grooves 103A in the peripheral area 11, and the plurality of grooves 103A are arranged around the display area 10.
  • the extending directions of the plurality of grooves are the same, the plurality of grooves are arranged in a plurality of rows and columns around the periphery of the display area, and the row direction of the grooves is the same as the row direction of the plurality of pixel openings
  • the column direction of the grooves is the same as the column direction of the pixel openings
  • the ends of the plurality of grooves away from the substrate have the same shape and are the same as the ends of the plurality of pixel openings away from the substrate
  • the size of the end of the plurality of grooves away from the substrate is equal to the size of the end of the plurality of pixel openings away from the substrate or at least a part of the plurality of grooves away from the The size of one end of the substrate is larger than the size of the end of the plurality of the pluralit
  • the size of the end of the plurality of grooves away from the substrate is equal to the size of the end of the plurality of pixel openings away from the substrate, that is, the length and width of the upper part of the plurality of grooves
  • the length and width of the upper part of the pixel opening are equal
  • the shape and size of the plurality of grooves are the same
  • the pitch of the row direction of the groove 10501 is the same as the pitch of the row direction of the pixel opening 10500 and/or
  • the pitch of the grooves in the column direction is the same as the pitch of the pixel openings in the column direction.
  • the pitch of the grooves may be regarded as grooves
  • the pitch between the pixel openings that is, as shown in FIG. 5C, the plurality of pixel openings 1042A are arranged in a first array, and the plurality of grooves 103A are arranged in a second array.
  • the first array and the second array have The same arrangement direction and the same pitch in the arrangement direction, that is, the plurality of pixel openings 1042A and the plurality of grooves 103A adopt substantially the same arrangement.
  • the length and width of the rectangle extend in the same direction
  • the pitch of the adjacent groove 103A is substantially the same as the pitch of the adjacent pixel opening 1042A, where the pitch is The distance between the edges of adjacent grooves in the row or column direction, and the pitch is the distance in the row or column direction from the center of the adjacent groove to the center.
  • the groove and the pixel opening together form an array
  • the groove and the pixel opening together form a unit of the array, and the pitch between the units is the same.
  • the pitch of the groove and the pitch of the pixel opening are the same, so that there is no need to modify the equipment and process parameters of other light-emitting functional layers such as the light-emitting layer, such as stepping pitch, nozzle pitch, etc., so that The light-emitting layer in the frame sealant setting area can all fall into the groove to achieve a good sealing effect.
  • the pitch, shape, and size of part of the grooves are the same as the pitch, shape, and size of the pixel openings, so that part of the light-emitting layer in the setting area of the frame sealant can all fall into the groove, and The sealing effect can be improved, and the embodiments of the present disclosure do not limit this.
  • the size and shape of any place of the groove is equal to the size and shape of the corresponding position of the plurality of pixel openings, for example, the size and shape of the middle depth of the groove is equal to that of the middle depth of the pixel opening
  • the size and shape can be set according to needs by those skilled in the art.
  • the second array of the plurality of grooves 103A is different from the first array of the plurality of pixel openings 1042A. Not only is the plane size of the groove 103A different from the plane size of the pixel opening 1042A, but also the section of the array The distance can also be different.
  • the plurality of grooves are divided into two groups according to length, the width of the plurality of grooves is equal to the width of the pixel opening, and the length of the groove of one of the two groups is equal to or slightly smaller than the row of the plurality of pixel openings
  • the other group is arranged on both sides of the display area in the column direction, and the pitch of the plurality of grooves in the row direction is the same as the pitch of the plurality of pixel openings in the row direction.
  • the pitch of the grooves located on the left and right edges of the pixel unit where the pitch of the groove can be regarded as the pitch between the groove and the pixel opening.
  • the plurality of grooves 103A may be arranged in an irregular row and column manner, for example, grooves 103A in adjacent rows are shifted from each other by half the length in the row direction.
  • the groove 103A located in the peripheral region 11 can collect the material of the light emitting layer 1043 formed on the insulating layer 103 located in the peripheral region 11 to avoid or reduce The material of the light emitting layer 1043 remains on the insulating layer 103 of the peripheral region 11.
  • the material of the insulating layer 103 includes inorganic materials such as SiOx, SiNx, Al2O3, or organic materials such as polyimide, polyacrylate, or phenolic resin.
  • inorganic materials such as SiOx, SiNx, Al2O3, or organic materials such as polyimide, polyacrylate, or phenolic resin.
  • organic materials such as polyimide, polyacrylate, or phenolic resin.
  • the substrate provided by the embodiment of the present disclosure further includes a base substrate 101 and a driving circuit 102.
  • the base substrate 101 is used to support the structures and devices in the display area 10 and the peripheral area 11; the driving circuit 102 is located on the base substrate 102 and is used to drive a plurality of pixel units.
  • the driving circuit 102 includes a pixel driving circuit for a pixel unit.
  • the pixel driving circuit includes thin-film transistors and capacitors and other structures, which can be formed as 2T1C (that is, two transistors and one capacitor), or can be in the form of 3T1C, such as driving light.
  • the light emitting device of the device layer can also provide functions such as compensation and reset while emitting light.
  • the driving circuit 102 further includes signal lines such as gate lines and data lines, which are not limited in the embodiments of the present disclosure.
  • the insulating layer 103 covers the driving circuit 102 to protect the driving circuit 102 and planarize the driving circuit 102.
  • the groove 103A may collect the material of the light emitting layer 1043.
  • the second electrode 1044 and the passivation layer 1045 on the light-emitting layer 1043 will also be formed over the entire surface, so the material of the second electrode 1044 and the passivation layer 1045 may also exist in the groove 103A .
  • the frame sealant 106 can be directly bonded between the insulating layer 103 and the opposite substrate 105, forming a better
  • the sealing and bonding effect can be reduced, for example, compared with the case where an undesired material remains on the insulating layer 103 of the peripheral region 11 to form a route for impurities such as water and oxygen to enter the display region, the entry path of water and oxygen can be reduced.
  • the sealant 106 may also be at least partially filled into the groove 103A. The arrangement of the groove 103A also complicates the entry path of impurities such as water and oxygen under the sealant 106, thereby further enhancing the sealing effect.
  • the insulating layer in order to increase the capacity of the groove, may adopt a double-layer structure, and the groove is formed in the double-layer structure.
  • This arrangement can further ensure that, for example, no undesired material remains on the insulating layer located in the peripheral region.
  • this setting can reduce the number of grooves provided.
  • a display panel provided by some embodiments of the present disclosure includes a substrate 1000, an opposite substrate 105, and a frame sealant 106.
  • the opposite substrate is disposed opposite to the substrate, and the frame sealant 106 is disposed at Between the substrate and the opposite substrate, for example, the groove 103A is covered, and the opposite substrate 105 and the substrate 1000 are combined in the peripheral area to form the display panel 100 and achieve sealing.
  • FIG. 7A is a schematic cross-sectional view of the substrate
  • FIG. 7B is a schematic cross-sectional view of a display panel including the substrate
  • FIG. 7C is a schematic plan view of the display panel, where FIG. 7A is a diagram. 7C is a schematic cross-sectional view of the display panel along line BB.
  • the substrate 2000 has a display area 20 and a peripheral area 21 for sealing, and the substrate 2000 includes an insulating layer 203 in the display area 20 and the peripheral area 21.
  • the insulating layer 203 includes a groove 203A in the peripheral area 21, and a light emitting element layer 204 for a plurality of pixel units (R/G/B) is formed on the insulating layer 203 in the display area 20, and the light emitting element layer 204 includes the light emitting layer 2043.
  • the insulating layer 203 includes a first sub-insulating layer 2031 and a second sub-insulating layer 2032 stacked on the first sub-insulating layer 2031.
  • the first sub-insulating layer 2031 has a first groove portion 2031A
  • the second sub-insulating layer 2032 is laminated on the first sub-insulating layer 2031, and has an opening 2032A communicating with the first groove portion 2031A, the first groove portion 2031A Together with the opening 2032A, a groove 203A is formed.
  • the longitudinal section of the first groove portion 2031A has a regular trapezoidal shape
  • the longitudinal section of the opening 2032A has an inverted trapezoidal or rectangular shape, so that the groove 203A has a larger capacity.
  • the longitudinal section of the opening 2032A is an inverted trapezoid with an upper width and a lower width
  • the longitudinal section of the first groove portion 2031A is a regular trapezoid with an upper width and a lower width.
  • the size of the lower end of the opening 2032A is substantially the same as the size of the upper end of the first groove portion 2031A
  • the resulting groove 203A has an hourglass shape in cross section.
  • the groove 203A has a larger capacity, and makes the entry path of impurities such as water, oxygen, and the like more complicated than the case shown in FIG. 5A, for example.
  • the material of the first sub-insulating layer 2031 includes a negative photoresist material, thereby facilitating the formation of a first groove portion 2031A having a larger capacity and a narrower width in the manufacturing process.
  • the material of the second sub-insulating layer 2032 includes a positive photoresist material, or includes an inorganic material.
  • negative photoresist materials include phenolic resin, etc.
  • positive photoresist materials include polyimide, polyacrylate, etc.
  • inorganic materials include SiOx, SiNx, Al2O3, etc. Since the photoresist material is exposed to a larger amount of material in the surface layer during exposure, the vertical cross-section is formed into a trapezoidal shape with oblique edges due to the difference in exposure intensity of the upper and lower parts after development.
  • the substrate further includes a pixel defining layer 2042
  • the pixel defining layer 2042 includes a plurality of pixel openings 2042A for defining a plurality of pixel units, respectively
  • the light emitting layer 2043 covers at least the plurality of pixel openings 2042A.
  • the light emitting element layer 204 further includes a first electrode 2041 and a second electrode 2044 for driving the light emitting layer 2043 to emit light, and further includes a passivation layer 2045 that may cover the light emitting layer 2043 to form encapsulation and protection.
  • the light-emitting layer 2043 is formed on the entire surface, for example, by inkjet printing, spin coating, or spray coating. Therefore, the light-emitting layer 2043 The material will flow into the peripheral area 21 for sealing.
  • the groove 203A in the insulating layer 203 can collect the material flowing to the light emitting layer 2043 of the peripheral area 21, so that the insulating layer 203 located on the peripheral area 21 does not The material of the light emitting layer 2043 will remain.
  • the light emitting layer 2043 extends at least partially into the groove 203A.
  • the surface of the insulating layer 203 located in the peripheral region 21 has liquid repellent properties.
  • the first sub-insulating layer 2031 of the insulating layer 203 is formed of a material having a liquid-repellent property, or the surface of the first sub-insulating layer 2031 located in the peripheral region 21 has a hydrophobic property by surface treatment.
  • the liquid-repellent surface of the insulating layer 203 will promote the material of the light-emitting layer 2043 to flow into the groove 203A, so that the material of the light-emitting layer 2043 flowing into the peripheral area 21 will sufficiently flow into the groove 203A to ensure that the material located in the peripheral area 21 The material of the light emitting layer 2043 does not remain on the insulating layer 203.
  • the planar shape and size of the groove 203A and the pixel opening 2042A are the same, or the planar size of the groove 203A is larger than the planar size of the pixel opening 2042A.
  • the planar shape of the groove 203A refers to the shape shown in the plan view of the second sub-insulating layer 2032 at the upper layer in the groove 203A, that is, the uppermost part of the second sub-insulating layer 2032 Planar shape
  • the planar shape of the pixel opening 2042A refers to the shape of the pixel opening 2042A shown in its plan view, that is, the shape of the uppermost part of the pixel opening, for example, the rectangular shape shown in FIG.
  • planar shapes of the groove 203A and the pixel opening 2042A may also be circular, elliptical, or irregular shapes, etc. The embodiments of the present disclosure do not specifically limit this.
  • the planar size of the groove 203A refers to the area occupied by the shape of the second sub-insulating layer 2032 located in the upper layer in the groove 203A in its plan view
  • the planar size of the pixel opening 2042A refers to the pixel opening 2042A in its
  • the dimensions of the shape shown in the plan view in the same dimension (eg, length, width, etc.), such as the length and width of the rectangle shown in FIG. 7B, or the area of the rectangle.
  • the plane shape and plane size of the groove 203A and the pixel opening 2042A may be selected according to actual needs.
  • the plane size of the groove 203A may also be smaller than the plane size of the pixel opening 2042A, The embodiments of the present disclosure do not specifically limit this.
  • the insulating layer 203 includes a plurality of grooves 203A in the peripheral area 21, and the plurality of grooves 203A are arranged around the display area 20.
  • the plurality of pixel openings 2042A are arranged in a first array
  • the plurality of grooves 203A are arranged in a second array.
  • the first array and the second array have the same arrangement direction and the same pitch in the arrangement direction. That is, the plurality of pixel openings 2042A and the plurality of grooves 203A adopt substantially the same arrangement.
  • the length and width of the rectangle extend in the same direction, and the pitch of the adjacent groove 203A is substantially the same as the pitch of the adjacent pixel opening 2042A.
  • the groove 203A in the peripheral region 21 can better collect the material of the light emitting layer 2043 formed on the insulating layer 203 in the peripheral region 21 to ensure For example, the material of the light emitting layer 2043 does not remain on the insulating layer 203 located in the peripheral region 21.
  • the substrate 2000 provided in this embodiment further includes a base substrate 201 and a driving circuit 202.
  • the base substrate 201 is used to support the display area 20 and the peripheral area 21;
  • the driving circuit 202 is located on the base substrate 202 and is used to drive a plurality of pixel units.
  • the driving circuit 202 includes a pixel driving circuit for a pixel unit.
  • the driving circuit includes thin-film transistors and capacitors and other structures, which can be formed in the form of 2T1C, 3T1C, etc. The embodiments of the present disclosure do not limit this.
  • the insulating layer 203 covers the driving circuit 202 to protect the driving circuit 202.
  • the first sub-insulating layer 2031 of the insulating layer 203 is on the driving circuit 202, and the driving circuit 202 is planarized, and the second sub-insulating layer 2032 is on the first sub-insulating layer 2031 for forming the groove 203A.
  • the display panel 200 provided by some embodiments of the present disclosure includes a substrate 2000, an opposite substrate 205, and a frame sealant 206.
  • the opposite substrate is disposed opposite to the substrate, and the frame sealant 206 is disposed between the substrate and the substrate.
  • the groove 203A is covered, and the substrate 2000 and the opposing substrate 205 are bonded together.
  • the first substrate 1000 differs from the second substrate 2000 only in the structure of the insulating layer, and the remaining components and structures are the same. Therefore, the repetitions are not listed here, and the related description in the first substrate 1000 can be referred to.
  • the groove 203A may collect the material of the light emitting layer 2043.
  • the second electrode 2044 and the passivation layer 2045 on the light-emitting layer 2043 may also be formed over the entire surface, so the materials of the second electrode 2044 and the passivation layer 2045 may also exist in the groove 203A .
  • At least one embodiment of the present disclosure provides a manufacturing method of a display panel, the manufacturing method includes forming a display area and a peripheral area for sealing, the forming the display area and the peripheral area for sealing include: in the display area and the peripheral area An insulating layer is formed, a groove is formed in the insulating layer in the peripheral area, and a light-emitting element layer for a plurality of pixel units is formed on the insulating layer in the display area, and the light-emitting element layer includes the light-emitting layer.
  • Embodiments of the present disclosure also provide a method for manufacturing a substrate, the substrate including a display area and a peripheral area for sealing located around the display area, the preparation method includes: providing a base substrate; Forming an insulating layer in the region and the peripheral region and on the side of the base substrate, forming at least one groove in the peripheral region and on the side of the insulating layer facing away from the base substrate, so The side of the groove away from the base substrate is open, and the depth direction of the groove is perpendicular to the base substrate, wherein the substrate includes a plurality of pixel units, and the plurality of pixel units are located in the The insulating layer corresponding to the display area.
  • the insulating layer is formed to have a liquid-repellent property at least on the surface of the peripheral region.
  • the manufacturing method of the substrate further includes: forming a pixel defining layer including a plurality of pixel openings respectively used for the plurality of pixel units; forming a light emitting layer, the light emitting layer covering at least the plurality of pixels An opening; wherein the light-emitting layer is formed by inkjet printing, spin coating or spray coating, and at least a part of the light-emitting layer is formed in the groove.
  • forming the insulating layer includes forming a first sub-insulating layer having a first groove portion, forming a second sub-insulating layer on the first sub-insulating layer, the second The sub-insulating layer has an opening communicating with the first groove portion, wherein the first groove portion and the opening constitute the groove.
  • the second sub-insulating layer is formed of a material with lyophobic properties, or the surface of the second sub-insulating layer located in the peripheral region is surface-treated so that the second sub-insulating layer is located
  • the surface of the peripheral area has liquid repellent properties.
  • the surface treatment is performed using plasma of Ar, N2, CF4, or O2.
  • a base substrate 201 is first provided, and then a display area 20 and a peripheral area 21 are formed in different areas of the base substrate 201.
  • the base substrate 201 uses a glass substrate, a quartz substrate, a plastic substrate, etc., which is not specifically limited in the embodiments of the present disclosure.
  • a driving circuit 202 for a plurality of pixel units in the display area 20 is formed on the base substrate 201.
  • the driving circuit 202 includes a pixel driving circuit for a pixel unit.
  • the pixel driving circuit includes thin film transistors, capacitors, and other structures.
  • the driving circuit may further include signal lines such as gate lines and data lines, which may be formed using a semiconductor manufacturing process. This disclosure The embodiment does not limit this.
  • this step includes: forming a first sub-insulating material layer on the driving circuit 202, and then patterning the first sub-insulating material layer to form a first groove Part 2031A.
  • the first sub-insulating layer 2031 is formed using a negative photoresist material, such as phenol resin.
  • patterning the first sub-insulating material layer includes exposing the first sub-insulating material layer through a reticle and then developing to form a first groove portion 2031A.
  • the first groove portion 2031A has an upper narrow and lower wide structure, and thus has a larger capacity.
  • a second sub-insulating layer 2032 may be formed on the first sub-insulating layer 2031.
  • This step includes: forming a second sub-insulating layer on the first sub-insulating layer 2031 The insulating material layer, and then patterning the second sub-insulating material layer to form an opening 2032A communicating with the first groove portion 2031A.
  • the second sub-insulating layer 2032 is formed of a positive photoresist material or an inorganic material, for example, a positive photoresist material such as polyimide or polyacrylate, or an inorganic material such as SiOx, SiNx, or Al2O3.
  • patterning the second sub-insulating material layer includes exposing and developing the second sub-insulating material layer through a reticle to form the opening 2032A.
  • patterning the second sub-insulating material layer includes forming a layer of photoresist on the second sub-insulating material layer, and then exposing the photoresist through a mask Develop to form a photoresist pattern, and then etch the second sub-insulating material layer through the photoresist pattern to form the opening 2032A.
  • the etching is, for example, dry etching or wet etching. Be limited.
  • the first groove portion 2031A and the opening 2032A constitute a groove 203A in the insulating layer 203.
  • the insulating layer 203 is formed to have liquid-repellent properties at least on the surface of the peripheral region 21.
  • the second sub-insulating layer 2032 located above the insulating layer 203 is formed of a material having a liquid-repellent property (such as the materials exemplified above), or the surface of the second sub-insulating layer 2032 located in the peripheral region 21
  • the treatment is performed so that the surface of the second sub-insulating layer 2032 located in the peripheral region 21 has liquid-repellent properties.
  • the surface of the second sub-insulating layer 2032 located in the peripheral region 21 may be surface-treated with plasma of Ar, N 2 , CF 4 or O 2 , so that the surface of the second sub-insulating layer 2032 located in the peripheral region 21 With liquid-repellent properties.
  • the second sub-insulating layer 2032 is formed of a material with liquid-repellent properties
  • the corresponding materials can be selected according to requirements
  • the surface of the second sub-insulating layer 2032 formed with a material having a liquid-repellent property may be subjected to a liquid-repellent treatment to further improve the liquid-repellent performance of the surface of the second sub-insulating layer 2032.
  • a light-emitting element layer 204 is formed on a portion of the insulating layer 203 located in the display area 20.
  • the first electrode 2041 includes a plurality of sub-electrodes corresponding to a plurality of pixel units; then a pixel defining layer 2042 is formed, the pixel defining layer 2042 includes a plurality of pixel openings for the plurality of pixel units, respectively 2042A, the plurality of pixel openings 2042A respectively expose the plurality of sub-electrodes of the first electrode 2041, the light emitting layer 2043 is formed to cover at least the plurality of pixel openings 2042A, and then the second electrode 2043 and the passivation layer 2044 are formed on the light emitting layer 2043.
  • the first electrode 2041 and the pixel defining layer 2042 can be formed by a patterning process.
  • the material of the first electrode 2041 includes metal oxides such as ITO and IZO or metals such as Ag, Al, Mo or alloys thereof, and the material of the pixel defining layer 2042 Examples include organic materials such as polyimide or inorganic materials such as silicon oxide and silicon nitride.
  • the light-emitting layer 2043 may be formed by printing such as inkjet printing, spin coating, or spray coating. Due to the fluidity of the printed ink, the material of the printed light-emitting layer 2043 also extends into the groove 203A.
  • the material of the light emitting layer 2043 is selected according to the type of light emitting element to be formed.
  • an organic light-emitting material is used, and the light-emitting layer may be a composite layer, including, for example, an electron injection sublayer, an electron transport sublayer, a light emitting sublayer, a hole transport sublayer, a hole injection sublayer, etc.; and
  • quantum dot luminescent materials are used.
  • the second electrode 2044 and the passivation layer 2044 may be formed through a mask plate by evaporation, sputtering, or deposition.
  • the material of the second electrode 2044 includes metals such as Mg, Ca, Li, or Al or alloys thereof, or conductive inorganic materials such as IZO and ZTO, or PEDOT/PSS (poly 3,4-ethylenedioxythiophene/poly Styrene sulfonate) and other conductive organic materials.
  • the material of the passivation layer 2045 includes organic materials such as polyimide or inorganic materials such as silicon oxide and silicon nitride.
  • an embodiment of the present disclosure further provides a method of manufacturing a display panel, including: manufacturing the substrate, the substrate is prepared by any of the above-described manufacturing methods; providing an opposite substrate, and applying the opposite substrate The frame sealant is combined on the display panel, wherein the frame sealant covers the groove.
  • the preparation method will be described. As shown in FIG. 8D, after the light-emitting element layer 204 is formed, the preparation method of the display panel further includes: after the preparation method of the substrate: providing an opposite substrate 206, and the opposite The substrate 206 is bonded to the substrate by a frame sealant 205.
  • the frame sealant 206 is applied to the peripheral area in a predetermined pattern to cover the groove 203A so as to at least partially fill the cover groove 203A; Type, UV curing or thermal curing can be applied to the sealant.
  • the material of the counter substrate 206 includes a glass plate, a plastic plate, or a plastic film.
  • a transparent material such as PET (polyethylene terephthalate) or PI (polyimide) may be used as the plastic material.
  • the material of 205 includes adhesive materials such as resin.
  • the groove 203A of the insulating layer 203 located in the peripheral region 21 can collect the material of the light emitting layer 2043 formed in the peripheral region 21 when the light emitting element layer 204 is formed. Therefore, the insulating layer 203 located in the peripheral region 21 For example, no undesired material remains on the part.
  • the frame sealant 205 can directly combine the opposite substrate 206 with the insulating layer 103, thereby having a better packaging effect.
  • the second electrode 2044 and/or the passivation layer 2044 can also be formed on the entire surface by evaporation, sputtering, or deposition.
  • the groove 203A further includes the second electrode 2044 and /Or the forming material of the passivation layer 2044.
  • the groove 203A may collect undesired materials formed on the portion of the insulating layer 203 located in the peripheral region 21.
  • the preparation method can be used to use one motherboard to prepare multiple display panels at the same time, and these display panels can have the same shape or different shapes, and then these display panels can be cut through a cutting process Separated from each other.
  • three display panels are prepared on the same motherboard, including an oval display panel on the upper side and two rectangular display panels on the lower side.
  • the frame sealant 206 surrounds the display area 20, covering the grooves in the peripheral area.
  • the display panel may also have an irregular shape.
  • the material of the functional layers such as the light emitting layer 2043 is also not It will remain on the portion of the insulating layer 203 located in the peripheral area 21, so as not to affect the sealing effect of the frame sealant 205. Therefore, the display panel prepared by the preparation method provided by the embodiments of the present disclosure has a better encapsulation effect, and a plurality of display panels can be formed at the same time by the preparation method to improve production efficiency.
  • the display device 300 includes any display panel provided by an embodiment of the present disclosure, which is shown as the display panel 200 in the figure.
  • the display device 300 may be any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.
  • the embodiments of the present disclosure do not limit this.

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Abstract

一种基板及其制备方法、显示面板及其制备方法、显示装置。该基板(1000,2000)包括显示区(10)和位于所述显示区(10)周边的用于密封的周边区(11)，所述基板(1000,2000)包括：衬底基板(101)；绝缘层(103)，设置在所述衬底基板(101)的一侧，且位于所述显示区(10)和用于密封的周边区(11)；多个像素单元，位于所述显示区(10)对应的所述绝缘层(103)上，在所述周边区(11)中，所述绝缘层(103)在背离所述衬底基板(101)的一侧设置有至少一个凹槽(103A)，所述凹槽(103A)远离所述衬底基板(101)的一侧是开口的，所述凹槽(103A)的深度方向垂直于所述衬底基板(101)。包括该基板的显示面板具有较好的封装效果。

Description

基板及其制备方法、显示面板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种基板及其制备方法、显示面板及其制备方法、显示装置。
背景技术
显示面板可以包括阵列基板以及与阵列基板相对的用于封装与保护的对置基板。阵列基板包括用于显示的多个像素单元以及驱动这些像素单元发光的驱动电路等功能结构。对置基板通过封框胶与阵列基板结合，以对阵列基板上的像素单元以及驱动电路等功能结构提供封装与保护。
发明内容
本公开至少一实施例提供一种基板，包括显示区和位于所述显示区周边的用于密封的周边区，所述基板包括：衬底基板；绝缘层，设置在所述衬底基板的一侧，且位于所述显示区和用于密封的周边区；多个像素单元，位于所述显示区对应的所述绝缘层上，其中在所述周边区中，所述绝缘层在背离所述衬底基板的一侧设置有至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板。
例如，本公开至少一实施例提供的基板中，所述用于密封的周边区是封框胶设置区域，所述像素单元包括：发光元件层，设置在所述绝缘层的背离衬底基板的一侧，且包括发光层。
例如，本公开至少一实施例提供的基板中，所述凹槽的延伸方向平行于所述衬底基板所在的平面，在垂直于所述衬底基板的平面上，所述凹槽的纵截面呈正梯形或者倒梯形。
例如，本公开至少一实施例提供的基板还包括：像素界定层，位于所述显示区对应的所述绝缘层上，且包括用于限定所述多个像素单元的多个像素开口，所述发光层至少覆盖所述多个像素开口，所述凹槽的延伸方向与所述像素开口的延伸方向相同。
例如，本公开至少一实施例提供的基板中，所述凹槽的远离所述衬底基板的一端的形状和尺寸与所述多个像素开口的远离所述衬底基板的一端的 形状和尺寸相同；或者所述凹槽的远离所述衬底基板的一端的形状与所述多个像素开口的远离所述衬底基板的一端的形状相同，所述凹槽的远离所述衬底基板的一端的尺寸大于所述多个像素开口的远离所述衬底基板的一端的尺寸。
例如，本公开至少一实施例提供的基板中，所述绝缘层在所述周边区中包括多个所述凹槽，所述多个凹槽的延伸方向相同，所述多个凹槽在所述显示区的周边排布成多行和多列，所述凹槽的行方向与所述多个像素开口的行方向相同，所述凹槽的列方向与所述像素开口的列方向相同,其中所述凹槽的远离所述衬底基板的一端的形状与所述多个像素开口的远离所述衬底基板的一端的形状相同，所述多个凹槽的远离所述衬底基板的一端的尺寸等于所述多个像素开口的远离所述衬底基板的一端的尺寸或者所述多个凹槽中至少一部分的远离所述衬底基板的一端的尺寸大于所述多个像素开口的远离所述衬底基板的一端的尺寸。
例如，本公开至少一实施例提供的基板中，所述多个凹槽的远离所述衬底基板的一端的尺寸等于所述多个像素开口的远离所述衬底基板的一端的尺寸，所述多个凹槽的形状和大小相同，所述凹槽的行方向的节距与所述像素开口的行方向的节距相同和/或所述凹槽的列方向的节距与所述像素开口的列方向的节距相同。
例如，本公开至少一实施例提供的基板中，所述多个凹槽按照长度分成两组，所述多个凹槽的宽度等于所述像素开口的宽度，两组之一的凹槽的长度等于所述多个像素开口的沿列方向节距之和，且沿像素开口的行方向排布在所述显示区的两侧，所述两组中另一组的凹槽的长度等于所述多个像素开口的长度，所述另外一组排布在所述显示区的在列方向的两侧，所述多个凹槽沿行方向的节距与所述多个像素开口的沿行方向的节距相同。
例如，本公开至少一实施例提供的基板中，所述绝缘层的位于所述周边区的表面具有疏液性质。
例如，本公开至少一实施例提供的基板中，所述发光层的至少一部分位于所述凹槽中。
例如，本公开至少一实施例提供的基板中，所述绝缘层包括：第一子绝缘层，具有第一凹槽部分，第二子绝缘层，层叠在所述第一子绝缘层上，具有与所述第一凹槽部分连通的开口，所述第一凹槽部分和所述开口构成所述 凹槽。
例如，本公开至少一实施例提供的基板中，所述第一凹槽部分的纵截面呈正梯形，所述开口的纵截面呈倒梯形或者矩形。
例如，本公开至少一实施例提供的基板中，所述第一子绝缘层的材料包括负性光刻胶材料，所述第二子绝缘层的材料包括正性光刻胶材料或无机材料。
例如，本公开至少一实施例提供的基板还包括：驱动电路，在所述显示区中位于所述衬底基板上，用于驱动所述多个像素单元，其中，所述绝缘层覆盖所述驱动电路。
本公开至少一实施例提供一种显示面板，包括：以上任意所述的基板；对置基板，设置为与所述基板相对；以及封框胶，设置在所述基板与所述对置基板之间，所述封框胶覆盖所述凹槽，将所述对置基板与所述基板结合。
本公开至少一实施例提供一种基板的制备方法，所述基板包括显示区和位于所述显示区周边的用于密封的周边区，所述制备方法包括：提供衬底基板；在所述显示区和所述周边区中且在所述衬底基板的一侧形成绝缘层，在所述周边区中且在所述绝缘层在背离所述衬底基板的一侧形成至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板，其中所述基板包括多个像素单元，所述多个像素单元位于所述显示区对应的所述绝缘层上。
例如，本公开至少一实施例提供的制备方法中，所述绝缘层形成为至少在所述周边区的表面具有疏液性质。
例如，本公开至少一实施例提供的制备方法，还包括：形成像素界定层，所述像素界定层包括分别用于所述多个像素单元的多个像素开口；形成发光层，所述发光层至少覆盖所述多个像素开口；其中，采用喷墨打印、旋涂或者喷涂的方式形成所述发光层，并且所述发光层的至少一部分形成于所述凹槽中。
例如，本公开至少一实施例提供的制备方法中，形成所述绝缘层包括：形成第一子绝缘层，所述第一子绝缘层具有第一凹槽部分，在所述第一子绝缘层上形成第二子绝缘层，所述第二子绝缘层具有与所述第一凹槽部分连通的开口，其中，所述第一凹槽部分和所述开口构成所述凹槽。
例如，本公开至少一实施例提供的制备方法中，所述第二子绝缘层采用 具有疏液性质的材料形成，或者对所述第二子绝缘层的位于所述周边区的表面进行表面处理，以使所述第二子绝缘层的位于所述周边区的表面具有疏液性质。
例如，本公开至少一实施例提供的制备方法中，采用Ar、N 2、CF 4或O2的等离子体进行所述表面处理。
本公开至少一实施例提供一种显示面板的制备方法，包括：制造所述基板，所述基板由以上任意所述的制备方法制备；提供对置基板，且将所述对置基板通过封框胶结合在显示面板上，其中，所述封框胶覆盖所述凹槽。
本公开至少一实施例提供一种显示装置，包括上述任一的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示面板的截面示意图；
图1B为一种显示面板的平面示意图；
图2为一种显示面板中水、氧等杂质进入路线的示意图；
图3A为另一种显示面板的截面示意图；
图3B为另一种显示面板的平面示意图；
图4为另一种显示面板中水、氧等杂质进入路线的示意图；
图5A为本公开一些实施例提供的一种基板的截面示意图；
图5B为本公开一些实施例提供的一种显示面板的截面示意图；
图5C为本公开一些实施例提供的一种显示面板的平面示意图；
图6为本公开一些实施例提供的另一种显示面板的平面示意图；
图7A为本公开一些实施例提供的再一种基板的截面示意图；
图7B为本公开一些实施例提供的再一种显示面板的截面示意图；
图7C为本公开一些实施例提供的再一种显示面板的平面示意图；
图8A-8D为本公开一些实施例提供的显示面板在制备过程中的截面示意图；
图9为本公开一些实施例提供的同时形成多个显示面板的平面示意图；
图10为本公开一些实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常来说，在显示面板的一种结构中，对置基板和阵列基板通过封框胶彼此结合，从而对置基板以及封框胶将阵列基板的显示区中的像素单元以及驱动电路等功能结构与外界环境完全隔离，以避免水、氧等杂质进入显示区，由此延长显示面板的工作寿命。例如，图1A和图1B示出了一种理想的显示面板结构。
如图1A和图1B所示，显示面板1具有显示区1A和用于将显示区1A密封的周边区1B，该显示面板1包括阵列基板17和对置基板15，该阵列基板17包括衬底基板11以及在衬底基板11上的驱动电路12、绝缘层13、发光元件层14，对置基板15通过封框胶16结合在绝缘层13上，从而结合到阵列基板上，并对显示区1A进行密封。如图1A和图1B所示，封框胶16完全围绕发光元件层14，因此对置基板15和封框胶16将发光元件层14与外界环境完全隔离。
在上述结构下，如图2所示，显示面板1中仅在封框胶16的上下两侧存在水、氧等杂质进入显示区1A的路线(如封框胶16上下两侧的箭头所示)，因此该显示面板1具有较好的封装效果。
但是在实际制备工艺中，如图3A和图3B所示，发光元件层14的部分功能层(例如发光层、公共电极等)往往采用整面形成的方式，因此既会覆盖显示区也可能覆盖至周边区。此时，在一些示例中，如图3B所示，可以在一次制备工艺中形成多个显示面板。例如，发光元件层14包括第一电极141、具有多个像素开口的像素界定层142、至少形成在多个像素开口中的发光层143、第二电极144以及钝化层145等结构。例如，发光元件层14中的发光层143等结构采用整面形成的方式，如图3A所示，使得用于密封的周边区2中也形成有发光层143，导致后期采用封框胶16形成对置基板15时，封框胶16形成(例如涂敷)在发光层143上，而不会与绝缘层103直接接触。
如图4所示，在上述情况下，显示面板中在位于周边区1B的发光层143以及发光层143的上下两侧也形成了水、氧等杂质进入显示区1A的路线，从而降低了显示面板的封装效果。
本公开至少一实施例提供一种基板，包括显示区和位于所述显示区周边的用于密封的周边区，所述基板包括：衬底基板；绝缘层，设置在所述衬底基板的一侧，且位于所述显示区和用于密封的周边区；多个像素单元，位于所述显示区对应的所述绝缘层上，其中在所述周边区中，所述绝缘层在背离所述衬底基板的一侧设置有至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板。
本公开至少一实施例提供一种基板的制备方法，所述基板包括显示区和位于所述显示区周边的用于密封的周边区，所述制备方法包括：提供衬底基板在所述显示区和所述周边区中且在所述衬底基板的一侧形成绝缘层，在所述周边区中且在所述绝缘层在背离所述衬底基板的一侧形成至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板，其中所述基板包括多个像素单元，所述多个像素单元位于所述显示区对应的所述绝缘层上。
本公开至少一实施例提供一种显示面板，该显示面板包括上述基板。
本公开至少一实施例提供一种显示装置，该显示装置包括上述显示面板。
下面通过几个具体的实施例对本公开的基板及其制备方法、显示面板及其制备方法、显示装置进行说明。
本公开至少一实施例提供一种显示面板，图5A为该基板1000的截面示意图，图5C为该显示面板的平面示意图，其中图5B是图5C的显示面板的 沿A-A线的截面示意图。
该显示面板包括阵列基板和对置基板，该阵列基板包括衬底基板、形成在衬底基板上的驱动电路、覆盖驱动电路的绝缘层、在绝缘层上的发光元件层，并且对置基板通过封框胶在周边区结合在阵列基板的绝缘层上，对显示区进行密封。显示区包括多个像素单元，在每个像素单元中，驱动电路包括像素驱动电路，发光元件层包括发光元件，像素驱动电路驱动与之电连接的发光元件发光。
如图5B和5C所示，基板1000包括显示区10和位于所述显示区周边的用于密封的周边区11，所述基板1000包括：衬底基板101；绝缘层103，设置在所述衬底基板101的一侧，且位于所述显示区和用于密封的周边区；多个像素单元，位于所述显示区对应的所述绝缘层103上，其中在所述周边区中，所述绝缘层在背离所述衬底基板的一侧设置有至少一个凹槽103A，所述凹槽103A远离所述衬底基板101的一侧是开口的，所述凹槽103A的深度方向垂直于所述衬底基板。
例如，本实施例中，所述用于密封的周边区是封框胶设置区域，所述多个像素单元(R/G/B)的每个包括：发光元件层104，设置在所述绝缘层103的背离基底的一侧，且包括发光层1043。
例如，本实施例中，基板1000还包括像素界定层1042，像素界定层1042包括分别用于多个像素单元的多个像素开口1042A，发光层1043至少覆盖多个像素开口1042A，也即多个像素单元共用该发光层1043，或者多个像素单元单独设置有各自的发光层，本公开的实施例不对此进行限制。例如，对应于每个像素单元发光元件层104还包括用于驱动发光层1043发光的第一电极1041以及第二电极1044，也即第一电极1041以及第二电极1044与夹置在它们之间的发光层1043构成发光元件，该发光层可以为有机发光层或量子点发光层，由此所得到的发光元件可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。并且，发光元件层104还可以包括覆盖在发光层1043上的钝化层1045以形成封装与保护。
例如，本实施例中，所述凹槽的延伸方向平行于所述基底所在的平面，在垂直于所述基底的平面上，所述凹槽的纵截面呈正梯形或者倒梯形。
例如，凹槽103A的纵截面可以呈上窄下宽的正梯形(底边比顶边长的梯形)，从而凹槽103A可以具有较大的容量。另外，如图5A所示，凹槽103A 的纵截面也可以为上宽下窄的倒梯形(底边比顶边短的梯形)，从而有利于液体流入。在一些实施例中，凹槽103A也可以为上下宽度一致的矩形等，本公开的实施例对此不做具体限定。
例如，本公开的一些实施例提供的显示面板在制备的过程中，发光层1043采用整面形成的方式，例如采用喷墨打印、旋涂、喷涂等印刷的方式形成，因此，发光层1043的材料会流淌到用于密封的周边区11，此时，绝缘层103中的凹槽103A可收集流淌到周边区11的发光层1043的材料，使得位于周边区11的绝缘层103上残留的发光层1043的材料减少，不会残留发光层1043的材料，或发光层1043的材料的残留部分彼此间隔开，因此使得水、氧等杂质进入显示区10的路线被断开，以下不会残留发光层的材料为例进行说明。此时，在一些实施例中，发光层1043至少部分延伸至凹槽103A中。
例如，本实施例中，绝缘层103的位于周边区11的表面具有疏液性质。例如，绝缘层103采用具有疏液性质的材料形成，或者绝缘层103的位于周边区11的表面通过表面处理从而具有疏水性质。此时，绝缘层103的具有疏液性质的表面会促进发光层1043的材料流入凹槽103A，使得流淌到周边区11的发光层1043的材料充分流入凹槽103A，容纳于凹槽103A之中，以保证位于周边区11的绝缘层103上不会残留发光层1043的材料。
例如，在一些实施例中，如图5B所示，凹槽103A与像素开口1042A的平面形状和尺寸相同，这里的平面形状是指凹槽和像素开口最上部的形状，也就是，所述凹槽的远离所述基底的一端以及所述多个像素开口的远离所述基底的一端，即，二者的上端的平面形状及尺寸。或者如图6所示，所述凹槽的远离所述基底的一端的形状与所述多个像素开口的远离所述基底的一端的形状相同，凹槽103A的平面尺寸大于像素开口1042A的平面尺寸，例如凹槽103A的长度和/或宽度大于像素开口1042A的长度和/或宽度。本公开的实施例中，凹槽103A与像素开口1042A的平面形状指的是凹槽103A和像素开口1042A在其平面图中所示出的形状，即，二者最上部的形状，例如图5C和图6示出的为长方形，在其他实施例中，凹槽103A与像素开口1042A的平面形状也可以为圆形、椭圆形或者不规则形状等，本公开的实施例对此不做具体限定。凹槽103A与像素开口1042A的平面尺寸指的是凹槽103A和像素开口1042A在其平面图中所示出的形状，即，二者最上部的形状在相同维度上的尺寸(例如长度、宽度等)，例如图5C和图6示出的长方形的长和宽 的尺寸或者长方形的面积。本实施例中，凹槽103A与像素开口1042A的平面形状和平面尺寸可以根据实际需求进行选择，例如在一些实施例中，凹槽103A的平面尺寸也可以小于像素开口1042A的平面尺寸，本公开的实施例对此不做具体限定。
例如，在一些实施例中，绝缘层103在周边区11中包括多个凹槽103A，多个凹槽103A围绕显示区10排布。所述多个凹槽的延伸方向相同，所述多个凹槽在所述显示区的周边排布成多行和多列，所述凹槽的行方向与所述多个像素开口的行方向相同，所述凹槽的列方向与所述像素开口的列方向相同，所述多个凹槽的远离所述基底的一端的形状相同且与所述多个像素开口的远离所述基底的一端的形状相同，所述多个凹槽的远离所述基底的一端的尺寸均等于所述多个像素开口的远离所述基底的一端的尺寸或者所述多个凹槽中至少一部分的远离所述基底的一端的尺寸大于所述多个像素开口的远离所述基底的一端的尺寸，例如，一部分的尺寸等于像素开口，另一部分的尺寸大于或小于像素开口；或者凹槽的全部尺寸均大于或均小于像素开口；一部分的尺寸等于像素开口，一部分小于像素开口，其余部分大于像素开口。
例如，如图5B所示，多个凹槽的远离所述基底的一端的尺寸等于所述多个像素开口的远离所述基底的一端的尺寸，即，多个凹槽的上部的长度和宽度与像素开口的上部的长度和宽度相等，所述多个凹槽的形状和大小相同，所述凹槽的行方向的节距10501与所述像素开口的行方向的节距10500相同和/或所述凹槽的列方向的节距与所述像素开口的列方向的节距相同，对于位于像素单元左右两侧边缘的凹槽的节距，此处凹槽的节距可以认为是凹槽与像素开口之间的节距，也就是，如图5C所示，多个像素开口1042A呈第一阵列排布，多个凹槽103A呈第二阵列排布，第一阵列和第二阵列具有相同排布方向以及在排布方向上具有相同的节距，即多个像素开口1042A和多个凹槽103A采用基本相同的排布方式。例如，凹槽103A与像素开口1042A的平面形状为长方形时，长方形的长和宽的延伸方向相同，并且相邻的凹槽103A的间距与相邻的像素开口1042A的间距基本相同，这里间距是相邻凹槽边缘在行方向或列方向之间的距离，节距是相邻凹槽的中心到中心的在行方向或列方向上的距离。从平面图上看，凹槽和像素开口共同构成阵列，凹槽和像素开口共同构成阵列的单元，单元之间的节距相同。从平面图 上看，凹槽的节距和像素开口的节距相同，从而，不需要改造发光层等其他发光功能层的设备以及工艺参数，例如，步进节距、喷嘴节距等，使得在封框胶设置区域中的发光层能够全部落入凹槽中，实现良好的密封效果。
备选地，可以是部分凹槽的节距、形状、尺寸与像素开口的节距、形状、尺寸相同，从而能够使得封框胶设置区域中的部分发光层能够全部落入凹槽中，也能够改善密封效果，本公开的实施例并不对此进行限制。
备选地，可以是凹槽的任意处的尺寸和形状等于所述多个像素开口的对应位置处的尺寸和形状，例如，凹槽中间深度处的尺寸和形状等于像素开口的中间深度处的尺寸和形状，本领域的技术人员可根据需要而设定。
又例如，如图6所示，多个凹槽103A的第二阵列与多个像素开口1042A的第一阵列不同，不但凹槽103A的平面尺寸不同于像素开口1042A的平面尺寸，而且阵列的节距也可以不同。所述多个凹槽按照长度分成两组，所述多个凹槽的宽度等于所述像素开口的宽度，两组之一的凹槽的长度等于或者略小于所述多个像素开口的沿列方向节距之和，且沿像素开口的行方向排布在所述显示区的两侧，所述两组中另一组的凹槽的长度等于或大于所述多个像素开口的长度，所述另外一组排布在所述显示区的在列方向的两侧，所述多个凹槽沿行方向的节距与所述多个像素开口的沿行方向的节距相同，这里，对于位于像素单元左右两侧边缘的凹槽的节距，此处凹槽的节距可以认为是凹槽与像素开口之间的节距。
备选地，在包括多个凹槽103A的第二阵列中，多个凹槽103A可以以非规则行列的方式排布，例如相邻行中的凹槽103A在行方向彼此错开一半长度。
在上述设置下，当在像素开口1042A中形成发光层1043时，位于周边区11的凹槽103A可以收集形成在位于周边区11的绝缘层103上的发光层1043的材料，以避免或减少位于周边区11的绝缘层103上残留发光层1043的材料。
例如，本公开的实施例中，绝缘层103的材料包括SiOx、SiNx、Al2O3等无机材料，或者包括聚亚酰胺、聚丙烯酸酯或酚醛树脂等有机材料，本公开的实施例对此不做具体限定。
如图5A所示，例如，本公开的实施例提供的基板还包括衬底基板101和驱动电路102。衬底基板101用于支撑显示区10和周边区11中的结构和 器件；驱动电路102位于衬底基板102上，用于驱动多个像素单元。例如，驱动电路102包括用于像素单元的像素驱动电路，像素驱动电路包括薄膜晶体管和电容等结构，可形成为2T1C(即两个晶体管一个电容)，也可以为3T1C等形式，例如在驱动发光器件层的发光器件发光的同时还可以提供补偿、复位等功能，该驱动电路102还包括栅线、数据线等信号线，本公开的实施例对此不做限定。
例如，绝缘层103覆盖驱动电路102，以对驱动电路102进行保护，且平坦化驱动电路102。
本公开的一些实施例提供的显示面板中，由于绝缘层103在周边区11中包括凹槽103A，凹槽103A可收集发光层1043的材料。例如，在一些实施例中，发光层1043上的第二电极1044和钝化层1045也会采用整面形成的方式，因此凹槽103A中也可能存在第二电极1044和钝化层1045的材料。由此，周边区11的绝缘层103上例如不会残留发光层1043的材料等不希望的材料，从而封框胶106可以直接粘结在绝缘层103和对置基板105之间，形成更好的密封和结合效果，例如相比于周边区11的绝缘层103上残留不希望的材料而形成水、氧等杂质进入显示区的路线的情形来说，可减少水、氧等的进入路径。另一方面，封框胶106也可以至少部分填充到凹槽103A中，凹槽103A的设置也将封框胶106下方的水、氧等杂质的进入路径复杂化，从而进一步增强了密封效果。
例如，在一些实施例中，为了提高凹槽的容量，绝缘层可以采用双层结构，并且在双层结构中形成凹槽。该设置可以进一步保证位于周边区的绝缘层上例如不会残留不希望的材料。另一方面，在多个凹槽的总容量一定的情况下，该设置可以减少凹槽的设置数量。
例如，如图5B所示，本公开的一些实施例提供的显示面板包括基板1000、对置基板105和封框胶106，对置基板，设置为与所述基板相对，封框胶106设置在所述基板与所述对置基板之间，例如覆盖凹槽103A，且在周边区中将对置基板105和基板1000结合以形成显示面板100且实现密封。
例如，本公开至少一实施例提供一种基板2000，图7A为该基板的截面示意图，图7B为包括该基板的显示面板的截面示意图，图7C为显示面板的平面示意图，其中图7A是图7C中的显示面板沿B-B线的截面示意图。
如图7A、图7B和图7C所示，基板2000具有显示区20和用于密封的 周边区21，且基板2000包括在显示区20和周边区21中的绝缘层203。绝缘层203在周边区21中包括凹槽203A，在显示区20中于绝缘层203上形成有用于多个像素单元(R/G/B)的发光元件层204，发光元件层204包括发光层2043。
例如，绝缘层203包括第一子绝缘层2031和层叠在第一子绝缘层2031上的第二子绝缘层2032。第一子绝缘层2031具有第一凹槽部分2031A，第二子绝缘层2032层叠在第一子绝缘层2031上，且具有与第一凹槽部分2031A连通的开口2032A，第一凹槽部分2031A和开口2032A一起构成凹槽203A。例如，第一凹槽部分2031A的纵截面呈正梯形，开口2032A的纵截面呈倒梯形或者矩形，使得凹槽203A具有较大的容量。
例如，如图7A所示，开口2032A的纵截面为上宽下窄的倒梯形，而第一凹槽部分2031A的纵截面为上窄下宽的正梯形。例如，开口2032A的下端尺寸与第一凹槽部分2031A的上端尺寸基本相同，由此所得得到的凹槽203A的截面呈沙漏形。本实施例中，凹槽203A具有更大的容量，而且使得水、氧等杂质的进入路径与例如图5A所示的情形相比更加复杂化。
在一些实施例中，例如，第一子绝缘层2031的材料包括负性光刻胶材料，从而有利于在制备过程中形成上窄下宽的具有更大容量的第一凹槽部分2031A。第二子绝缘层2032的材料包括正性光刻胶材料，或包括无机材料。例如，负性光刻胶材料包括酚醛树脂等，正性光刻胶材料包括聚亚酰胺、聚丙烯酸酯等，无机材料包括SiOx、SiNx、Al2O3等。由于光刻胶材料在曝光时位于表层的材料的曝光量更大，因此在显影后由于上下部位曝光强度的不同而形成纵截面为具有斜边的梯形形状。
例如，本公开的一些实施例中，基板还包括像素界定层2042，像素界定层2042包括分别用于限定多个像素单元的多个像素开口2042A，发光层2043至少覆盖多个像素开口2042A。例如，发光元件层204还包括用于驱动发光层2043发光的第一电极2041以及第二电极2044，并且还包括可以覆盖在发光层2043上的钝化层2045以形成封装与保护。
例如，本公开的一些实施例提供的显示面板在制备的过程中，发光层2043采用整面形成的方式，例如采用喷墨打印、旋涂或者喷涂等印刷的方式形成，因此，发光层2043的材料会流淌到用于密封的周边区21中，此时，绝缘层203中的凹槽203A可收集流淌到周边区21的发光层2043的材料，使得位于 周边区21的绝缘层203上例如不会残留发光层2043的材料。此时，在一些实施例中，发光层2043至少部分延伸至凹槽203A中。
例如，在本公开的一些实施例中，绝缘层203的位于周边区21的表面具有疏液性质。例如，绝缘层203的第一子绝缘层2031采用具有疏液性质的材料形成，或者第一子绝缘层2031的位于周边区21的表面通过表面处理从而具有疏水性质。此时，绝缘层203的具有疏液性质的表面会促进发光层2043的材料流入凹槽203A，使得流淌到周边区21的发光层2043的材料充分流入凹槽203A，以保证位于周边区21的绝缘层203上不会残留发光层2043的材料。
例如，在本公开的一些实施例中，凹槽203A与像素开口2042A的平面形状和尺寸相同，或者凹槽203A的平面尺寸大于像素开口2042A的平面尺寸。本实施例中，凹槽203A的平面形状指的是凹槽203A中位于上层的第二子绝缘层2032在其平面图中所示出的形状，也就是，第二子绝缘层2032的最上部的平面形状，像素开口2042A的平面形状指的是像素开口2042A在其平面图中所示出的形状，也就是，像素开口的最上部的形状，例如图7C示出的为长方形，在其他实施例中，凹槽203A与像素开口2042A的平面形状也可以为圆形、椭圆形或者不规则形状等，本公开的实施例对此不做具体限定。凹槽203A的平面尺寸指的是凹槽203A中位于上层的第二子绝缘层2032在其平面图中所示出的形状所占有的面积，像素开口2042A的平面尺寸指的是像素开口2042A在其平面图中所示出的形状在相同维度上的尺寸(例如长、宽等)，例如图7B示出的长方形的长和宽的尺寸，或者长方形的面积。本公开的实施例中，凹槽203A与像素开口2042A的平面形状和平面尺寸可以根据实际需求进行选择，例如在一些实施例中，凹槽203A的平面尺寸也可以小于像素开口2042A的平面尺寸，本公开的实施例对此不做具体限定。
例如，在一些实施例中，绝缘层203在周边区21中包括多个凹槽203A，多个凹槽203A围绕显示区20排布。例如，多个像素开口2042A呈第一阵列排布，多个凹槽203A呈第二阵列排布，第一阵列和第二阵列具有相同排布方向以及在排布方向上具有相同的节距，即多个像素开口2042A和多个凹槽203A采用基本相同的排布方式。例如，凹槽203A与像素开口2042A的平面形状为长方形时，长方形的长和宽的延伸方向相同，并且相邻的凹槽203A的间距与相邻的像素开口2042A的间距基本相同。
在上述设置下，当在像素开口2042A中形成发光层2043时，位于周边区21的凹槽203A可以更好地收集形成在位于周边区21的绝缘层203上的发光层2043的材料，以保证位于周边区21的绝缘层203上例如不会残留发光层2043的材料。
例如，本实施例提供的基板2000还包括衬底基板201和驱动电路202。衬底基板201用于支撑显示区20和周边区21；驱动电路202位于衬底基板202上，用于驱动多个像素单元。例如，驱动电路202包括用于像素单元的像素驱动电路，该驱动电路包括薄膜晶体管和电容等结构，可形成为2T1C、3T1C等形式，本公开的实施例对此不做限定。例如，绝缘层203覆盖驱动电路202，以对驱动电路202进行保护。例如，绝缘层203的第一子绝缘层2031在驱动电路202上，且平坦化驱动电路202，第二子绝缘层2032在第一子绝缘层2031上，用于形成凹槽203A。
例如，本公开的一些实施例提供的显示面板200包括基板2000、对置基板205和封框胶206，对置基板，设置为与所述基板相对，封框胶206设置在所述基板与所述对置基板之间，例如，覆盖凹槽203A，且将基板2000和对置基板205结合在一起。
第一基板1000与第二基板2000的不同之处仅在于：绝缘层的结构，其余部件和结构均相同，因此，重复之处这里并未列出，可以参照第一基板1000中的相关描述。
本公开的一些实施例提供的基板、显示面板中，由于绝缘层203在周边区21中包括具有双层结构的凹槽203A，凹槽203A可收集发光层2043的材料。例如，在一些实施例中，发光层2043上的第二电极2044和钝化层2045也会采用整面形成的方式，因此凹槽203A中也可能存在第二电极2044和钝化层2045的材料。由此，周边区21的绝缘层203上例如不会残留发光层2043的材料等不希望的材料，从而封框胶206可以直接粘结在绝缘层203和对置基板205之间，形成更好的密封，例如相比于周边区21的绝缘层203上残留不希望的材料来说，可减少水、氧等杂质的进入路径。另一方面，凹槽203A的设置也将封框胶206下方的水、氧等杂质的进入路径复杂化，从而进一步增强了密封效果。
本公开至少一实施例提供一种显示面板的制备方法，该制备方法包括形成显示区和用于密封的周边区，该形成显示区和用于密封的周边区包括：在 显示区和周边区中形成绝缘层，在周边区中在绝缘层中形成凹槽，在显示区中在绝缘层上形成用于多个像素单元的发光元件层，发光元件层包括发光层。
本公开的实施例还提供一种基板的制备方法，所述基板包括显示区和位于所述显示区周边的用于密封的周边区，所述制备方法包括：提供衬底基板；在所述显示区和所述周边区中且在所述衬底基板的一侧形成绝缘层，在所述周边区中且在所述绝缘层在背离所述衬底基板的一侧形成至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板，其中所述基板包括多个像素单元，所述多个像素单元位于所述显示区对应的所述绝缘层上。
例如，所述绝缘层形成为至少在所述周边区的表面具有疏液性质。
例如，基板的制备方法还包括：形成像素界定层，所述像素界定层包括分别用于所述多个像素单元的多个像素开口；形成发光层，所述发光层至少覆盖所述多个像素开口；其中，采用喷墨打印、旋涂或者喷涂的方式形成所述发光层，并且所述发光层的至少一部分形成于所述凹槽中。
例如，形成所述绝缘层包括：形成第一子绝缘层，所述第一子绝缘层具有第一凹槽部分，在所述第一子绝缘层上形成第二子绝缘层，所述第二子绝缘层具有与所述第一凹槽部分连通的开口，其中，所述第一凹槽部分和所述开口构成所述凹槽。
例如，所述第二子绝缘层采用具有疏液性质的材料形成，或者对所述第二子绝缘层的位于所述周边区的表面进行表面处理，以使所述第二子绝缘层的位于所述周边区的表面具有疏液性质。
例如，采用Ar、N2、CF4或O2的等离子体进行所述表面处理。
下面，以形成图7A和图7C示出的基板为例，对本实施例提供的制备方法进行介绍。
例如，如图8A所示，首先提供衬底基板201，然后在衬底基板201的不同区域形成显示区20和周边区21。例如，衬底基板201采用玻璃基板、石英基板、塑料基板等，本公开的实施例对此不做具体限定。
例如，在衬底基板201上形成用于显示区20中多个像素单元的驱动电路202。例如，驱动电路202包括用于像素单元的像素驱动电路，该像素驱动电路包括薄膜晶体管、电容等结构，驱动电路还可以包括栅线、数据线等信号线，可以采用半导体制备工艺形成，本公开的实施例对此不做限定。
例如，在驱动电路202上形成第一子绝缘层2031，该步骤包括：在驱动电路202上形成一层第一子绝缘材料层，然后对第一子绝缘材料层进行构图以形成第一凹槽部分2031A。
例如，第一子绝缘层2031采用负性光刻胶材料形成，例如采用酚醛树脂等。此时，对第一子绝缘材料层进行构图包括通过掩膜版对第一子绝缘材料层进行曝光，然后进行显影，以形成第一凹槽部分2031A。第一凹槽部分2031A具有上窄下宽的结构，因此具有更大的容量。
如图8B所示，第一子绝缘层2031形成后，可以在第一子绝缘层2031上形成第二子绝缘层2032，该步骤包括：在第一子绝缘层2031上形成一层第二子绝缘材料层，然后对第二子绝缘材料层进行构图以形成与第一凹槽部分2031A连通的开口2032A。
例如，第二子绝缘层2032采用正性光刻胶材料或无机材料形成，例如采用聚亚酰胺、聚丙烯酸酯等正性光刻胶材料，或者SiOx、SiNx、Al2O3等无机材料。例如，当第二子绝缘层2032采用正性光刻胶材料形成时，对第二子绝缘材料层进行构图包括通过掩膜版对第二子绝缘材料层进行曝光与显影，以形成开口2032A。当第二子绝缘层2032采用无机材料形成时，对第二子绝缘材料层进行构图包括在第二子绝缘材料层上形成一层光刻胶，然后通过掩膜版对光刻胶进行曝光与显影形成光刻胶图案，然后通过该光刻胶图案对第二子绝缘材料层进行刻蚀以形成开口2032A，该刻蚀例如采用干刻蚀或湿刻蚀，本公开的实施例对此不做限定。第一凹槽部分2031A和开口2032A构成绝缘层203中的凹槽203A。
例如，绝缘层203形成为至少在周边区21的表面具有疏液性质。此时，绝缘层203中位于上方的第二子绝缘层2032采用具有疏液性质的材料形成(例如上面例举的材料)，或者对第二子绝缘层2032的位于周边区21的表面进行表面处理，以使第二子绝缘层2032的位于周边区21的表面具有疏液性质。
例如，可以采用Ar、N 2、CF 4或O 2的等离子体对第二子绝缘层2032的位于周边区21的表面进行表面处理，以使第二子绝缘层2032的位于周边区21的表面具有疏液性质。例如，当第二子绝缘层2032采用具有疏液性质的材料形成时，由于不同的具有疏液性质的材料对形成于其上的不同液体的疏液程度不同，因此可以根据需求选择相应的材料；又或者，也可以对采用具 有疏液性质的材料形成的第二子绝缘层2032的表面进行疏液处理，以进一步提高第二子绝缘层2032表面的疏液性能。
如图8C所示，在绝缘层203的位于显示区20的部分上形成发光元件层204。例如，首先形成第一电极2041，该第一电极2041包括对应于多个像素单元的多个子电极；然后形成像素界定层2042，像素界定层2042包括分别用于多个像素单元的多个像素开口2042A，该多个像素开口2042A分别暴露第一电极2041的多个子电极，发光层2043形成为至少覆盖多个像素开口2042A，然后在发光层2043上形成第二电极2043以及钝化层2044。
例如，第一电极2041以及像素界定层2042可以采用构图工艺形成，第一电极2041的材料例如包括ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金，像素界定层2042的材料例如包括聚酰亚胺等有机材料或者氧化硅、氮化硅等无机材料。
例如，发光层2043可以采用喷墨打印、旋涂或者喷涂等印刷的方式形成，由于印刷的墨水的流动性，印刷的发光层2043的材料还延伸至凹槽203A中。发光层2043的材料根据要形成的发光元件的类型进行相应的选择。例如，要形成OLED时，使用有机发光材料，并且发光层可以为复合层，例如包括电子注入子层、电子传输子层、发光子层、空穴传输子层、空穴注入子层等；又例如，要形成QLED时，使用量子点发光材料。本公开的实施例对发光层的材料不作限制。例如，第二电极2044和钝化层2044可以分别采用蒸镀、溅射或者沉积等方式通过掩膜板形成。例如，第二电极2044的材料包括Mg、Ca、Li或Al等金属或其合金，或者IZO、ZTO等具有导电性的无机材料，或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性的有机材料，钝化层2045的材料包括聚酰亚胺等有机材料或者氧化硅、氮化硅等无机材料。
进一步地，本公开的实施例还提供一种显示面板的制备方法，包括：制造所述基板，所述基板由以上任意所述的制备方法制备；提供对置基板，且将所述对置基板通过封框胶结合在显示面板上，其中，所述封框胶覆盖所述凹槽。例如，参照附图对该制备方法进行描述，如图8D所示，发光元件层204形成后，该显示面板的制备方法在基板的制备方法之后还包括：提供对置基板206，且将对置基板206通过封框胶205结合在基板上，例如，封框胶206以预定图案涂敷在周边区域中，覆盖凹槽203A，从而至少部分填入到 覆盖凹槽203A；例如根据封框胶的类型，可以对封框胶进行紫外光照固化或热固化。例如，对置基板206的材料包括玻璃板、塑料板或塑料膜，例如塑料材料可以采用PET(聚对苯二甲酸乙二醇酯)或者PI(聚酰亚胺)等透明材料，封框胶205的材料包括树脂等具有粘结性的材料。
本公开的一些实施例中，绝缘层203位于周边区21的凹槽203A可以收集在形成发光元件层204时形成于周边区21的发光层2043的材料，因此绝缘层203的位于周边区21的部分上例如不会残留不希望的材料，此时，封框胶205可以直接将对置基板206与绝缘层103结合，从而具有更好的封装效果。
例如，在一些实施例中，第二电极2044和/或钝化层2044也可以采用蒸镀、溅射或者沉积等方式形成为一整面，此时凹槽203A中还具有第二电极2044和/或钝化层2044的形成材料。
本公开的一些实施例中，由于绝缘层203的位于周边区21的部分具有凹槽203A，该凹槽203A可以收集形成在绝缘层203的位于周边区21的部分上的不希望的材料。如图9所示，该制备方法可以用于使用一个母板，通过该母板同时制备多个显示面板，这些显示面板可以具有相同的形状或者不同的形状，之后可以通过切割工艺将这些显示面板彼此分开。例如，图9中，在同一母板上制备三个显示面板，包括位于上侧的椭圆形的显示面板和位于下侧的两个矩形显示面板。在各个显示面板中，封框胶206围绕显示区20，覆盖周边区中的凹槽。例如在一些实施例中，显示面板也可以具有不规则的形状，此时，即使整面形成发光层2043等功能层，由于凹槽203A的收集作用，发光层2043等功能层的材料例如也不会残留在绝缘层203的位于周边区21的部分上，从而不会影响封框胶205的封装效果。因此，本公开的实施例提供的制备方法制备得到的显示面板具有更好的封装效果，并且利用该制备方法可以同时形成多个显示面板，以提高生产效率。
本公开至少一实施例还提供了一种显示装置，如图10所示，显示装置300包括本公开实施例提供的任一显示面板，图中示出为显示面板200。该显示装置300可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不做限定。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
本申请要求于2018年12月07日提交的中国专利申请第201811496810.5的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。

Claims (23)

  1. 一种基板，包括显示区和位于所述显示区周边的用于密封的周边区，所述基板包括：
    衬底基板；
    绝缘层，设置在所述衬底基板的一侧，且位于所述显示区和用于密封的周边区；
    多个像素单元，位于所述显示区对应的所述绝缘层上，
    其中在所述周边区中，所述绝缘层在背离所述衬底基板的一侧设置有至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板。
  2. 根据权利要求1所述的基板，其中所述用于密封的周边区是封框胶设置区域，
    所述像素单元包括：
    发光元件层，设置在所述绝缘层的背离衬底基板的一侧，且包括发光层。
  3. 根据权利要求1所述的基板，其中所述凹槽的延伸方向平行于所述衬底基板所在的平面，在垂直于所述衬底基板的平面上，所述凹槽的纵截面呈正梯形或者倒梯形。
  4. 根据权利要求2所述的基板，包括：
    像素界定层，位于所述显示区对应的所述绝缘层上，且包括用于限定所述多个像素单元的多个像素开口，
    所述发光层至少覆盖所述多个像素开口；
    其中，所述凹槽的延伸方向与所述像素开口的延伸方向相同。
  5. 根据权利要求4所述的基板，其中所述凹槽的远离所述衬底基板的一端的形状和尺寸与所述多个像素开口的远离所述衬底基板的一端的形状和尺寸相同；
    或者所述凹槽的远离所述衬底基板的一端的形状与所述多个像素开口的远离所述衬底基板的一端的形状相同，所述凹槽的远离所述衬底基板的一端的尺寸大于所述多个像素开口的远离所述衬底基板的一端的尺寸。
  6. 根据权利要求1-4中任一项所述的基板，其中，所述绝缘层在所述 周边区中包括多个所述凹槽，
    所述多个凹槽的延伸方向相同，所述多个凹槽在所述显示区的周边排布成多行和多列，所述凹槽的行方向与所述多个像素开口的行方向相同，所述凹槽的列方向与所述像素开口的列方向相同,
    其中所述凹槽的远离所述衬底基板的一端的形状与所述多个像素开口的远离所述衬底基板的一端的形状相同，
    所述多个凹槽的远离所述衬底基板的一端的尺寸等于所述多个像素开口的远离所述衬底基板的一端的尺寸或者所述多个凹槽中至少一部分的远离所述衬底基板的一端的尺寸大于所述多个像素开口的远离所述衬底基板的一端的尺寸。
  7. 根据权利要求6所述的基板，其中所述多个凹槽的远离所述衬底基板的一端的尺寸等于所述多个像素开口的远离所述衬底基板的一端的尺寸，所述多个凹槽的形状和大小相同，所述凹槽的行方向的节距与所述像素开口的行方向的节距相同和/或所述凹槽的列方向的节距与所述像素开口的列方向的节距相同。
  8. 根据权利要求6所述的基板，其中所述多个凹槽按照长度不同分成两组，所述多个凹槽的宽度等于所述像素开口的宽度，两组之一的凹槽的长度等于所述多个像素开口的沿列方向节距之和，且沿像素开口的行方向排布在所述显示区的两侧，所述两组中另一组的凹槽的长度等于或大于所述多个像素开口的长度，所述另外一组排布在所述显示区的在列方向的两侧，所述多个凹槽沿行方向的节距与所述多个像素开口的沿行方向的节距相同。
  9. 根据权利要求1-8中任一项所述的基板，其中，所述绝缘层的位于所述周边区的表面具有疏液性质。
  10. 根据权利要求1-9中任一项所述的基板，其中所述发光层的至少一部分位于所述凹槽中。
  11. 根据权利要求1-6任一项所述的基板，其中，所述绝缘层包括：
    第一子绝缘层，具有第一凹槽部分，
    第二子绝缘层，层叠在所述第一子绝缘层上，具有与所述第一凹槽部分连通的开口，
    所述第一凹槽部分和所述开口构成所述凹槽。
  12. 根据权利要求11所述的基板，其中，所述第一凹槽部分的纵截面 呈正梯形，所述开口的纵截面呈倒梯形或者矩形。
  13. 根据权利要求11或12所述的基板，其中，所述第一子绝缘层的材料包括负性光刻胶材料，所述第二子绝缘层的材料包括正性光刻胶材料或无机材料。
  14. 根据权利要求1-13所述的基板，还包括：
    驱动电路，在所述显示区中位于所述衬底基板上，用于驱动所述多个像素单元，
    其中，所述绝缘层覆盖所述驱动电路。
  15. 一种显示面板，包括：
    根据权利要求1-14中任一项所述的基板；
    对置基板，设置为与所述基板相对；以及
    封框胶，设置在所述基板与所述对置基板之间，
    其中，所述封框胶覆盖所述凹槽，将所述对置基板与所述基板结合。
  16. 一种基板的制备方法，所述基板包括显示区和位于所述显示区周边的用于密封的周边区，所述制备方法包括：
    提供衬底基板；
    在所述显示区和所述周边区中且在所述衬底基板的一侧形成绝缘层，
    在所述周边区中且在所述绝缘层在背离所述衬底基板的一侧形成至少一个凹槽，所述凹槽远离所述衬底基板的一侧是开口的，所述凹槽的深度方向垂直于所述衬底基板，
    其中所述基板包括多个像素单元，所述多个像素单元位于所述显示区对应的所述绝缘层上。
  17. 根据权利要求16所述的制备方法，其中，所述绝缘层形成为至少在所述周边区的表面具有疏液性质。
  18. 根据权利要求16所述的制备方法，还包括：
    形成像素界定层，所述像素界定层包括分别用于所述多个像素单元的多个像素开口；
    形成发光层，所述发光层至少覆盖所述多个像素开口；
    其中，采用喷墨打印、旋涂或者喷涂的方式形成所述发光层，并且所述发光层的至少一部分形成于所述凹槽中。
  19. 根据权利要求16-18中任一所述的制备方法，其中，形成所述绝缘 层包括：
    形成第一子绝缘层，所述第一子绝缘层具有第一凹槽部分，
    在所述第一子绝缘层上形成第二子绝缘层，所述第二子绝缘层具有与所述第一凹槽部分连通的开口，
    其中，所述第一凹槽部分和所述开口构成所述凹槽。
  20. 根据权利要求19所述的制备方法，其中，所述第二子绝缘层采用具有疏液性质的材料形成，或者对所述第二子绝缘层的位于所述周边区的表面进行表面处理，以使所述第二子绝缘层的位于所述周边区的表面具有疏液性质。
  21. 根据权利要求20所述的制备方法，其中，采用Ar、N 2、CF 4或O 2的等离子体进行所述表面处理。
  22. 一种如权利要求15所述的显示面板的制备方法，包括：
    制造所述基板，所述基板由根据16-21中任一项所述的制备方法制备；
    提供对置基板，且将所述对置基板通过封框胶结合在所述基板上，其中，所述封框胶覆盖所述凹槽。
  23. 一种显示装置，包括权利要求15所述的显示面板。
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