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WO2019174372A1 - 像素补偿电路、驱动方法、电致发光显示面板及显示装置 - Google Patents

像素补偿电路、驱动方法、电致发光显示面板及显示装置 Download PDF

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Publication number
WO2019174372A1
WO2019174372A1 PCT/CN2019/070056 CN2019070056W WO2019174372A1 WO 2019174372 A1 WO2019174372 A1 WO 2019174372A1 CN 2019070056 W CN2019070056 W CN 2019070056W WO 2019174372 A1 WO2019174372 A1 WO 2019174372A1
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WIPO (PCT)
Prior art keywords
circuit
switching transistor
driving
signal
control
Prior art date
Application number
PCT/CN2019/070056
Other languages
English (en)
French (fr)
Inventor
张陶然
莫再隆
周炟
代科
张祎杨
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/480,340 priority Critical patent/US10950176B2/en
Priority to EP19740304.1A priority patent/EP3767615A4/en
Publication of WO2019174372A1 publication Critical patent/WO2019174372A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel compensation circuit, a driving method, an electroluminescence display panel, and a display device.
  • OLED displays have the advantages of low power consumption, low production cost, self-illumination, wide viewing angle and fast response. They are one of the hotspots in the field of flat panel display research. Among them, the design of the pixel circuit for controlling the OLED to emit light is the core technical content of the OLED display. OLEDs are current-driven and require a constant current to control their illumination to ensure display uniformity of the display panel.
  • a data writing circuit for providing a data signal to a control end of the driving circuit during a reset phase and a threshold compensation phase
  • a voltage input circuit for providing a first power signal to an input end of the driving circuit during the reset phase and the light emitting phase
  • a storage circuit for storing a voltage of an input end of the driving circuit and a connection node
  • a discharge control circuit for resetting a voltage of the connection node and a first electrode of the light emitting device during the resetting phase, and controlling the driving circuit to write a threshold voltage of the driving circuit during the threshold compensation phase An input end of the drive circuit;
  • a conduction control circuit configured to turn on the connection node and the control end of the driving circuit during the lighting phase
  • the driving circuit is configured to generate a driving current flowing to the first electrode of the light emitting device during the light emitting phase to drive the light emitting device to emit light.
  • control end of the data writing circuit is configured to input a first scan signal, the input end is configured to input the data signal, and the output end is coupled to the control end of the driving circuit.
  • the data writing circuit is configured to provide the data signal to a control end of the driving circuit under the control of the first scanning signal;
  • the control terminal of the voltage input circuit is configured to input a second scan signal, the input end is configured to input the first power signal, and the output end is coupled to an input end of the driving circuit; Providing the first power signal to an input end of the driving circuit under the control of the second scan signal;
  • the first end of the storage circuit is coupled to the input end of the driving circuit, and the second end is coupled to the connection node;
  • the control end of the discharge control circuit is configured to receive the first scan signal, and the input end is configured to receive a reset signal, and the output end is respectively connected to the connection node, the first electrode of the light emitting device, and the output of the driving circuit End-disconnecting; the discharge control circuit is configured to provide the reset signal to the connection node and the first electrode of the light-emitting device under control of the first scan signal, and control the drive circuit to a threshold voltage of the driving circuit is written to an input end of the driving circuit;
  • the control end of the conduction control circuit is configured to receive a third scan signal, the input end is coupled to the connection node, and the output end is coupled to the control end of the drive circuit; the conduction control circuit is used in the Under the control of the third scan signal, the connection node and the control end of the driving circuit are turned on.
  • the discharge control circuit includes: a first switching transistor and a second switching transistor;
  • a gate of the first switching transistor is configured to receive a first scan signal, a first pole of the first switching transistor is configured to receive a reset signal, and a second end of the first switching transistor is coupled to the connection node ;
  • a gate of the second switching transistor is configured to receive the first scan signal, a first pole of the second switching transistor is configured to receive the reset signal, and a second pole of the second switching transistor is respectively An output end of the driving circuit and a first electrode of the light emitting device are coupled.
  • the rising edge of the first scan signal changes from a low level signal to a high level signal in a linear rising manner.
  • the falling edge of the first scan signal changes from a high level signal to a low level signal in a linearly decreasing manner.
  • the driving circuit includes: a driving transistor
  • a first pole of the driving transistor is respectively connected to the voltage input circuit and the storage circuit, and a gate of the driving transistor is respectively connected to the conduction control circuit and the data writing circuit, the driving transistor
  • the second pole is connected to the first pole of the light emitting device.
  • the storage circuit includes: a storage capacitor
  • the first end of the storage capacitor is coupled to the input end of the driving circuit, and the second end of the storage capacitor is coupled to the connecting node.
  • the conduction control circuit includes: a third switching transistor
  • a gate of the third switching transistor is configured to receive a third scan signal, a first pole of the third switching transistor is coupled to the connection node, and a second pole of the third switching transistor is coupled to the driving circuit
  • the control terminals are coupled.
  • the third scan signal and the first scan signal are the same signal.
  • the voltage input circuit includes: a fourth switching transistor
  • a gate of the fourth switching transistor is configured to receive a second scan signal
  • a first pole of the fourth switching transistor is configured to receive the first power signal
  • a second pole of the fourth switching transistor is The input ends of the driving circuit are coupled.
  • the data writing circuit includes: a fifth switching transistor
  • a gate of the fifth switching transistor is configured to receive a first scan signal
  • a first pole of the fifth switching transistor is configured to receive the data signal
  • a second pole of the fifth switching transistor and the driving circuit The control terminals are coupled.
  • the array substrate further includes: the light emitting device comprises: an electroluminescent diode;
  • An anode of the electroluminescent diode serves as a first electrode of the light emitting device, and a cathode of the electroluminescent diode is configured to receive a second power signal.
  • an embodiment of the present disclosure further provides an electroluminescent display panel, which includes the pixel compensation circuit provided by the embodiment of the present disclosure.
  • embodiments of the present disclosure also provide a display device including an electroluminescent display panel provided by an embodiment of the present disclosure.
  • the driving method of the pixel compensation circuit provided by the embodiment of the present disclosure, wherein the method includes:
  • the data write circuit providing a data signal to a control terminal of the drive circuit;
  • the voltage input circuit providing a first power signal to an input of the drive circuit;
  • the discharge control circuit Resetting the voltage of the connection node and the first electrode of the light emitting device;
  • the data write circuit providing a data signal to a control terminal of the drive circuit;
  • the discharge control circuit controlling the drive circuit to write a threshold voltage of the drive circuit to an input end of the drive circuit
  • the storage circuit stores a voltage of an input end of the driving circuit and a connection node;
  • the voltage input circuit supplies a first power signal to an input end of the driving circuit;
  • the memory circuit stores a voltage of an input end of the driving circuit and a connection node; and the conduction control circuit is turned on a connection node and a control terminal of the driving circuit; the driving circuit generates a driving current flowing to the first electrode of the light emitting device to drive the light emitting device to emit light.
  • FIG. 1 is a schematic structural diagram of a pixel compensation circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel compensation circuit according to an embodiment of the present disclosure
  • FIG. 3 is a second schematic structural diagram of a pixel compensation circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a third schematic structural diagram of a pixel compensation circuit according to an embodiment of the present disclosure.
  • FIG. 5a is one of circuit timing diagrams provided by an embodiment of the present disclosure.
  • FIG. 5b is a second circuit diagram of the circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a waveform diagram of a first scan signal
  • Figure 7a is a simulation diagram of the first scan signal
  • Figure 7b is a simulation diagram of the current outputted from the output of the driving circuit
  • FIG. 8 is a flowchart of a driving method provided by an embodiment of the present disclosure.
  • OLED displays can be generally used a pixel compensation circuit compensating the threshold voltage V th and IR Drop to drive the OLED to emit light.
  • the pixel compensation circuit of the related OLED display has a large number of switching transistors and a complicated circuit operation timing, which results in a large process difficulty, an increase in production cost, and a large area occupied by the pixel compensation circuit.
  • the charging time of the pixel compensation circuit is currently long, which is disadvantageous for achieving high resolution of the OLED display.
  • the embodiment of the present disclosure provides a pixel compensation circuit, which can realize the compensation of the threshold voltage of the driving circuit and the IR Drop of the power signal by a simple structure and a simple timing, thereby simplifying the preparation process, reducing the production cost, and reducing The small footprint is conducive to the design of high resolution OLED display panels.
  • a pixel compensation circuit includes: a data writing circuit 1, a voltage input circuit 2, a discharge control circuit 3, a storage circuit 4, a conduction control circuit 5, a driving circuit 6, Light emitting device L; wherein
  • the data writing circuit 1 is for supplying the data signal DA to the control terminal of the driving circuit 6 in the reset phase and the threshold compensation phase;
  • the voltage input circuit 2 is configured to supply the first power signal VDD to the input end of the driving circuit 6 in the reset phase and the light emitting phase;
  • the storage circuit 4 is configured to store the input end of the drive circuit 6 and the voltage of the connection node N0;
  • the discharge control circuit 3 is for resetting the voltage of the connection node N0 and the first electrode of the light-emitting device L in the reset phase, and controlling the drive circuit 6 to write the threshold voltage of the drive circuit 6 to the input terminal of the drive circuit 6 in the threshold compensation phase. ;
  • the conduction control circuit 5 is configured to conduct the connection node N0 and the control end of the driving circuit 6 in the light emitting phase;
  • the driving circuit 6 is for generating a driving current flowing to the first electrode of the light emitting device L in the light emitting phase to drive the light emitting device L to emit light.
  • the pixel compensation circuit provided by the embodiment of the present disclosure provides a data signal to the control end of the driving circuit through the data writing circuit in the reset phase, and the discharge control circuit resets the voltage of the connection node and the first electrode of the light emitting device, and the voltage
  • the input circuit supplies the first power signal to the input end of the driving circuit, and respectively charges the input node of the connection node and the driving circuit to increase the charging rate and reduce the charging time.
  • the data signal is supplied to the control terminal of the driving circuit through the data writing circuit, and the discharging control circuit controls the driving circuit to write the threshold voltage of the driving circuit to the input end of the driving circuit, thereby enabling writing of the data signal and Compensation of the threshold voltage Vth of the drive circuit.
  • the first power signal is supplied to the input end of the driving circuit through the voltage input circuit, and the conduction control circuit turns on the connection node and the control end of the driving circuit to implement compensation for the IR Drop of the first power signal. And controlling the driving circuit to generate a driving current to drive the light emitting device to emit light. Therefore, the mutual matching of the above circuits can be used to compensate the threshold voltage of the driving circuit and the IR Drop of the first power signal by a simple structure and a simple timing, thereby simplifying the manufacturing process, reducing the production cost, and reducing the occupation.
  • the area is conducive to the design of high resolution OLED display panels.
  • the control end of the data write circuit 1 is used to input the first scan signal SC1 , and the input end is used to input the data signal DA and output.
  • the terminal is coupled to the control terminal of the driving circuit 6; the data writing circuit 1 is for supplying the data signal DA to the control terminal of the driving circuit 6 under the control of the first scanning signal SC1.
  • the control terminal of the voltage input circuit 2 is for inputting the second scan signal SC2, the input terminal is for inputting the first power source signal VDD, the output terminal is coupled to the input end of the drive circuit 6, and the voltage input circuit 2 is for inputting the second scan signal. Under the control of SC2, the first power supply signal VDD is supplied to the input terminal of the drive circuit 6.
  • the first end of the storage circuit 4 is coupled to the input end of the drive circuit 6, and the second end is coupled to the connection node N0.
  • the control end of the discharge control circuit 3 is configured to receive the first scan signal SC1, the input end is configured to receive the reset signal VINIT, and the output end is coupled to the connection node N0, the first electrode of the light emitting device L, and the output end of the driving circuit 6, respectively;
  • the discharge control circuit 3 is configured to supply the reset signal VINIT to the connection node N0 and the first electrode of the light emitting device L under the control of the first scan signal SC1, and control the drive circuit 6 to write the threshold voltage of the drive circuit 6 to the drive circuit.
  • the control terminal of the conduction control circuit 5 is configured to receive the third scan signal SC3, the input end is coupled to the connection node N0, the output end is coupled to the control end of the drive circuit 6, and the conduction control circuit 5 is configured to be used in the third scan signal. Under the control of SC3, the connection node N0 and the control terminal of the drive circuit 6 are turned on.
  • the driving circuit 6 includes a driving transistor M0, and the first electrode S of the driving transistor M0 and the voltage input circuit 2 and the storage respectively The circuit 4 is connected, and the gate G of the driving transistor M0 is connected to the conduction control circuit 5 and the data writing circuit 1, respectively, and the second pole D of the driving transistor M0 and the light emitting device L One pole is connected.
  • the driving transistor M0 may be a P-type transistor; wherein the first pole S of the driving transistor M0 serves as The source, the second pole D of the driving transistor M0 serves as its drain. And the current when the driving transistor M0 is in a saturated state flows from the source of the driving transistor M0 to the drain thereof.
  • the light emitting device generally emits light under the action of a current when the driving transistor is in a saturated state.
  • a general light emitting device has a light-emitting threshold voltage, and emits light when a voltage across the light-emitting device is greater than or equal to a light-emitting threshold voltage.
  • the light emitting device may include: an electroluminescent diode; wherein the anode of the electroluminescent diode is used as the first electrode of the light emitting device, and the cathode of the electroluminescent diode For receiving the second power signal.
  • the electroluminescent diode may include: an OLED, or a Quantum Dot Light Emitting Diodes (QLED).
  • the voltage V dd of the first power signal is generally a positive value
  • the voltage V init of the reset signal is generally a negative value
  • the voltage V ss of the second power signal is generally a ground voltage or a negative value. In practical applications, the above voltages need to be determined according to the actual application environment, which is not limited herein.
  • the discharge control circuit 3 may include: a first switching transistor M1 and a second switching transistor M2.
  • the gate of the first switching transistor M1 is configured to receive the first scan signal SC1
  • the first pole of the first switching transistor M1 is configured to receive the reset signal VINIT
  • the second end of the first switching transistor M1 is coupled to the connection node N0.
  • the gate of the second switching transistor M2 is for receiving the first scan signal SC1
  • the first pole of the second switching transistor M1 is for receiving the reset signal VINIT
  • the second pole of the second switching transistor M2 is respectively connected with the output of the driving circuit 6. And coupling the first electrode of the light emitting device L.
  • the reset signal when the first switching transistor is in an on state under the control of the first scan signal, the reset signal may be provided to the connection node.
  • the reset signal when the second switching transistor is in an on state under the control of the first scan signal, the reset signal may be supplied to the output terminal of the driving circuit and the first electrode of the light emitting device.
  • the first switching transistor M1 and the second switching transistor M2 may be N-type transistors. As shown in FIG. 3, the first switching transistor M1 and the second switching transistor M2 may also be P-type transistors, which are not limited herein.
  • the storage circuit 4 may include: a storage capacitor Cst; wherein the first end of the storage capacitor Cst and the driving The input end of the circuit 6 is coupled, and the second end of the storage capacitor Cst is coupled to the connection node N0.
  • the storage capacitor can be charged or discharged according to a signal input to the input end of the driving circuit and a signal input to the node to store the voltage across the terminal.
  • the connection node When the connection node is in a floating state, the voltage at the input of the input drive circuit can be coupled to the connection node by the coupling of the storage capacitor.
  • the conduction control circuit 5 may include: a third switching transistor M3; wherein the third switching transistor M3 The gate of the third switching transistor M3 is coupled to the connection node N0, and the second electrode of the third switching transistor M3 is coupled to the control terminal of the driving circuit 6.
  • connection node and the control end of the driving circuit when the third switching transistor is in an on state under the control of the third scan signal, the connection node and the control end of the driving circuit may be turned on to The signal of the connection node is input to the control terminal of the drive circuit.
  • the third switching transistor M3 may be a P-type transistor.
  • the third switching transistor may also be an N-type transistor, which is not limited herein.
  • the third scan signal and the first scan signal can be set to the same signal.
  • the gates of the first switching transistor M1, the second switching transistor M2, and the third switching transistor M3 are both used to receive the first scan signal SC1.
  • the types of the first switching transistor M1 and the third switching transistor M3 are different.
  • the first switching transistor M1 is an N-type transistor
  • the third switching transistor M3 is a P-type transistor.
  • the voltage input circuit 2 may include: a fourth switching transistor M4; wherein, the fourth switching transistor M4 The gate is for receiving the second scan signal SC2, the first pole of the fourth switching transistor M4 is for receiving the first power signal VDD, and the second pole of the fourth switching transistor M4 is coupled to the input end of the driving circuit 6.
  • the first power signal when the fourth switching transistor is in an on state under the control of the second scan signal, the first power signal may be provided to the input end of the driving circuit.
  • the fourth switching transistor M4 may be a P-type transistor.
  • the fourth switching transistor may also be an N-type transistor, which is not limited herein.
  • the data writing circuit 1 may include: a fifth switching transistor M5; wherein, the fifth switching transistor M5 The gate of the fifth switching transistor M5 is for receiving the data signal DA, and the second electrode of the fifth switching transistor M5 is coupled to the control terminal of the driving circuit 6.
  • the data signal when the fifth switching transistor is in an on state under the control of the first scan signal, the data signal may be provided to the control end of the driving circuit.
  • the fifth switching transistor M5 may be an N-type transistor. As shown in FIG. 3, the fifth switching transistor M5 may also be a P-type transistor, which is not limited herein.
  • each circuit in the pixel compensation circuit provided by the embodiment of the present disclosure.
  • the specific structure of each circuit is not limited to the foregoing structure provided by the embodiment of the present disclosure, and may also be a person skilled in the art. Other structures that are known are not limited herein.
  • the driving transistor M0 is a P-type transistor
  • all the transistors are used. It can be a P-type transistor.
  • the P-type transistor is turned off under the action of the high level, and is turned on under the action of the low level; the N-type transistor is turned on under the action of the high level. Cut off at low level.
  • the transistor in the pixel compensation circuit may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor). Not limited.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the first pole of the switching transistor can be used as its source, and the second pole can be used as its drain; or vice versa, the first pole can be used as its drain.
  • the second pole serves as its source and no specific distinction is made here.
  • the structure of the pixel compensation circuit shown in FIG. 2 is taken as an example, and the corresponding circuit timing diagram is shown in FIG. 5a.
  • the reset phase T1 the threshold compensation phase T2, and the illumination phase T3 are mainly selected.
  • the turned-on first switching transistor M1 supplies a reset signal VINIT to the connection node N0 to reset the connection node N0.
  • the turned-on second switching transistor M2 supplies the reset signal VINIT to the second pole D of the driving transistor M0 and the anode of the light emitting device L to reset the anode of the light emitting device L.
  • the turned-on fifth switching transistor M5 supplies the data signal DA to the gate G of the driving transistor M0.
  • the gate of the driving transistor M0 voltage V G to the data signal DA voltage V da, the driving transistor M0 voltage V S S pole of the first signal to a first power source voltage VDD is V dd
  • the second driving transistor M0 The voltage V D of the diode D is the voltage V init of the reset signal VINIT.
  • the driving transistor M0 generates a current flowing from its first pole S to the second pole D, and the current is discharged through the second switching transistor M2, so that the light-emitting device L can be prevented from being advanced by the current generated by the driving transistor M0 in this stage.
  • the turned-on first switching transistor M1 supplies the reset signal VINIT to the connection node N0 such that the voltage V N0 of the connection node N0 is V init .
  • the turned-on second switching transistor M2 supplies a reset signal VINIT to the second pole D of the driving transistor M0.
  • the driving transistor M0 generates a current flowing from the first pole S to the second pole D, and the current passes through The second switching transistor M2 is released, so that the voltage of V S is decreased, that is, the storage capacitor Cst is discharged until the voltage V S of the first pole of the driving transistor M0 becomes V da -V th , and the driving transistor M0 is turned off, thereby realizing The compensation of the threshold voltage Vth of the driving transistor M0.
  • V GS is a gate-source voltage of the driving transistor M0
  • K is a structural parameter
  • ⁇ represents the mobility of the driving transistor M0
  • C o represents the gate oxide capacitance per unit area. Representing the aspect ratio of the drive transistor M0, these values are relatively stable in the same structure and can be counted as constants.
  • the driving current I L generated by the driving transistor M0 is only related to the voltage V init of the reset signal VINIT and the voltage V da of the data signal DA, and the threshold voltage V th of the driving transistor M0 and the first power signal VDD Regardless of the voltage V dd , the influence of the threshold voltage V th of the driving transistor M0 and the influence of the IR drop on the driving current I L can be solved, so that the driving current of the light-emitting device L is kept stable, thereby ensuring the normal operation of the light-emitting device L.
  • the capacitor Cst is saved.
  • the voltage connected to the node N0 causes an adverse effect.
  • the first switching transistor M1 is controlled to be completely turned off.
  • the threshold voltage V th of the driving transistor and the IR Drop of the first power signal can be realized by a simple structure and a simple timing. Compensation, which simplifies the preparation process, reduces production costs, and reduces footprint.
  • the voltage of the first power signal is generally a voltage of a fixed voltage value
  • charging the storage capacitor by using the first power signal during the reset phase can increase the charging rate of the storage capacitor and reduce the charging time.
  • the processing rate of the circuit can be increased, which is advantageous for application in the design of a high resolution display panel.
  • the structure of the pixel compensation circuit shown in FIG. 4 is taken as an example, and the corresponding circuit timing diagram is shown in FIG. 5b.
  • the reset phase T1 the threshold compensation phase T2, and the illumination phase T3 are mainly selected.
  • the working process in this stage is basically the same as the working process of the threshold compensation phase T2 in the first embodiment, and is not limited herein.
  • the voltage of the connection node N0 held by the capacitor Cst is adversely affected.
  • the threshold voltage V th of the driving transistor and the IR Drop of the first power signal can be realized by a simple structure and a simple timing. Compensation, which simplifies the preparation process, reduces production costs, and reduces footprint.
  • the voltage of the first power signal is generally a voltage of a fixed voltage value
  • charging the storage capacitor by using the first power signal during the reset phase can increase the charging rate of the storage capacitor and reduce the charging time.
  • the processing rate of the circuit can be increased, which is advantageous for application in the design of a high resolution display panel.
  • the first scan signal SC1 when the first scan signal is switched between high and low levels, for example, in FIG. 5a and FIG. 5b, the first scan signal SC1 is directly switched from a low level signal to a high level signal, or is switched by a high level signal.
  • the driving transistor M0 When the signal is low level, the driving transistor M0 has a sharp current with a large current value, which may affect the circuit.
  • the rising edge of the first scan signal SC1 may be linearly increased to gradually change the first scan signal SC1 from a low level signal to a high level.
  • Flat signal For example, as shown in FIG. 7a and FIG. 7b, FIG.
  • FIG. 7a is a simulation simulation diagram of the first scan signal SC1, wherein the abscissa represents time and the ordinate represents voltage value.
  • Fig. 7b is a simulation diagram of the current flowing out of the second pole D of the driving transistor M0, wherein the abscissa represents time and the ordinate represents current value.
  • FIG. 7a and FIG. 7b by gradually ramping the first scan signal SC1 from -7V to 7V, the current flowing out of the second pole D of the driving transistor M0 can be stabilized, thereby avoiding spikes. Current.
  • the falling edge of the first scan signal SC1 may be linearly decreased to gradually change the first scan signal SC1 from the high level signal to the low level signal.
  • the first scan signal SC1 may be linearly decreased to gradually change the first scan signal SC1 from the high level signal to the low level signal.
  • FIG. 7a and FIG. 7b by gradually ramping the first scan signal SC1 from 7V to -7V, the current flowing out of the second pole D of the driving transistor M0 can be stabilized, so that a spike current can be avoided.
  • an embodiment of the present disclosure further provides a driving method of a pixel compensation circuit provided by an embodiment of the present disclosure.
  • the principle of the driving method is similar to the foregoing pixel compensation circuit. Therefore, the implementation of the driving method can be referred to the implementation of the foregoing pixel compensation circuit, and the repetitive points are not described herein again.
  • the driving method of the pixel compensation circuit may include:
  • the data writing circuit supplies the data signal to the control end of the driving circuit; the voltage input circuit supplies the first power signal to the input end of the driving circuit; and the discharging control circuit pairs the connecting node and the first electrode of the light emitting device The voltage is reset.
  • the data writing circuit supplies the data signal to the control end of the driving circuit; the discharging control circuit controls the driving circuit to write the threshold voltage of the driving circuit to the input end of the driving circuit; the storage circuit stores the input end of the driving circuit and The voltage at which the node is connected.
  • the voltage input circuit provides the first power signal to the input end of the driving circuit;
  • the storage circuit stores the input end of the driving circuit and the voltage of the connecting node;
  • the conduction control circuit turns on the connecting node and the control end of the driving circuit;
  • the driving circuit generates a driving current flowing to the first electrode of the light emitting device to drive the light emitting device to emit light.
  • the above driving method provided by the embodiment of the present disclosure can realize the compensation of the threshold voltage of the driving circuit and the IR Drop of the first power signal by a simple structure and a simple timing, thereby simplifying the manufacturing process, reducing the production cost, and reducing the occupation.
  • the area is conducive to the design of high resolution OLED display panels.
  • an embodiment of the present disclosure further provides an electroluminescent display panel, including the above pixel compensation circuit provided by an embodiment of the present disclosure.
  • the principle of solving the problem of the electroluminescent display panel is similar to that of the foregoing pixel compensation circuit. Therefore, the implementation of the electroluminescent display panel can be referred to the implementation of the foregoing pixel compensation circuit, and the repeated description is not repeated herein.
  • the electroluminescent display panel provided by the embodiment of the present disclosure may include an organic light emitting display panel and a quantum dot light emitting display panel.
  • an embodiment of the present disclosure further provides a display device including the above-described electroluminescent display panel provided by an embodiment of the present disclosure.
  • a display device including the above-described electroluminescent display panel provided by an embodiment of the present disclosure.
  • the display device reference may be made to the embodiment of the pixel compensation circuit described above, and the repeated description is omitted.
  • the display device provided by the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.
  • the pixel compensation circuit, the driving method, the electroluminescence display panel and the display device provided by the embodiments of the present disclosure provide a data signal to the control end of the driving circuit through the data writing circuit in the reset phase, and the discharge control circuit pairs the connection node and the light emitting
  • the voltage of the first electrode of the device is reset, and the voltage input circuit supplies the first power signal to the input end of the driving circuit, respectively charging the input node of the connection node and the driving circuit to increase the charging rate and reduce the charging time.
  • the data signal is supplied to the control terminal of the driving circuit through the data writing circuit, and the discharging control circuit controls the driving circuit to write the threshold voltage of the driving circuit to the input end of the driving circuit, thereby enabling writing of the data signal and Compensation of the threshold voltage Vth of the drive circuit.
  • the first power signal is supplied to the input end of the driving circuit through the voltage input circuit, and the conduction control circuit turns on the connection node and the control end of the driving circuit to implement compensation for the IR Drop of the first power signal. And controlling the driving circuit to generate a driving current to drive the light emitting device to emit light.
  • the mutual matching of the above circuits can be used to compensate the threshold voltage of the driving circuit and the IR Drop of the first power signal by a simple structure and a simple timing, thereby simplifying the manufacturing process, reducing the production cost, and reducing the occupation.
  • the area is conducive to the design of high resolution OLED display panels.

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Abstract

本公开公开了像素补偿电路、驱动方法、电致发光显示面板及显示装置，通过数据写入电路、电压输入电路、放电控制电路、存储电路、导通控制电路以及驱动电路的相互配合，可以通过简单的结构与简单的时序实现对驱动电路的阈值电压与第一电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积，有利于高分辨率的OLED显示面板的设计。

Description

像素补偿电路、驱动方法、电致发光显示面板及显示装置
本公开要求在2018年03月16日提交中国专利局、公开号为201810219431.5、公开名称为“像素补偿电路、驱动方法、电致发光显示面板及显示装置”的中国专利公开的优先权，其全部内容以引入的方式并入本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及像素补偿电路、驱动方法、电致发光显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，是当今平板显示器研究领域的热点之一。其中，用于控制OLED进行发光的像素电路的设计是OLED显示器的核心技术内容。OLED属于电流驱动，需要稳定的电流来控制其发光，以保证显示面板的显示均匀性。
发明内容
本公开实施例提供的像素补偿电路，其中，包括：
数据写入电路，用于在复位阶段与阈值补偿阶段，将数据信号提供给驱动电路的控制端；
电压输入电路，用于在所述复位阶段与发光阶段将第一电源信号提供给所述驱动电路的输入端；
存储电路，用于存储所述驱动电路的输入端和连接节点的电压；
放电控制电路，用于在所述复位阶段对所述连接节点与发光器件的第一电极的电压进行复位，以及在所述阈值补偿阶段控制所述驱动电路将所述驱动电路的阈值电压写入所述驱动电路的输入端；
导通控制电路，用于在所述发光阶段导通所述连接节点与所述驱动电路的控制端；
所述驱动电路，用于在所述发光阶段产生流向所述发光器件的第一电极的驱动电流，以驱动所述发光器件发光。
可选地，在本公开实施例中，所述数据写入电路的控制端用于输入第一扫描信号，输入端用于输入所述数据信号，输出端与所述驱动电路的控制端耦接；所述数据写入电路用于在所述第一扫描信号的控制下，将所述数据信号提供给所述驱动电路的控制端；
所述电压输入电路的控制端用于输入第二扫描信号，输入端用于输入所述第一电源信号，输出端与所述驱动电路的输入端耦接；所述电压输入电路用于在所述第二扫描信号的控制下，将所述第一电源信号提供给所述驱动电路的输入端；
所述存储电路的第一端与所述驱动电路的输入端耦接，第二端与所述连接节点耦接；
所述放电控制电路的控制端用于接收所述第一扫描信号，输入端用于接收复位信号，输出端分别与所述连接节点、所述发光器件的第一电极以及所述驱动电路的输出端耦接；所述放电控制电路用于在所述第一扫描信号的控制下，将所述复位信号提供给所述连接节点与所述发光器件的第一电极，以及控制所述驱动电路将所述驱动电路的阈值电压写入所述驱动电路的输入端；
所述导通控制电路的控制端用于接收第三扫描信号，输入端与所述连接节点耦接，输出端与所述驱动电路的控制端耦接；所述导通控制电路用于在所述第三扫描信号的控制下，导通所述连接节点与所述驱动电路的控制端。
可选地，在本公开实施例中，所述放电控制电路包括：第一开关晶体管与第二开关晶体管；
所述第一开关晶体管的栅极用于接收第一扫描信号，所述第一开关晶体管的第一极用于接收复位信号，所述第一开关晶体管的第二端与所述连接节点耦接；
所述第二开关晶体管的栅极用于接收所述第一扫描信号，所述第二开关晶体管的第一极用于接收所述复位信号，所述第二开关晶体管的第二极分别与所述驱动电路的输出端以及所述发光器件的第一电极耦接。
可选地，在本公开实施例中，所述第一扫描信号的上升沿以线性上升的方式，从低电平信号转变为高电平信号。
可选地，在本公开实施例中，所述第一扫描信号的下降沿以线性下降的方式，从高电平信号转变为低电平信号。
可选地，在本公开实施例中，所述驱动电路包括：驱动晶体管；
所述驱动晶体管的第一极分别与所述电压输入电路和所述存储电路相连，所述驱动晶体管的栅极分别与所述导通控制电路和所述数据写入电路相连，所述驱动晶体管的第二极与所述发光器件的第一极相连。
可选地，在本公开实施例中，所述存储电路包括：存储电容；
所述存储电容的第一端与所述驱动电路的输入端耦接，所述存储电容的第二端与所述连接节点耦接。
可选地，在本公开实施例中，所述导通控制电路包括：第三开关晶体管；
所述第三开关晶体管的栅极用于接收第三扫描信号，所述第三开关晶体管的第一极与所述连接节点耦接，所述第三开关晶体管的第二极与所述驱动电路的控制端耦接。
可选地，在本公开实施例中，所述第三扫描信号与所述第一扫描信号为同一信号。
可选地，在本公开实施例中，所述电压输入电路包括：第四开关晶体管；
所述第四开关晶体管的栅极用于接收第二扫描信号，所述第四开关晶体管的第一极用于接收所述第一电源信号，所述第四开关晶体管的第二极与所述驱动电路的输入端耦接。
可选地，在本公开实施例中，所述数据写入电路包括：第五开关晶体管；
所述第五开关晶体管的栅极用于接收第一扫描信号，所述第五开关晶体管的第一极用于接收所述数据信号，所述第五开关晶体管的第二极与所述驱 动电路的控制端耦接。
可选地，在本公开实施例中，所述阵列基板还包括：所述发光器件包括：电致发光二极管；
所述电致发光二极管的阳极作为所述发光器件的第一电极，所述电致发光二极管的阴极用于接收第二电源信号。
相应地，本公开实施例还提供了电致发光显示面板，其中，包括本公开实施例提供的像素补偿电路。
相应地，本公开实施例还提供了显示装置，其中，包括本公开实施例提供的电致发光显示面板。
相应地，本公开实施例提供的像素补偿电路的驱动方法，其中，所述方法包括：
复位阶段，所述数据写入电路将数据信号提供给所述驱动电路的控制端；所述电压输入电路将第一电源信号提供给所述驱动电路的输入端；所述放电控制电路对所述连接节点与所述发光器件的第一电极的电压进行复位；
阈值补偿阶段，所述数据写入电路将数据信号提供给所述驱动电路的控制端；所述放电控制电路控制所述驱动电路将所述驱动电路的阈值电压写入所述驱动电路的输入端；所述存储电路存储所述驱动电路的输入端和连接节点的电压；
发光阶段，所述电压输入电路将第一电源信号提供给所述驱动电路的输入端；所述存储电路存储所述驱动电路的输入端和连接节点的电压；所述导通控制电路导通所述连接节点与所述驱动电路的控制端；所述驱动电路产生流向所述发光器件的第一电极的驱动电流，以驱动所述发光器件发光。
附图说明
图1为本公开实施例提供的像素补偿电路的结构示意图；
图2为本公开实施例提供的像素补偿电路的具体结构示意图之一；
图3为本公开实施例提供的像素补偿电路的具体结构示意图之二；
图4为本公开实施例提供的像素补偿电路的具体结构示意图之三；
图5a为本公开实施例提供的电路时序图之一；
图5b为本公开实施例提供的电路时序图之二；
图6为第一扫描信号的波形示意图；
图7a为第一扫描信号的仿真模拟图；
图7b为驱动电路的输出端输出的电流的仿真模拟图；
图8为本公开实施例提供的驱动方法的流程图。
具体实施方式
目前，为了解决驱动电路的阈值电压V th与IR Drop导致的亮度不均匀现象，OLED显示器中一般采用可以补偿阈值电压V th与IR Drop的像素补偿电路来驱动OLED发光。然而，相关的OLED显示器的像素补偿电路中包括的开关晶体管的个数较多且电路工作时序较复杂，导致工艺难度较大，生产成本增加，以及导致像素补偿电路占用较大面积。并且，目前像素补偿电路的充电时间较长，从而不利于OLED显示器实现高的分辨率。
基于此，本公开实施例提供了像素补偿电路，可以通过简单的结构与简单的时序来实现对驱动电路的阈值电压与电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积，有利于高分辨率的OLED显示面板的设计。
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的像素补偿电路、驱动方法、电致发光显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本公开实施例提供的一种像素补偿电路，如图1所示，包括：数据写入电路1、电压输入电路2、放电控制电路3、存储电路4、导通控制电路5、驱动电路6、发光器件L；其中，
数据写入电路1用于在复位阶段与阈值补偿阶段，将数据信号DA提供给驱动电路6的控制端；
电压输入电路2用于在复位阶段与发光阶段将第一电源信号VDD提供给驱动电路6的输入端；
存储电路4用于存储驱动电路6的输入端和连接节点N0的电压；
放电控制电路3用于在复位阶段对连接节点N0与发光器件L的第一电极的电压进行复位，以及在阈值补偿阶段控制驱动电路6将驱动电路6的阈值电压写入驱动电路6的输入端；
导通控制电路5用于在发光阶段导通连接节点N0与驱动电路6的控制端；
驱动电路6用于在发光阶段产生流向发光器件L的第一电极的驱动电流，以驱动发光器件L发光。
本公开实施例提供的像素补偿电路，在复位阶段，通过数据写入电路将数据信号提供给驱动电路的控制端，放电控制电路对连接节点与发光器件的第一电极的电压进行复位，以及电压输入电路将第一电源信号提供给驱动电路的输入端，分别对连接节点与驱动电路的输入端进行充电，提高充电速率，降低充电时间。在阈值补偿阶段，通过数据写入电路将数据信号提供给驱动电路的控制端，以及放电控制电路控制驱动电路将驱动电路的阈值电压写入驱动电路的输入端，从而可以实现写入数据信号以及对驱动电路的阈值电压V th的补偿。在发光阶段，通过电压输入电路将第一电源信号提供给驱动电路的输入端，以及导通控制电路导通连接节点与驱动电路的控制端，以实现对第一电源信号的IR Drop进行补偿，以及控制驱动电路产生驱动电流，以驱动发光器件发光。从而可以通过上述各电路的相互配合，以通过简单的结构与简单的时序实现对驱动电路的阈值电压与第一电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积，有利于高分辨率的OLED显示面板的设计。
在具体实施时，在本公开实施例提供的像素补偿电路中，如图1所示，数据写入电路1的控制端用于输入第一扫描信号SC1，输入端用于输入数据 信号DA，输出端与驱动电路6的控制端耦接；数据写入电路1用于在第一扫描信号SC1的控制下，将数据信号DA提供给驱动电路6的控制端。
电压输入电路2的控制端用于输入第二扫描信号SC2，输入端用于输入第一电源信号VDD，输出端与驱动电路6的输入端耦接；电压输入电路2用于在第二扫描信号SC2的控制下，将第一电源信号VDD提供给驱动电路6的输入端。
存储电路4的第一端与驱动电路6的输入端耦接，第二端与连接节点N0耦接。
放电控制电路3的控制端用于接收第一扫描信号SC1，输入端用于接收复位信号VINIT，输出端分别与连接节点N0、发光器件L的第一电极以及驱动电路6的输出端耦接；放电控制电路3用于在第一扫描信号SC1的控制下，将复位信号VINIT提供给连接节点N0与发光器件L的第一电极，以及控制驱动电路6将驱动电路6的阈值电压写入驱动电路6的输入端。
导通控制电路5的控制端用于接收第三扫描信号SC3，输入端与连接节点N0耦接，输出端与驱动电路6的控制端耦接；导通控制电路5用于在第三扫描信号SC3的控制下，导通连接节点N0与驱动电路6的控制端。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例中是为了更好的解释本公开，但不限制本公开。
具体地，在本公开实施例提供的像素补偿电路中，如图2所示，驱动电路6包括驱动晶体管M0，该驱动晶体管M0的第一极S分别与所述电压输入电路2和所述存储电路4相连，所述驱动晶体管M0的栅极G分别与所述导通控制电路5和所述数据写入电路1相连，所述驱动晶体管M0的第二极D与所述发光器件L的第一极相连。
具体地，在具体实施时，在本公开实施例提供的像素补偿电路中，如图2至图4所示，驱动晶体管M0可以为P型晶体管；其中，驱动晶体管M0的第一极S作为其源极，驱动晶体管M0的第二极D作为其漏极。并且该驱动晶体管M0处于饱和状态时的电流由驱动晶体管M0的源极流向其漏极。
发光器件一般在驱动晶体管处于饱和状态时的电流的作用下实现发光。并且，一般发光器件具有发光阈值电压，在发光器件两端的电压大于或等于发光阈值电压时进行发光。在具体实施时，在本公开实施例提供的上述像素补偿电路中，发光器件可以包括：电致发光二极管；其中，电致发光二极管的阳极作为发光器件的第一电极，电致发光二极管的阴极用于接收第二电源信号。具体地，电致发光二极管可以包括：OLED，或量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)。
在具体实施时，在本公开实施例提供的上述像素补偿电路中，第一电源信号的电压V dd一般为正值，复位信号的电压V init一般为负值。第二电源信号的电压V ss一般为接地电压或为负值。在实际应用中，上述各电压需要根据实际应用环境来设计确定，在此不作限定。
具体地，在具体实施时，在本公开实施例提供的像素补偿电路中，如图2至图4所示，放电控制电路3可以包括：第一开关晶体管M1与第二开关晶体管M2。其中，第一开关晶体管M1的栅极用于接收第一扫描信号SC1，第一开关晶体管M1的第一极用于接收复位信号VINIT，第一开关晶体管M1的第二端与连接节点N0耦接。第二开关晶体管M2的栅极用于接收第一扫描信号SC1，第二开关晶体管M1的第一极用于接收复位信号VINIT，第二开关晶体管M2的第二极分别与驱动电路6的输出端以及发光器件L的第一电极耦接。
在具体实施时，在本公开实施例提供的像素补偿电路中，第一开关晶体管在第一扫描信号的控制下处于导通状态时，可以将复位信号提供给连接节点。第二开关晶体管在第一扫描信号的控制下处于导通状态时，可以将复位信号提供给驱动电路的输出端与发光器件的第一电极。
在具体实施时，如图2与图4所示，第一开关晶体管M1与第二开关晶体管M2可以为N型晶体管。如图3所示，第一开关晶体管M1与第二开关晶体管M2也可以为P型晶体管，在此不作限定。
具体地，在具体实施时，在本公开实施例提供的像素补偿电路中，如图2至图4所示，存储电路4可以包括：存储电容Cst；其中，存储电容Cst的第 一端与驱动电路6的输入端耦接，存储电容Cst的第二端与连接节点N0耦接。
在具体实施时，存储电容可以根据输入驱动电路的输入端的信号与输入连接节点的信号进行充电或放电，以存储其两端的电压。在连接节点处于浮接状态时，可以通过存储电容的耦合作用，将输入驱动电路的输入端的电压耦合到连接节点。
具体地，在具体实施时，在本公开实施例提供的像素补偿电路中，如图2至图4所示，导通控制电路5可以包括：第三开关晶体管M3；其中，第三开关晶体管M3的栅极用于接收第三扫描信号SC3，第三开关晶体管M3的第一极与连接节点N0耦接，第三开关晶体管M3的第二极与驱动电路6的控制端耦接。
在具体实施时，在本公开实施例提供的像素补偿电路中，第三开关晶体管在第三扫描信号的控制下处于导通状态时，可以将连接节点与驱动电路的控制端导通，以将连接节点的信号输入驱动电路的控制端。
在具体实施时，如图2至图4所示，第三开关晶体管M3可以为P型晶体管，当然，第三开关晶体管也可以为N型晶体管，在此不作限定。
为了减少信号线的设置，节省信号端口数量，节省布线空间，在具体实施时，可以使第三扫描信号与第一扫描信号设置为同一信号。具体地，如图4所示，第一开关晶体管M1、第二开关晶体管M2以及第三开关晶体管M3的栅极均用于接收第一扫描信号SC1。并且，第一开关晶体管M1与第三开关晶体管M3的类型不同。例如，第一开关晶体管M1为N型晶体管，第三开关晶体管M3为P型晶体管。
具体地，在具体实施时，在本公开实施例提供的像素补偿电路中，如图2至图4所示，电压输入电路2可以包括：第四开关晶体管M4；其中，第四开关晶体管M4的栅极用于接收第二扫描信号SC2，第四开关晶体管M4的第一极用于接收第一电源信号VDD，第四开关晶体管M4的第二极与驱动电路6的输入端耦接。
在具体实施时，在本公开实施例提供的像素补偿电路中，第四开关晶体 管在第二扫描信号的控制下处于导通状态时，可以将第一电源信号提供给驱动电路的输入端。
在具体实施时，如图2至图4所示，第四开关晶体管M4可以为P型晶体管，当然，第四开关晶体管也可以为N型晶体管，在此不作限定。
具体地，在具体实施时，在本公开实施例提供的像素补偿电路中，如图2至图4所示，数据写入电路1可以包括：第五开关晶体管M5；其中，第五开关晶体管M5的栅极用于接收第一扫描信号SC1，第五开关晶体管M5的第一极用于接收数据信号DA，第五开关晶体管M5的第二极与驱动电路6的控制端耦接。
在具体实施时，在本公开实施例提供的像素补偿电路中，第五开关晶体管在第一扫描信号的控制下处于导通状态时，可以将数据信号提供给驱动电路的控制端。
在具体实施时，如图2与图4所示，第五开关晶体管M5可以为N型晶体管，如图3所示，第五开关晶体管M5也可以为P型晶体管，在此不作限定。
以上仅是举例说明本公开实施例提供的像素补偿电路中各电路的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
进一步地，为了简化像素补偿电路的制作工艺流程，在具体实施时，在本公开实施例提供的上述像素补偿电路中，如图3所示，在驱动晶体管M0为P型晶体管时，所有的晶体管可以均为P型晶体管。
在具体实施时，在本公开实施例提供的上述像素补偿电路中，P型晶体管在高电平作用下截止，在低电平作用下导通；N型晶体管在高电平作用下导通，在低电平作用下截止。
需要说明的是，本公开实施例提供的上述像素补偿电路中的晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不作限定。在具体实施时， 可以根据开关晶体管类型以及信号的电压的不同，可以将开关晶体管的第一极作为其源极，第二极作为其漏极；或者反之，将第一极作为其漏极，第二极作为其源极，在此不做具体区分。
下面结合电路时序图对本公开实施例提供的上述像素补偿电路的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各开关晶体管的栅极上的电压。
在一些可能的实施方式中，以图2所示的像素补偿电路的结构为例，其对应的电路时序图如图5a所示。在图5a中，主要选取复位阶段T1、阈值补偿阶段T2以及发光阶段T3。
在复位阶段T1，SC1＝1，SC2＝0，SC3＝1。
由于SC1＝1，因此第一开关晶体管M1、第二开关晶体管M2以及第五开关晶体管M5均导通。导通的第一开关晶体管M1将复位信号VINIT提供给连接节点N0，以对连接节点N0进行复位。导通的第二开关晶体管M2将复位信号VINIT提供给驱动晶体管M0的第二极D与发光器件L的阳极，以对发光器件L的阳极进行复位。导通的第五开关晶体管M5将数据信号DA提供给驱动晶体管M0的栅极G。由于SC2＝0，因此第四开关晶体管M4导通，并将第一电源信号VDD提供给驱动晶体管M0的第一极S，以对驱动晶体管的M0的第一极S进行复位，并对存储电容Cst进行充电。此时，驱动晶体管M0的栅极的电压V G为数据信号DA的电压V da，驱动晶体管M0的第一极S的电压V S为第一电源信号VDD的电压V dd，驱动晶体管M0的第二极D的电压V D为复位信号VINIT的电压V init。因此，驱动晶体管M0会产生由其第一极S流向第二极D的电流，该电流通过第二开关晶体管M2释放，从而可以避免本阶段中由于驱动晶体管M0产生的电流而导致发光器件L提前开启。由于SC3＝1，因此第三开关晶体管M3截止。
在阈值补偿阶段T2，SC1＝1，SC2＝1，SC3＝1。
由于SC1＝1，因此第一开关晶体管M1、第二开关晶体管M2以及第五开 关晶体管M5均导通。导通的第一开关晶体管M1将复位信号VINIT提供给连接节点N0，使连接节点N0的电压V N0为V init。导通的第二开关晶体管M2将复位信号VINIT提供给驱动晶体管M0的第二极D。导通的第五开关晶体管M5将数据信号DA提供给驱动晶体管M0的栅极G，使V G＝V da。由于SC2＝1，因此第四开关晶体管M4截止。由于存储电容Cst的作用，驱动晶体管M0的第一极S的电压V S可以先保持为V dd，因此，驱动晶体管M0会产生由其第一极S流向第二极D的电流，该电流通过第二开关晶体管M2释放，从而使得V S的电压下降，即存储电容Cst进行放电，直至驱动晶体管M0的第一极的电压V S变为V da-V th，驱动晶体管M0关闭，从而实现对驱动晶体管M0的阈值电压V th的补偿。并且，由于本阶段中驱动晶体管M0产生的电流可以通过第二开关晶体管M2释放，从而可以减少漏电流进入发光器件L，从而增加黑画面的时间，进而可以改善短时残像的问题。由于SC3＝1，因此第三开关晶体管M3截止。
在发光阶段T3，SC1＝0，SC2＝0，SC3＝0。
由于SC1＝0，因此第一开关晶体管M1、第二开关晶体管M2以及第五开关晶体管M5均截止，连接节点N0处于浮接状态。由于SC2＝0，因此第四开关晶体管M4导通，并将第一电源信号VDD提供给驱动晶体管M0的第一极S，使电压V S＝V dd。由于连接节点N0处于浮接状态，通过存储电容Cst的耦合作用，连接节点N0的电压V N0可以跳变为：V init+V dd-V da+V th。由于SC3＝0，因此第三开关晶体管M3导通，使V G＝V init+V dd-V da+V th。根据饱和状态电流特性，驱动晶体管M0产生的用于驱动发光器件L发光的驱动电流I L满足公式：I L＝K(V GS-V th) 2＝K[V init+V dd-V da+V th-V dd-V th] 2＝K[V init-V da] 2。其中，V GS为驱动晶体管M0的栅源电压；并且，K为结构参数，且
Figure PCTCN2019070056-appb-000001
μ代表驱动晶体管M0的迁移率，C o代表单位面积栅氧化层电容，
Figure PCTCN2019070056-appb-000002
代表驱动晶体管M0的宽长比，相同结构中这些数值相对稳定，可以算作常量。通过上式可知，驱动晶体管M0产生的驱动电流I L仅与复位信号VINIT的电压V init 和数据信号DA的电压V da相关，而与驱动晶体管M0的阈值电压V th以及第一电源信号VDD的电压V dd无关，可以解决由于驱动晶体管M0的阈值电压V th漂移以及IR Drop对驱动电流I L的影响，从而使发光器件L的驱动电流保持稳定，进而保证了发光器件L的正常工作。
并且，在发光阶段T3中，由于电压V dd需要通过存储电容Cst的耦合作用耦合到连接节点N0中，因此为了避免第四开关晶体管M4与第一开关晶体管M1同时导通，对电容Cst保存的连接节点N0的电压造成不利影响，在具体实施时，在发光阶段T3开始的一段时间内，可以使SC1＝0，SC2＝1，SC3＝0，以在第四开关晶体管M4还处于截止状态时控制第一开关晶体管M1完全关闭。在该时间之后使SC1＝0，SC2＝0，SC3＝0，以控制第四开关晶体管M4由截止变为导通状态，使电压V dd通过存储电容Cst的耦合作用耦合到连接节点N0中。
本公开提供的上述实施例中，通过上述各晶体管与存储电容之间的相互配合，可以通过简单的结构与简单的时序，实现对驱动晶体管的阈值电压V th与第一电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积。并且，在具体实施时，由于第一电源信号的电压一般为固定电压值的电压，在复位阶段中采用第一电源信号对存储电容进行充电，可以提高存储电容的充电速率，降低充电时间，从而可以提高电路的处理速率，进而有利于应用于高分辨率的显示面板的设计中。
在又一些可能的实施方式中，以图4所示的像素补偿电路的结构为例，其对应的电路时序图如图5b所示。在图5b中，主要选取复位阶段T1、阈值补偿阶段T2以及发光阶段T3。
在复位阶段T1，SC1＝1，SC2＝0。由于SC1＝1，因此第一开关晶体管M1、第二开关晶体管M2以及第五开关晶体管M5均导通，而第三开关晶体管M3截止。由于SC2＝0，因此第四开关晶体管M4导通。因此，本阶段中的工作过程与实施例一中的复位阶段T1的工作过程基本相同，在此不作赘述。
在阈值补偿阶段T2，SC1＝1，SC2＝1。由于SC1＝1，因此第一开关晶体 管M1、第二开关晶体管M2以及第五开关晶体管M5均导通，而第三开关晶体管M3截止。由于SC2＝1，因此第四开关晶体管M4截止。因此，本阶段中的工作过程与实施例一中的阈值补偿阶段T2的工作过程基本相同，在此不作限定。
在发光阶段T3，SC1＝0，SC2＝0。由于SC1＝0，因此第三开关晶体管M3导通，而第一开关晶体管M1、第二开关晶体管M2以及第五开关晶体管M5均截止，连接节点N0处于浮接状态。由于SC2＝0，因此第四开关晶体管M4导通。因此，本阶段中的工作过程与实施例一中的发光阶段T3的工作过程基本相同，在此不作限定。
并且，为了避免第四开关晶体管M4与第一开关晶体管M1同时导通，对电容Cst保存的连接节点N0的电压造成不利影响，在具体实施时，在发光阶段T3开始的一段时间内，可以使SC1＝0，SC2＝1，以在第四开关晶体管M4还处于截止状态时控制第一开关晶体管M1完全关闭。在该时间之后使SC1＝0，SC2＝0，以控制第四开关晶体管M4由截止变为导通状态，使电压V dd通过存储电容Cst的耦合作用耦合到连接节点N0中。
本公开提供的上述实施例中，通过上述各晶体管与存储电容之间的相互配合，可以通过简单的结构与简单的时序，实现对驱动晶体管的阈值电压V th与第一电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积。并且，在具体实施时，由于第一电源信号的电压一般为固定电压值的电压，在复位阶段中采用第一电源信号对存储电容进行充电，可以提高存储电容的充电速率，降低充电时间，从而可以提高电路的处理速率，进而有利于应用于高分辨率的显示面板的设计中。
在实际应用中，在第一扫描信号进行高低电平切换时，例如图5a与图5b中，第一扫描信号SC1直接由低电平信号切换为高电平信号，或由高电平信号切换为低电平信号时，会导致驱动晶体管M0出现电流值较大的尖峰电流，从而可能会对电路造成影响。为了改善尖峰电流的影响，在具体实施时，如图6所示，可以使第一扫描信号SC1的上升沿以线性上升的方式，使第一扫 描信号SC1从低电平信号逐渐变为高电平信号。例如图7a与图7b所示，图7a为第一扫描信号SC1的仿真模拟图，其中，横坐标代表时间，纵坐标代表电压值。图7b为驱动晶体管M0的第二极D流出的电流的仿真模拟图，其中，横坐标代表时间，纵坐标代表电流值。从图7a与图7b中可以看出，通过使第一扫描信号SC1由-7V以线性上升的方式渐变到7V，可以使驱动晶体管M0的第二极D流出的电流稳定，从而可以避免出现尖峰电流。
当然，如图6所示，也可以使第一扫描信号SC1的下降沿以线性下降的方式，使第一扫描信号SC1从高电平信号逐渐变为低电平信号。例如图7a与图7b所示，通过使第一扫描信号SC1由7V以线性下降的方式渐变到-7V，可以使驱动晶体管M0的第二极D流出的电流稳定，从而可以避免出现尖峰电流。
基于同一发明构思，本公开实施例还提供了本公开实施例提供的像素补偿电路的驱动方法。该驱动方法解决问题的原理与前述像素补偿电路相似，因此该驱动方法的实施可以参见前述像素补偿电路的实施，重复之处在此不再赘述。
如图8所示，本公开实施例提供的像素补偿电路的驱动方法可以包括：
S801、复位阶段，数据写入电路将数据信号提供给驱动电路的控制端；电压输入电路将第一电源信号提供给驱动电路的输入端；放电控制电路对连接节点与发光器件的第一电极的电压进行复位。
S802、阈值补偿阶段，数据写入电路将数据信号提供给驱动电路的控制端；放电控制电路控制驱动电路将驱动电路的阈值电压写入驱动电路的输入端；存储电路存储驱动电路的输入端和连接节点的电压。
S803、发光阶段，电压输入电路将第一电源信号提供给驱动电路的输入端；存储电路存储驱动电路的输入端和连接节点的电压；导通控制电路导通连接节点与驱动电路的控制端；驱动电路产生流向发光器件的第一电极的驱动电流，以驱动发光器件发光。
本公开实施例提供的上述驱动方法，可以通过简单的结构与简单的时序 实现对驱动电路的阈值电压与第一电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积，有利于高分辨率的OLED显示面板的设计。
基于同一发明构思，本公开实施例还提供了电致发光显示面板，包括本公开实施例提供的上述像素补偿电路。该电致发光显示面板解决问题的原理与前述像素补偿电路相似，因此该电致发光显示面板的实施可以参见前述像素补偿电路的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的电致发光显示面板可以包括有机发光显示面板、量子点发光显示面板。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述电致发光显示面板。该显示装置的实施可以参见上述像素补偿电路的实施例，重复之处不再赘述。
在具体实施时，本公开实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的像素补偿电路、驱动方法、电致发光显示面板及显示装置，在复位阶段，通过数据写入电路将数据信号提供给驱动电路的控制端，放电控制电路对连接节点与发光器件的第一电极的电压进行复位，以及电压输入电路将第一电源信号提供给驱动电路的输入端，分别对连接节点与驱动电路的输入端进行充电，提高充电速率，降低充电时间。在阈值补偿阶段，通过数据写入电路将数据信号提供给驱动电路的控制端，以及放电控制电路控制驱动电路将驱动电路的阈值电压写入驱动电路的输入端，从而可以实现写入数据信号以及对驱动电路的阈值电压V th的补偿。在发光阶段，通过电压输入电路将第一电源信号提供给驱动电路的输入端，以及导通控制电路导通连接节点与驱动电路的控制端，以实现对第一电源信号的IR Drop进行补偿，以及控制驱动电路产生驱动电流，以驱动发光器件发光。从而可以通过 上述各电路的相互配合，以通过简单的结构与简单的时序实现对驱动电路的阈值电压与第一电源信号的IR Drop的补偿，从而可以简化制备工艺、降低生产成本以及减小占用面积，有利于高分辨率的OLED显示面板的设计。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种像素补偿电路，其中，包括：
    数据写入电路，用于在复位阶段与阈值补偿阶段，将数据信号提供给驱动电路的控制端；
    电压输入电路，用于在所述复位阶段与发光阶段将第一电源信号提供给所述驱动电路的输入端；
    存储电路，用于存储所述驱动电路的输入端和连接节点的电压；
    放电控制电路，用于在所述复位阶段对所述连接节点与发光器件的第一电极的电压进行复位，以及在所述阈值补偿阶段控制所述驱动电路将所述驱动电路的阈值电压写入所述驱动电路的输入端；
    导通控制电路，用于在所述发光阶段导通所述连接节点与所述驱动电路的控制端；
    所述驱动电路，用于在所述发光阶段产生流向所述发光器件的第一电极的驱动电流，以驱动所述发光器件发光。
  2. 根据权利要求1所述的像素补偿电路，其中，所述数据写入电路的控制端用于输入第一扫描信号，输入端用于输入所述数据信号，输出端与所述驱动电路的控制端耦接；所述数据写入电路用于在所述第一扫描信号的控制下，将所述数据信号提供给所述驱动电路的控制端；
    所述电压输入电路的控制端用于输入第二扫描信号，输入端用于输入所述第一电源信号，输出端与所述驱动电路的输入端耦接；所述电压输入电路用于在所述第二扫描信号的控制下，将所述第一电源信号提供给所述驱动电路的输入端；
    所述存储电路的第一端与所述驱动电路的输入端耦接，第二端与所述连接节点耦接；
    所述放电控制电路的控制端用于接收所述第一扫描信号，输入端用于接收复位信号，输出端分别与所述连接节点、所述发光器件的第一电极以及所 述驱动电路的输出端耦接；所述放电控制电路用于在所述第一扫描信号的控制下，将所述复位信号提供给所述连接节点与所述发光器件的第一电极，以及控制所述驱动电路将所述驱动电路的阈值电压写入所述驱动电路的输入端；
    所述导通控制电路的控制端用于接收第三扫描信号，输入端与所述连接节点耦接，输出端与所述驱动电路的控制端耦接；所述导通控制电路用于在所述第三扫描信号的控制下，导通所述连接节点与所述驱动电路的控制端。
  3. 根据权利要求1所述的像素补偿电路，其中，所述放电控制电路包括：第一开关晶体管与第二开关晶体管；
    所述第一开关晶体管的栅极用于接收第一扫描信号，所述第一开关晶体管的第一极用于接收复位信号，所述第一开关晶体管的第二端与所述连接节点耦接；
    所述第二开关晶体管的栅极用于接收所述第一扫描信号，所述第二开关晶体管的第一极用于接收所述复位信号，所述第二开关晶体管的第二极分别与所述驱动电路的输出端以及所述发光器件的第一电极耦接。
  4. 根据权利要求2或3所述的像素补偿电路，其中，所述第一扫描信号的上升沿以线性上升的方式，从低电平信号转变为高电平信号。
  5. 根据权利要求2或3所述的像素补偿电路，其中，所述第一扫描信号的下降沿以线性下降的方式，从高电平信号转变为低电平信号。
  6. 根据权利要求1所述的像素补偿电路，其中，所述驱动电路包括：驱动晶体管；
    所述驱动晶体管的第一极分别与所述电压输入电路和所述存储电路相连，所述驱动晶体管的栅极分别与所述导通控制电路和所述数据写入电路相连，所述驱动晶体管的第二极与所述发光器件的第一极相连。
  7. 根据权利要求1所述的像素补偿电路，其中，所述存储电路包括：存储电容；
    所述存储电容的第一端与所述驱动电路的输入端耦接，所述存储电容的第二端与所述连接节点耦接。
  8. 根据权利要求1所述的像素补偿电路，其中，所述导通控制电路包括：第三开关晶体管；
    所述第三开关晶体管的栅极用于接收第三扫描信号，所述第三开关晶体管的第一极与所述连接节点耦接，所述第三开关晶体管的第二极与所述驱动电路的控制端耦接。
  9. 根据权利要求8所述的像素补偿电路，其中，所述第三扫描信号与所述第一扫描信号为同一信号。
  10. 根据权利要求1所述的像素补偿电路，其中，所述电压输入电路包括：第四开关晶体管；
    所述第四开关晶体管的栅极用于接收第二扫描信号，所述第四开关晶体管的第一极用于接收所述第一电源信号，所述第四开关晶体管的第二极与所述驱动电路的输入端耦接。
  11. 根据权利要求1所述的像素补偿电路，其中，所述数据写入电路包括：第五开关晶体管；
    所述第五开关晶体管的栅极用于接收第一扫描信号，所述第五开关晶体管的第一极用于接收所述数据信号，所述第五开关晶体管的第二极与所述驱动电路的控制端耦接。
  12. 根据权利要求1所述的像素补偿电路，其中，所述发光器件包括：电致发光二极管；
    所述电致发光二极管的阳极作为所述发光器件的第一电极，所述电致发光二极管的阴极用于接收第二电源信号。
  13. 一种电致发光显示面板，其中，包括权利要求1～12任一所述的像素补偿电路。
  14. 一种显示装置，其中，包括权利要求13所述的电致发光显示面板。
  15. 一种如权利要求1-12任一项所述的像素补偿电路的驱动方法，其中，所述方法包括：
    复位阶段，所述数据写入电路将数据信号提供给所述驱动电路的控制端； 所述电压输入电路将第一电源信号提供给所述驱动电路的输入端；所述放电控制电路对所述连接节点与所述发光器件的第一电极的电压进行复位；
    阈值补偿阶段，所述数据写入电路将数据信号提供给所述驱动电路的控制端；所述放电控制电路控制所述驱动电路将所述驱动电路的阈值电压写入所述驱动电路的输入端；所述存储电路存储所述驱动电路的输入端和所述连接节点的电压；
    发光阶段，所述电压输入电路将第一电源信号提供给所述驱动电路的输入端；所述存储电路存储所述驱动电路的输入端和所述连接节点的电压；所述导通控制电路导通所述连接节点与所述驱动电路的控制端；所述驱动电路产生流向所述发光器件的第一电极的驱动电流，以驱动所述发光器件发光。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883061A (zh) * 2020-07-31 2020-11-03 维沃移动通信有限公司 像素电路、显示装置、电子设备及像素电路的驱动方法

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TWI714317B (zh) 2019-10-23 2020-12-21 友達光電股份有限公司 畫素電路與相關的顯示裝置
CN111292684A (zh) * 2020-03-31 2020-06-16 京东方科技集团股份有限公司 显示面板、像素驱动电路及其控制方法
CN111739470B (zh) * 2020-07-28 2021-11-30 京东方科技集团股份有限公司 像素驱动电路、驱动方法及显示面板
CN114822387B (zh) * 2021-01-28 2023-11-14 成都辰显光电有限公司 像素电路和显示面板
CN115909970A (zh) * 2021-09-30 2023-04-04 昆山国显光电有限公司 像素电路及其驱动方法和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456267A (zh) * 2013-08-26 2013-12-18 北京京东方光电科技有限公司 触控显示驱动电路及其驱动方法和显示装置
CN104409047A (zh) * 2014-12-18 2015-03-11 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN106548753A (zh) * 2017-01-20 2017-03-29 深圳市华星光电技术有限公司 Amoled像素驱动系统及amoled像素驱动方法
CN106782321A (zh) * 2017-01-12 2017-05-31 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396175B (zh) * 2008-10-15 2013-05-11 Raydium Semiconductor Corp 源極驅動裝置
KR101509113B1 (ko) * 2008-12-05 2015-04-08 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
WO2013179847A1 (ja) * 2012-05-30 2013-12-05 シャープ株式会社 表示装置およびその駆動方法
CN102789761B (zh) * 2012-08-06 2014-12-10 京东方科技集团股份有限公司 像素电路及其驱动方法和有机发光显示器
CN103021331B (zh) * 2012-11-30 2016-02-24 北京京东方光电科技有限公司 一种像素驱动电路及其驱动方法、阵列基板和显示装置
CN104700776B (zh) * 2015-03-25 2016-12-07 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN106486051B (zh) * 2015-08-25 2020-07-31 群创光电股份有限公司 像素结构
CN106486063A (zh) * 2016-10-26 2017-03-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN107452331B (zh) * 2017-08-25 2023-12-05 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107610652B (zh) 2017-09-28 2019-11-19 京东方科技集团股份有限公司 像素电路、其驱动方法、显示面板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456267A (zh) * 2013-08-26 2013-12-18 北京京东方光电科技有限公司 触控显示驱动电路及其驱动方法和显示装置
CN104409047A (zh) * 2014-12-18 2015-03-11 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN106782321A (zh) * 2017-01-12 2017-05-31 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN106548753A (zh) * 2017-01-20 2017-03-29 深圳市华星光电技术有限公司 Amoled像素驱动系统及amoled像素驱动方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883061A (zh) * 2020-07-31 2020-11-03 维沃移动通信有限公司 像素电路、显示装置、电子设备及像素电路的驱动方法

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