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WO2019029397A1 - 一种交织方法及装置 - Google Patents

一种交织方法及装置 Download PDF

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Publication number
WO2019029397A1
WO2019029397A1 PCT/CN2018/097782 CN2018097782W WO2019029397A1 WO 2019029397 A1 WO2019029397 A1 WO 2019029397A1 CN 2018097782 W CN2018097782 W CN 2018097782W WO 2019029397 A1 WO2019029397 A1 WO 2019029397A1
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WIPO (PCT)
Prior art keywords
group
interleaving
subsequence
sub
sequence
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PCT/CN2018/097782
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English (en)
French (fr)
Inventor
王桂杰
王坚
乔云飞
杜颖钢
Original Assignee
华为技术有限公司
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Priority claimed from CN201710703557.5A external-priority patent/CN109391365B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18844627.2A priority Critical patent/EP3605904B1/en
Publication of WO2019029397A1 publication Critical patent/WO2019029397A1/zh
Priority to US16/705,647 priority patent/US10972220B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the embodiments of the present application relate to the field of communications technologies, and in particular, to an interleaving method and apparatus.
  • the rapid evolution of wireless communication indicates that the fifth generation (5th generation, 5G) communication system will present some new features.
  • the most typical three communication scenarios include enhanced mobile broadband (eMBB) and massive machine connection.
  • eMBB enhanced mobile broadband
  • LTE long term evolution
  • mMTC massive machine type communication
  • URLLC ultra reliable low latency communication
  • channel coding is one of the important research objects to meet the needs of 5G communication.
  • the formulation of the 5G standard has been in full swing, and Polar Codes have also been selected as the control channel coding method.
  • the polarization code also known as the Polar code, is the first and only known channel coding method that can be rigorously proven to "reach" the channel capacity.
  • Polar codes Under different code lengths, especially for finite codes, the performance of Polar codes is much better than Turbo codes and low density parity check (LDPC) codes. In addition, Polar codes have lower computational complexity in terms of encoding and decoding. These advantages make Polar code have great development and application prospects in 5G.
  • some channel coding is added to the interleaving module.
  • many composite channels where random errors and burst errors occur simultaneously, such as short-wave and troposcatter when an error occurs, the next string of data is affected, causing the burst error to exceed the error correction capability of the error-correcting code. Reduce the ability to correct errors. If the burst error is first discretized into random errors and then the random error is corrected, the anti-jamming performance of the system will be further improved.
  • the error correction encoder at the transmitting end is connected to the digital interleaving unit, and the receiving end demodulates and deinterleaves.
  • the interleaving deinterleaving circuit By the function of the interleaving deinterleaving circuit, the sudden error channel is transformed into an independent random error channel, and the burst error is expanded. The error discretization is realized, and the burst error is spread within the error correction encoder error correction range to improve the channel error correction capability.
  • the embodiment of the present application provides an interleaving method and apparatus for improving the randomness of the Polar code interleaving.
  • an interleaving method in which a bit sequence to be interleaved is once interleaved or grouped, so that a range of bits in the same group covers a larger range of the bit sequence to be interleaved, and then the bits in the group are performed.
  • Interleaving which can help to avoid the limitation of intra-group bit interleaving.
  • different groups of intra-group interleaving adopt different interleaving methods. For example, if row-row interleaving is used, in the case of fixed rows, different groups of groups The inner interleaving uses different number of rows.
  • a bit sequence to be interleaved is obtained, the bit sequence to be interleaved includes L sub-sequences, the L sub-sequences include S sub-sequence groups, and the S sub-sequence groups include at least a first sub-sequence group and a second subsequence set, the first subsequence set includes at least 2 subsequences, the second subsequence set includes at least 1 subsequence, and L is a positive integer greater than 1, for the first subsequence set
  • the subsequences are interleaved in a first interleaving manner, and the subsequences in the second subsequence group are not interleaved or interleaved in a second interleaving manner.
  • the interleaved data can be more discretely randomized, which is more helpful to improve the performance of Polar.
  • the results of the modulo operations of the respective numbers of the subsequences in the first subsequence group according to the set values are all the first operation results; the subsequences in the second subsequence group The results of the modulo operations for each of the respective numbers according to the set values are the second calculation results.
  • the first operation result is different from the second operation result. For example, the remainder is divided by the set number to obtain the remainder, and the remainder is divided into the same group.
  • the first interleaving manner is a first row and column interleaving
  • the second interleaving manner is a second row and column interleaving
  • the number of rows of the first row and column interleaving and the second row and column interleaving is different or column The number is different. That is, the first sub-sequence set and the second sub-sequence adopt an interleaving manner of different interleaving depths. In this way, it is easy to parallelly process in hardware implementation, and the addressing calculation is convenient, and the interleaved bit sequence is more random and discrete.
  • interleaving the subsequences in the first subsequence group by using a first interleaving manner may be implemented by: inputting all bits in the first subsequence group bit by bit into an interleaver Row-and-column interleaving is performed; or some or all of the sub-sequences in the first sub-sequence set are interleaved in a sub-sequence.
  • the sub-sequences in the second sub-sequence group are interleaved by using a second interleaving manner, which may be implemented by: inputting all the bits in the second sub-sequence group bit by bit into the interleaver Row-and-column interleaving is performed; or some or all of the subsequences in the second subsequence set are respectively interleaved in the subsequence.
  • the sub-sequences in the first sub-sequence group are interleaved by using a first interleaving manner, which may be implemented by interleaving the positions of the sub-sequences in the first sub-sequence group. Processing, inputting all the bits in the first sub-sequence group into the row-column interleaver for row-row interleaving, or performing inter-row interleaving in each sub-sequence in the first sub-sequence group.
  • the sub-sequences in the second sub-sequence group are interleaved by using a second interleaving manner, which may be implemented by interleaving the positions of the sub-sequences in the second sub-sequence group. Processing, inputting all the bits in the second sub-sequence set into the row-column interleaver for row-column interleaving, or performing inter-row interleaving in each sub-sequence of the second sub-sequence set in the sub-sequence.
  • the M is the length of the bit sequence to be interleaved; if j is known, The M is the length of the bit sequence to be interleaved.
  • the sub-sequences in the first sub-sequence group are interleaved by using a first interleaving manner, and the sub-sequences in the second sub-sequence group are not Before interleaving or interleaving in a second interleaving manner, the L subsequences are grouped to obtain the first subsequence set and the second subsequence set.
  • S sub-sequence groups can be obtained by modulo S-numbering the sub-sequences separately, modulo S-module, and S-determining the group of sub-sequence groups that need to be divided. number.
  • the numbers of the same operation result are grouped into one group. For example, the operation result of the modulo S of each subsequence number of the first subsequence group is the first operation result, and the operation result of the modulo S of each subsequence number of the second subsequence group is the second operation result.
  • the S subsequence groups can be obtained by using the bit reverse order operation on the numbers 1 to L of the subsequences to obtain a new number sorting sequence, according to the determined number of groups S of the subsequence groups, according to or The operation determines the number m of sub-sequences in a group, determines a set of m numbers from the obtained new numbered sorting sequence, and determines the sub-sequence of each group according to the number of each group.
  • the number of subsequences of the last group may be less than or equal to m.
  • the numbered sequence that is obtained by using the bit reverse sequence operation on the number 1 to L of the subsequence includes a value greater than L, and the bit reverse sequence operation obtains the sequence and sequentially rearranges the obtained sequence.
  • the sequence of positions continues the flow of the above selection according to the sequence of positions.
  • the S subsequence groups can be obtained by selecting the numbers from 1 to L according to the fixed interval G, obtaining the first group number, and removing the first group number in the numbers 1 to L; Then, select the number from the culled number according to the fixed interval G, obtain the second group number, and cull the second group number; and so on, perform the above similar operation until the last group number is selected.
  • the S subsequence groups can be obtained by operating the numbers 1 to L of the subsequences according to the method of the method 3, and obtaining a new numbered sorting sequence according to the selected group numbers, according to the determined subsequences.
  • Group number of groups S according to or The operation determines the number m of sub-sequences in a group, determines a set of m numbers from the obtained new numbered sorting sequence, and determines the sub-sequence of each group according to the number of each group.
  • the number of subsequences of the last group may be less than or equal to m.
  • the numbered sequence that is obtained by using the bit reverse sequence operation on the number 1 to L of the subsequence includes a value greater than L, and the bit reverse sequence operation obtains the sequence and sequentially rearranges the obtained sequence.
  • the sequence of positions continues the flow of the above selection according to the sequence of positions.
  • S subsequence groups can be obtained by selecting the minimum, maximum and intermediate values as the first group number according to the number 1 to L of each subsequence, and the middle value is the maximum of the number sorting sequence.
  • the value is divided by 2 or rounded down, and the first group number is removed from the numbers 1 to L; similarly, the minimum, maximum, and intermediate values are selected from the number after the rejection, and the second group number is The second set of numbers is removed; and so on, similar operations are performed until the last set of numbers is selected.
  • the S subsequence groups can be obtained by operating the numbers 1 to L of the subsequences according to the method of the method 5, and obtaining a new numbered sorting sequence according to the selected group numbers, according to the determined subsequences.
  • Group number of groups S according to or The operation determines the number m of sub-sequences in a group, determines a set of m numbers from the obtained new numbered sorting sequence, and determines the sub-sequence of each group according to the number of each group.
  • the number of subsequences of the last group may be less than or equal to m.
  • the numbered sequence that is obtained by using the bit reverse sequence operation on the number 1 to L of the subsequence includes a value greater than L, and the bit reverse sequence operation obtains the sequence and sequentially rearranges the obtained sequence.
  • the sequence of positions continues the flow of the above selection according to the sequence of positions.
  • the sub-sequence number L and the sub-sequence group number S can be determined by at least a combination of several factors. For example, one can be associated with a modulation order, and the number of subsequence groups S is a function of a modulation order; second, it can also be associated with an actual hardware implementation, where S is a power of 2 in hardware implementation. Easy to operate; third, it can also be associated with randomization as much as possible, S is as prime as possible.
  • L takes one of the following values: 16, 31, 32, 64, 7, 11, 13, 19, 23, 29, 37, 61.
  • the locations of the first subsequence set and the second subsequence set are interleaved.
  • an interlacing device having the functionality to implement the method described in the first aspect and any of the possible designs of the first aspect.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the interleaving device when part or all of the function is implemented by hardware, the interleaving device comprises: an input interface circuit for acquiring a bit sequence to be interleaved; and a logic circuit for performing the above first aspect and The behavior described in any of the possible designs of the first aspect; an output interface circuit for outputting the interleaved bit sequence.
  • the interleaving device may be a chip or an integrated circuit.
  • the interleaving device when part or all of the function is implemented by software, the interleaving device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the interleaving device can implement the method as described in the first aspect and any of the possible designs of the first aspect.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the interleaving device when some or all of the functionality is implemented in software, the interleaving device includes a processor.
  • a memory for storing a program is located outside the interleaving device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • a communication system comprising a transmitting end and a receiving end, the transmitting end being capable of performing the method as described in the first aspect above and its possible design.
  • a computer storage medium stored with a computer program comprising instructions for performing the method of any of the first aspect and any of the possible aspects of the first aspect.
  • an embodiment of the present application provides a computer program product comprising instructions, which when executed on a computer, cause the computer to perform the method described in the above aspects.
  • 1(a) and 1(b) are schematic diagrams showing the architecture of a communication system applied in an embodiment of the present application
  • FIG. 2 is a schematic diagram showing the travel of the interleaved interleaver in the embodiment of the present application
  • FIG. 3 is a schematic flowchart of an interleaving method in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a method for obtaining a subsequence group in the embodiment of the present application.
  • FIG. 5 is a schematic diagram of an interleaving process according to mode 1 in the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an interleave device according to an embodiment of the present application.
  • FIG. 8 is a second schematic structural diagram of an interleaving device according to an embodiment of the present application.
  • FIG. 9 is a third schematic structural diagram of an interleaving apparatus according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a deinterleaving apparatus according to an embodiment of the present application.
  • FIG. 11 is a second schematic structural diagram of a deinterleaving device according to an embodiment of the present application.
  • FIG. 12 is a third schematic structural diagram of a deinterleaving device according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a network device and a terminal in an embodiment of the present application.
  • the embodiment of the present application provides an interleaving method and apparatus, by performing interleaving or grouping of bit sequences to be interleaved, so that the bits in the same group cover a larger range on the bit sequence to be interleaved, and then Bits are interleaved, which can help to avoid the limitation of intra-group bit interleaving.
  • different groups of intra-group interleaving adopt different interleaving methods. For example, if row-row interleaving is used, in the case of fixed lines, different groups The intra-group interleaving uses different number of rows. In the case of fixed columns, different groups of intra-group interleaving use different number of columns, so that the interleaved sequences are more random.
  • the interleaving method provided by the present application can effectively reduce the data regularity. Improve the randomness of data, apply it to Polar code interleaving more effectively, and help to improve the compilation performance of Polar code.
  • the encoding strategy of the Polar code utilizes a noise-free channel to transmit useful information of the user, and the full-noise channel transmits the agreed information or does not transmit information.
  • the Polar code is also a linear block code whose encoding matrix is G N and the encoding process is among them Is a binary line vector of length N (ie code length); G N is an N ⁇ N matrix, and Defined as the Kronecker product of log 2 N matrices F 2 . Above matrix
  • G N (A) is the set of G N The sub-matrices obtained from those rows corresponding to the index
  • G N (A C ) is the set of G N The sub-matrices obtained from those rows corresponding to the index.
  • the encoded output of the Polar code can be simplified to:
  • indicates the number of elements in the collection, and K is the size of the information block.
  • the construction process of the Polar code is a collection
  • the selection process determines the performance of the Polar code.
  • the construction process of the Polar code is generally: determining that there are N polarized channels in total according to the length N of the mother code, respectively corresponding to N rows of the coding matrix, calculating the reliability of the polarized channel, and the first K polarizations with higher reliability.
  • Channel index as a collection Element
  • the index corresponding to the remaining (NK) polarized channels as the index set of fixed bits Elements. set Determine the location of the information bits, the collection The position of the fixed bit is determined.
  • the communication system 100 includes a network device 110, and a terminal 112.
  • the network device 110 can also be connected to the core network.
  • Network device 101 can also communicate with IP network 200, such as the Internet, a private IP network, or other data network.
  • IP network 200 such as the Internet, a private IP network, or other data network.
  • Network devices provide services to terminals within coverage.
  • network device 110 provides wireless access to one or more terminals within range of network device 110.
  • Network devices may also be in communication with one another, for example, network device 110 may communicate with network device 120.
  • the embodiment of the present application simplifies the communication system 100 to include sending as shown in FIG. 1(b), for the network device 110 or the terminal 112 to transmit information or data.
  • the transmitting end 101 can be the network device 110, and the receiving end 102 is the terminal 112; or the transmitting end 101 is the terminal 112, and the receiving end 102 is the network device 110.
  • Network device 110 may be a device for communicating with a terminal device.
  • the network device may be a base station (Base Transceiver Station, BTS) in a GSM system or a CDMA system, or a base station (NodeB, NB) in a WCDMA system, or an evolved base station (Evolved Node B, eNB) in an LTE system. Or eNodeB) or network side devices in the future 5G network. Or the network device may also be a relay station, an access point, an in-vehicle device, or the like. In a Device to Device (D2D) communication system, the network device may also be a terminal functioning as a base station. The terminal may include various handheld devices having wireless communication functions, in-vehicle devices, wearable devices, computing devices, or other processing devices connected to the wireless modem, and various forms of user equipment (UE), mobile stations (mobile) Station, MS), etc.
  • BTS Base Transceiver Station
  • NodeB NodeB
  • eNB evolved base station
  • eNodeB evolved base station
  • the encoding process involved in the present application is roughly: performing Polar code encoding on the encoded information, performing rate matching on the encoded code encoded by the Polar code according to the target code length M, interleaving the bit sequence after the rate matching, and outputting the interleaved bit sequence. .
  • Embodiments of the present application relate to the step of interleaving.
  • the bit sequence to be interleaved may be the bit sequence after rate matching in the above process.
  • the bit sequence to be interleaved may also be the coded bit before rate matching.
  • the sequence may be an example of a bit sequence after rate matching in the above process.
  • the length of the bit sequence after rate matching is the target code length M, and M is an integer power of 2.
  • the interleaver is used in the scheme designed by the embodiment of the present application. To facilitate the understanding of the subsequent content, the interleaver is briefly introduced below.
  • the bit to be interleaved by the interleaver is called the bit to be interleaved.
  • the bit to be interleaved After the bit to be interleaved is written into the interleaver, it is read by the interleaver, and the bit read is changed from the bit order of the write, thereby interleaving.
  • the method of writing and reading the interleaver can adopt the travel list, the column out, the list, the zigzag read of the marching column, the glyph read of the column into the column, etc., and the writing and reading modes are The prior art is not described here.
  • the number of rows When writing, you can first fix the number of rows, calculate the number of columns, that is, the number of bits included in each row; or you can fix the number of columns first, and calculate the number of rows, that is, the number of bits included in each column. If the fixed number of rows is i, the number of columns is the total length of the bits interleaved by the row and the i is rounded up; if the number of columns is fixed, the number of rows is the total length of the bits interleaved by the row and column divided by j. When writing in rows, the bits to be interleaved are input to the interleaver line by line. The number of bits input per line is the number of columns calculated by the above method.
  • the interleave depth refers to the size of the number of rows. If the number of columns is fixed first, the interleave depth refers to the number of columns. Taking the travel list as an example, as shown in FIG.
  • an m*n-dimensional matrix is generated according to the bits to be interleaved, and the bits to be interleaved are arranged according to the matrix of the matrix, and the data input order is [X 11 , X 12 , X 13 ,...,X 1m ,X 21 ,X 22 ,X 23 ,...,X 2m ,...,...,X n1 ,X n2 ,...,X nm ], the data output order is [X 11 , X 21 , X 31 , ..., X n1 , X 12 , X 22 , X 32 , ..., X n2 , ..., X 1m , X 2m , X 3m , X nm ].
  • X 11 is the bit of the first column of the first row in the interleaver. If the number of rows is fixed first, the interleaving depth is m. If the number of columns is fixed first, the interleaving depth
  • the execution body of the interleaving method may be the sending end 101.
  • the specific flow of the interleaving method provided by the embodiment of the present application is as follows. .
  • Step 301 Obtain a bit sequence to be interleaved.
  • the bit sequence to be interleaved includes L sub-sequences.
  • the L sub-sequences are consecutive sub-sequences divided by bit sequences to be interleaved, and any two sub-sequences do not intersect.
  • the L subsequences include S subsequence sets, and at least one subsequence is included in one subsequence set, but the number of subsequences included in at least one subsequence set is greater than one. Both L and S are positive integers greater than one. For convenience of explanation, it is assumed that any two subsequence groups included in the S subsequence group are respectively recorded as the first subsequence group and the second subsequence group.
  • the first subsequence group can be considered to include at least 2 subsequences
  • the second subsequence set includes at least 1 subsequence.
  • Step 302 Perform interleaving on the subsequences in the first subsequence group by using the first interleaving manner, and do not interleave the subsequences in the second subsequence group or interleave in the second interleaving manner.
  • some or all of the sub-sequence groups in the S sub-sequence groups perform inter-group interleaving.
  • the interleaving manner of intra-group interleaving may be, but is not limited to, performing inter-row interleaving using an interleaver.
  • the first interleaving manner and the second interleaving manner are different interleaving modes, and are intended to implement random discretization of each group of bits, thereby implementing random discretization of the bit sequence to be interleaved.
  • the first interleaving mode and the second interleaving mode can be understood as different methods of writing and reading the row and column interleaver, and it can also be understood that different interleaving depths are used when writing and reading the row and column interleaver by the same method. Or row or column interleaving with different numbers of rows or different columns.
  • the first interleaving mode and the second interleaving mode are both row and column interleaving performed by an interleaver
  • the first interleaving mode is recorded as the first row and column interleaving
  • the second interleaving mode is recorded as the second row and column interleaving
  • the first interleaving manner is performed.
  • the second interleaving method is a travel list. If the number of rows is fixed first, the number of rows fixed by the first interleaving mode and the second interleaving mode is different.
  • the first interleaving mode is fixed to 3 rows, and the second interleaving mode is fixed to 5 rows; if the number of columns is fixed first, The number of columns fixed by the first interleaving method and the second interleaving method is different.
  • the first interleaving method is fixed to three columns, and the second interleaving method is fixed to five columns.
  • Any two groups performing intra-group interleaving in the S sub-sequence groups adopt different interleaving depths, so that the interleaved bit sequences are more random discrete.
  • the intra-group interleaving of the sub-sequence group adopts the row-column interleaving method, and is easy to be processed in parallel in hardware implementation, and the addressing calculation is convenient.
  • the embodiment of the present application may also adopt more different processing manners, and perform inter-group interleaving for any one.
  • the inter-group interleaving manner can be, but is not limited to, the following methods.
  • Manner 2 At least one subsequence in the subsequence group is interleaved in the subsequence, wherein the bits in one subsequence are input to the interleaver for interleaving.
  • all the sub-sequences in the sub-sequence group are interlaced in the sub-sequence, and the inter-sub-sequences are arranged in order.
  • Manner 3 The positions of the sub-sequences in the sub-sequence group are interleaved, and then all the bits of the sub-sequence group are used as a whole to perform inter-row interleaving using the interleaver.
  • the positions of the sub-sequences in the sub-sequence group are interleaved, and at least one sub-sequence in the sub-sequence group is interleaved in the sub-sequence in the manner of the second method.
  • At least one subsequence in the subsequence group is first interleaved in the subsequence, and the positions of the interleaved subsequences are interleaved.
  • the row and column interleaving in the above manners 1 to 5 may be replaced with any other interleaving method.
  • the positions of the sub-sequence groups may be interleaved, that is, the position order of the sub-sequence groups is disturbed.
  • the position of each subsequence group is ranked as 1, 2, 3, 4, and 5.
  • the position of each subsequence group is ranked as 3, 5, 4, 2, 1.
  • the bit sequences to be interleaved may be grouped to obtain S sub-sequence groups, or the bit sequence to be interleaved may be input into the interleaver, one line. Or a column as a subsequence, output in the order of the grouped rows or in the order of the grouped columns to obtain S subsequence groups.
  • Embodiments of the present application may, but are not limited to, obtain S subsequence groups in the following manners.
  • the number of each subsequence is subjected to a modulo S operation
  • the modulo S operation is a modulo S
  • S is the number of groups of subsequence groups that need to be divided.
  • the numbers of the same operation result are grouped into one group.
  • the operation result of the modulo S of each subsequence number of the first subsequence group is the first operation result
  • the operation result of the modulo S of each subsequence number of the second subsequence group is the second operation result.
  • Mode 2 The sub-sequence numbers 1 to L are operated in bit reverse order to obtain a new numbered sequence, according to the determined number of groups S of the sub-sequence groups, according to or The operation determines the number m of sub-sequences in a group, determines a set of m numbers from the obtained new numbered sorting sequence, and determines the sub-sequence of each group according to the number of each group.
  • the number of subsequences of the last group may be less than or equal to m.
  • the numbered sequence of numbers 1 to L of the subsequences obtained by bit reverse order operation will include a value greater than L, and the bit reverse sequence operation obtains the sequence in order.
  • the rearrangement obtains a sequence of positions, and the flow of the above selection is continued in accordance with the sequence of positions.
  • Method 3 Select a number from 1 to L according to a fixed interval G, obtain a first group number, and remove the first group number in numbers 1 to L; similarly, select a fixed interval G from the eliminated number. Number, get the second set of numbers, and cull the second set of numbers; and so on, perform the similar operations described above until the last set of numbers is selected.
  • Method 4 The numbers 1 to L of the sub-sequences are operated according to the method of the method 3, and a new number sorting sequence is obtained according to the selected group numbers, and according to the determined group number S of the sub-sequence groups, according to or The operation determines the number m of sub-sequences in a group, determines a set of m numbers from the obtained new numbered sorting sequence, and determines the sub-sequence of each group according to the number of each group.
  • the number of subsequences of the last group may be less than or equal to m.
  • the numbered sequence of numbers 1 to L of the subsequences obtained by bit reverse order operation will include a value greater than L, and the bit reverse sequence operation obtains the sequence in order.
  • the rearrangement obtains a sequence of positions, and the flow of the above selection is continued in accordance with the sequence of positions.
  • Method 5 According to the number 1 to L of each subsequence, the minimum value, the maximum value, and the intermediate value are selected as the first group number, and the middle value is the maximum value of the number sorting sequence divided by 2, rounded up or rounded down, A group of numbers is eliminated in numbers 1 to L; similarly, the minimum, maximum, and intermediate values are selected from the number after the rejection, and the second group number is eliminated; and so on, the above is performed. A similar operation until the last set of numbers is selected.
  • Method 6 the sub-sequence numbers 1 to L are operated according to the method of the method 5, and a new number sorting sequence is obtained according to the selected group number, according to the determined group number S of the sub-sequence group, according to or The operation determines the number m of sub-sequences in a group, determines a set of m numbers from the obtained new numbered sorting sequence, and determines the sub-sequence of each group according to the number of each group.
  • the number of subsequences of the last group may be less than or equal to m.
  • the numbered sequence of numbers 1 to L of the subsequences obtained by bit reverse order operation will include a value greater than L, and the bit reverse sequence operation obtains the sequence in order.
  • the rearrangement obtains a sequence of positions, and the flow of the above selection is continued in accordance with the sequence of positions.
  • the bit sequence to be interleaved may be divided into L sub-sequences in order, or the bit sequence to be interleaved may be input to the interleaver to output L rows or L columns, one row. Or one column is a subsequence, and the L subsequences are grouped according to any one of the above modes 1 to 6, to obtain S subsequence groups.
  • the bit sequence to be interleaved is input to the interleaver, and the subsequence obtained by any one of the foregoing manners 1 to 6 is used to perform weighting on the row.
  • the row or column is rearranged and output sequentially, or the subsequence obtained in any of the above manners 1 to 6 is outputted row by row or column by column.
  • M is the length of the bit sequence to be interleaved
  • each set of 8 numbers obtains a set of data, and the subsequence components are obtained as [1, 17, 9, 25, 5, 21, 13,29], [3,19,11,27,7,23,15,31], [2,18,10,26,6,22,14,30], [4,20,12,28, 8,24,16,32].
  • the last group contains 4 sub-sequences, and the sub-sequence components are: [1,17,9,25,5,21,13], [29,3,19,11,27,7,23] , [15, 31, 2, 18, 10, 26, 6], [22, 14, 30, 4, 20, 12, 28], [8, 24, 16, 32].
  • the value 32 is operated in the above example, since 32 is a power of 2, 32 values can be easily obtained according to the bit reverse order. If the value does not satisfy the power of 2, the value of the sequence greater than L is generated according to the bit reverse order operation, and then reordered to obtain a new sequence, and the packet operates according to the new sequence.
  • the subsequence set is obtained in accordance with mode 2.
  • a subsequence set is obtained in accordance with mode 3.
  • the number is selected from 1 to 31 according to the interval 5, and the first group number [1 6 11 16 21 26 31] is obtained.
  • the number of the first group is removed, and the number is selected from the remaining number according to the interval 5.
  • the third group contains the number of columns [3 10 18 25]
  • the fourth group contains the number of columns [4 13 23] until the eighth group of data is [12 15 19 24 30].
  • the subsequence set is obtained in accordance with mode 4.
  • the number is selected from 1 to 31 according to the interval 5, and the number is selected from the remaining number according to the interval 5, and so on, and a new number sorting sequence can be obtained [1 6 11 16 21 26 31 2 8 14 20 27 3 10 18 25 4 13 23 5 17 29 7 22 9 28 12 15 19 24 30].
  • a subsequence set is obtained in accordance with mode 5.
  • the subsequence groups can be obtained as [1 11 6], [2 10 5], [3 9 7], [4 8], or the obtained subsequence groups are [1 11 6], [2 10 7], [ 3 9 5], [4 8].
  • the sub-sequence number L and the sub-sequence group number S may be determined by at least combining several factors. For example, one can be associated with a modulation order, and the number of subsequence groups S is a function of a modulation order; second, it can also be associated with an actual hardware implementation, where S is a power of 2 in hardware implementation. Easy to operate; third, it can also be associated with randomization as much as possible, S is as prime as possible.
  • L 31 is a prime number, which has an inherent advantage in random number generation; secondly, 31 is close to 32 rows fixed by the turbo code (ie Turbo code) outer interleaver in LTE.
  • turbo code ie Turbo code
  • L can choose any other value, for example, other values that are easy to implement in hardware, such as ⁇ 16, 32, 64 ⁇ , etc., and other prime numbers, such as ⁇ 7, 11, 13, 19, 23, 29, 37, 61 ⁇ and so on.
  • a bit sequence to be interleaved of length M is obtained, and a bit sequence to be interleaved is input to the interleaver.
  • the number of columns of the fixed interleaver is 31 columns, grouped according to the number of the column, and then inter-group interleaved; the number of rows of the fixed interleaver is 31 rows, grouped by the number of the row, and then grouped. Interwoven.
  • the number of columns of the fixed interleaver is 31, and the number of columns is 1 to 31, and of course, 0 to 30.
  • the bit in a column is a subsequence.
  • the number of rows is M divided by 31 and rounded up or down. The result is the number of bits in a column. If the last subsequence is insufficient, NULL can be filled.
  • the 31 columns are divided into S subsequence groups, and the value of S is assumed to be 5.
  • the choice of S value of 5 is: in high-order modulation, in association with the current modulation order, you can add 1 or subtract 1. If the modulation mode is 16QAM, the modulation order is 4, 64QAM, and the modulation order is 6.
  • S corresponds to [5 7] respectively.
  • the number of groups corresponds to [3 5], and the unified processing is considered here, and the number of subsequence groups is set to 5.
  • the number of subsequence groups of 5 can still be used when 256QAM, because 5 is not only related to the modulation order, but also a prime number.
  • the number of subsequence groups can be completely related to the modulation order, so that the corresponding groups under different modulation orders are different.
  • each of the numbers 1 to 31 is subjected to modulo 5 operation, and the remainders are 1, 2, 3, 4, and 0, respectively.
  • the numbers with the remainder of 1 are grouped into one, and the subsequence group S1 is obtained.
  • the subsequence included in S1 is [1 6 11 16 21 26 31]; the numbers with the remainder of 2 are grouped into one group, and the subsequence group S2 is obtained.
  • the subsequence included in S2 is [2 7 12 17 22 27]; the number with the remainder of 3 is grouped to obtain the subsequence group S3, and the subsequence included in S3 is [3 8 13 18 23 28]; The numbers with the remainder of 4 are grouped into one, and the subsequence group S4 is obtained.
  • the subsequence included in S4 is [4 9 14 19 24 29]; the numbers with the remainder of 0 are grouped into one group, and the subsequence group S5 is obtained.
  • the subsequence included in S5 is [5 10 15 20 25 30].
  • each subsequence group is then inter-group interleaved, and the method of interleaving in a specific group is as described above. It can be found that the number of subsequences in S1 is 7, and the number of subsequences in the remaining subsequence groups is 6. More generally, the number of subsequences to be grouped is L, the number of subsequence groups is S, and the number of subsequences in each group is at least Then the remaining number of sub-sequences Rg is L for S.
  • the number of remaining subsequences can be placed in the first to the Rg groups in order, or they can be placed in the even (odd) array first, or in the odd (even) array, or randomly placed in front according to a simple function.
  • the subsequence group Within the subsequence group.
  • inter-group interleaving uses row-array interleaving, and the write-reading manners listed in the travel list have at least two sets of interleaving depths different.
  • the interleaving depths of any two groups are different.
  • An example is as follows: As shown in FIG. 6, the subsequence group S1 is not interleaved, that is, sequentially written, and sequentially read; the subsequence group S2 adopts an interleaving depth of 3, fixed by 3 lines, and the number of columns is calculated according to the number of rows 3.
  • the read sequence is written according to the rules listed in the travel; the subsequence group S3 adopts an interleave depth of 5, fixed 5 rows, calculates the number of columns according to the number of rows 5, writes and reads according to the rules listed in the travel; the subsequence group S4 uses interleaving The depth is 7, fixed 7 rows, the number of columns is calculated according to the number of rows 7, and is written and read according to the rules listed in the travel; the sub-sequence group S5 has an interleaving depth of 9, fixed 9 rows, and the number of columns is calculated according to the number of rows 9, according to The rules listed for travel are written to read. Finally, after each sub-sequence group is inter-group interleaved, it may be output in order, or may be output after simple position interleaving. Only the sequential output is illustrated in FIG.
  • the number of sub-sequence groups S can take any other value, for example, the value [2, 3, 4, 6, 7] can be taken, and similarly, the pair can be respectively followed by [2, 3, 4, 6, 7 ] Perform modulo operations to obtain different subsequence sets.
  • the interleaving depth processing selected when each subsequence group is interleaved within the group may also be different.
  • the interleaving depth is more random, and the interleaving depth of the subsequence groups S1 to S5 may be ⁇ 1, 7 ⁇ or ⁇ 3, 11 ⁇ . Or ⁇ 5,10 ⁇ or ⁇ 7,11 ⁇ , etc.
  • the interleaving depth of the subsequence groups S1 to S5 may be ⁇ 1, 3, 5 ⁇ or ⁇ 3, 5, 7 ⁇ or ⁇ 3, 7, 11 ⁇ or ⁇ 5, 7, 11 ⁇ or ⁇ 2, 4, 6 ⁇ and so on.
  • the interleaving depth of the subsequence groups S1 to S5 may be ⁇ 1, 3, 5, 7 ⁇ or ⁇ 3, 5, 7, 9 ⁇ or ⁇ 3, 5, 7, 11 ⁇ or ⁇ 5, 7,11,13 ⁇ or ⁇ 2,4,6,8 ⁇ or ⁇ 2,5,8,11 ⁇ , etc.
  • the interleaving depth of the subsequence groups S1 to S5 may be ⁇ 1, 3, 5, 7, 9, 11 ⁇ or ⁇ 1, 3, 5, 1, 3, 5 ⁇ or ⁇ 5, 7, 9,5,7,9 ⁇ or ⁇ 3,3,5,5,7,7 ⁇ or ⁇ 3,7,11,3,7,11 ⁇ or ⁇ 2,4,6,8,10,12 ⁇ Or ⁇ 2,4,6,6,4,2 ⁇ or ⁇ 5,7,9,9,7,5 ⁇ or ⁇ 11,9,7 7,9,11 ⁇ , etc.
  • the interleaving depth of the subsequence groups S1 to S5 may be ⁇ 1, 3, 5, 7, 9, 11, 13 ⁇ or ⁇ 1, 3, 5, 7, 7, 5, 3, 1 ⁇ Or ⁇ 5,7,9,11,9,7,5 ⁇ or ⁇ 3,3,5,5,7,7,9 ⁇ or ⁇ 3,3,7,7,11,11,1 ⁇ or ⁇ 2,4,6,8,10,12,14 ⁇ or ⁇ 2,4,6,8,6,4,2 ⁇ or ⁇ 5,7,9,11,9,7,5 ⁇ or ⁇ 11, 9,7,5,7,9,11 ⁇ and so on.
  • all the bits in the group may be interleaved into the interleaver, or each sub-sequence in the group may be interleaved in the sub-sequence, and the bits in the sub-sequence are interleaved into the interleaver for interleaving.
  • the output bits are then combined into an interleaved subsequence set. For example, all the bits of the subsequence [1 6 11 16 21 26 31] included in S1 enter the interleaver for interleaving, or the first column is interleaved as the bit to be interleaved into the interleaver, and the sixth column is entered as the bit to be interleaved.
  • the interleaver performs interleaving, and similarly, the eleventh column, the sixteenth column, the twenty-first column, the twenty-sixth column, and the thirty-seventh column are interleaved.
  • the ordering position of the subsequence [1 6 11 16 21 26 31] is interleaved before interleaving, and the interleaving method is not limited.
  • the interleaved subsequence is [11 26 1 6 31 16 21].
  • the number of rows of the fixed interleaver is 31 rows, the number of rows is numbered from 1 to 31, and the bits in one row are a subsequence, and the number of columns is the number of bits to be interleaved divided by 31, rounded up or down. Integrity, the result is the number of bits in a row, if the last subsequence is insufficient, it can be filled with NULL.
  • the 31 lines are divided into S subsequence groups, and the value of S is assumed to be 5.
  • the subsequence group is obtained by way of example 1. It can be understood that the subsequence group can be obtained by any of the methods mentioned above, and the interleaving method in the subsequence group described later in the example. The same can be applied.
  • the number of columns is numbered from 1 to 31
  • the bits in one column are one subsequence
  • the number of rows is rounded up by the number of bits to be interleaved divided by 31.
  • the 31 columns of data are divided into S subsequence groups, and the value of S is assumed to be 5.
  • the data in each group is exchanged according to the rows, and the row exchange manners performed by each group may be different. For example, the rows of the first group of data are not exchanged, and are directly read in the order of columns or rows, and the rows of the second group of data are followed.
  • the interval 3 is exchanged, the rows of the third group of data are exchanged according to the interval 5, the rows of the fourth group of data are exchanged according to the interval 7, and the rows of the fifth group of data are exchanged according to the interval 11, and the size of the interleaver is assumed.
  • the interval is T
  • the row order after the row exchange of each group can be expressed as [1:T:R 2:T:R 3:T:R ... T:T:R]
  • each group interval may not be fixed.
  • the main principle is that the row exchange manners of the previous groups may not be exactly the same.
  • the row exchange interval of the above five groups of data may be [1 3 5 7 9] or the like, which is not limited.
  • each group is not limited to the above form, and may be exchanged in other orders, for example, the first group of data is not exchanged, the second group is used for interval switching, the third group is switched by bit reverse order, and the fourth group is parity. Type exchange, the fifth group uses reverse order exchange and so on.
  • the number of rows is numbered from 1 to 31
  • the bits in one row are a subsequence
  • the number of columns is rounded up by the number of bits to be interleaved divided by 31.
  • the 31 rows of data are divided into S subsequence groups, and the value of S is assumed to be 5.
  • the data in each group is exchanged according to the columns, and the column exchange manners performed by each group may be different.
  • the columns of the first group of data are not exchanged, and are directly read out in column or row order, and the columns of the second group of data are The interval 3 is exchanged, the columns of the third group of data are exchanged according to the interval 5, the columns of the fourth group of data are exchanged according to the interval 7, and the columns of the fifth group of data are exchanged according to the interval 11, and the size of the interleaver is assumed.
  • the interval is T
  • the column order after the column exchange of each group can be expressed as [1:T:C 2:T:C 3:T:C ... T:T:C]
  • each group interval may not be fixed.
  • the main principle is that the row exchange manners of the previous groups may not be exactly the same.
  • the column exchange interval of the above five groups of data may be [1 3 5 7 9] or the like, which is not limited.
  • the column exchange order of each group is not limited to the above form, and may be exchanged in other orders, for example, the first group of data is not exchanged, the second group is used for interval switching, the third group is switched by bit reverse order, and the fourth group is parity.
  • the fifth group of the type exchange uses reverse order exchange and the like.
  • the C column data is divided into S subsequence groups, and the value of S is assumed to be 5.
  • the data in each group is exchanged according to the rows, and the row exchange manners performed by each group may be different. For example, the rows of the first group of data are not exchanged, and are directly read in the row or column order, and the rows of the second group of data are followed.
  • the interval 3 is exchanged, the rows of the third group of data are exchanged according to the interval 5, the rows of the fourth group of data are exchanged according to the interval 7, and the rows of the fifth group of data are exchanged according to the interval 11, and the size of the interleaver is assumed.
  • the interval is T
  • the row order after the row exchange of each group can be expressed as [1:T:L 2:T:L 3:T:L ... T:T:L]
  • each group interval may not be fixed.
  • the main principle is that the row exchange manners of the previous groups may not be exactly the same.
  • the row exchange interval of the above five groups of data may be [1 3 5 7 9] or the like, which is not limited.
  • each group is not limited to the above form, and may be exchanged in other orders, for example, the first group of data is not exchanged, the second group is used for interval switching, the third group is switched by bit reverse order, and the fourth group is parity.
  • the fifth group of the type exchange uses reverse order exchange and the like.
  • the R row data is divided into S subsequence groups, and the value of S is assumed to be 5.
  • the data in each group is exchanged according to the columns, and the column exchange manners performed by each group may be different.
  • the columns of the first group of data are not exchanged, and are directly read out in column or row order, and the columns of the second group of data are The interval 3 is exchanged, the columns of the third group of data are exchanged according to the interval 5, the columns of the fourth group of data are exchanged according to the interval 7, and the columns of the fifth group of data are exchanged according to the interval 11, and the size of the interleaver is assumed.
  • the interval is T
  • the row order of each group of rows can be expressed as [1: T: L 2: T: L 3: T: L ... T: T: L]
  • each group interval may not be fixed.
  • the main principle is that the column exchange manners of the previous groups may not be identical.
  • the column exchange interval of the above five groups of data may be [1 3 5 7 9] or the like, which is not limited.
  • the column exchange order of each group is not limited to the above form, and may be exchanged in other orders, for example, the first group of data is not exchanged, the second group is used for interval switching, the third group is switched by bit reverse order, and the fourth group is parity.
  • the fifth group of the type exchange uses reverse order exchange and the like.
  • the number of rows is numbered from 1 to 31
  • the bits in one row are a subsequence
  • the number of columns is the number of bits to be interleaved divided by 31.
  • the remaining bits can be placed in multiple subsequences in a scattered manner, or placed in a subsequence in a centralized manner.
  • the grouping manner can adopt the same manner as the foregoing, and details are not described herein again.
  • the embodiments of the present application can be combined with the Polar code by obtaining sub-sequence groups and using different interleaving modes in the sub-sequence groups, so that the interleaving effect is better and the performance of the Polar code is improved.
  • the decoding process is: performing deinterleaving and de-rate matching on the received sequence to be decoded, and performing Polar code decoding on the obtained sequence.
  • the decoding end may obtain a deinterleaving method corresponding to the encoding end interleaving method according to the encoding end interleaving method, and perform a deinterleaving operation according to the obtained deinterleaving method.
  • the deinterleaving method is determined according to an interleaving method, and the deinterleaving method is an inverse operation of the interleaving method.
  • the first sequence obtains the second sequence after performing the interleaving operation by the interleaving method, and the first sequence can be obtained by the de-interleaving method determined according to the interleaving method for the second sequence. If the interleaving method uses the travel list for interleaving, the deinterleaving method performs deinterleaving using columns.
  • the interleaving method of the encoding end is as described above, and details are not described herein again.
  • the interleaved pattern is also obtained.
  • the receiving end needs to know the interleaving pattern (or mapping relationship) or other equivalent representation method, and the deinterleaving operation (that is, the inverse operation of the interleaving method) is to press the bits to be deinterleaved.
  • the row is written as a vector of length A, and the a_interleave bits b a_interleave are deinterleaved (or inversely mapped) to the position of the a_original bits as b a_original according to an interleaving pattern or other equivalent representation method.
  • the method of writing the vector of length A by the two ends of the transmitting and receiving is also applicable. In fact, it is only necessary to send and receive the two ends or to generate a vector of length A according to the same method according to the protocol.
  • the receiving end needs to know the interleaving pattern (or mapping relationship) or other equivalent representation method, and the deinterleaving operation (that is, the inverse operation of the interleaving method) is to bit the bits to be deinterleaved according to
  • the same rule as the sender is written as a matrix of B rows and C columns, and the bit b a_interleave of the a_j_interleave column of the a_i_interleave row is deinterleaved (or inversely mapped) to the a_i_original row a_j_original according to an interleaving pattern or other equivalent representation method.
  • the position of the column can be used as b a_original .
  • the sending end performs the traveling list operation
  • the receiving end performs the column out operation
  • the sending end performs the column out operation
  • the receiving end performs the traveling list operation
  • the transmitting end performs the line out operation
  • the receiving end performs the line out operation.
  • the transmitting end performs the listing operation
  • an embodiment of the present application further provides an interleaving apparatus 700 for performing the interleaving method shown in FIG.
  • the interleaving apparatus 700 includes: an input interface circuit 701 for acquiring a bit sequence to be interleaved; logic
  • the circuit 702 is configured to perform the interleaving method shown in FIG. 3 above.
  • the output interface circuit 703 is configured to output the interleaved bit sequence.
  • the interleaving device 700 may be a chip or an integrated circuit when implemented.
  • the interleaving apparatus 800 includes: a memory 801 for storing a program; and a processor 802 for executing the memory 801.
  • the stored program when executed, causes the interleaving device 800 to implement the interleaving method provided by the embodiment of FIG. 3 described above.
  • the foregoing memory 801 may be a physically separate unit or may be integrated with the processor 802.
  • the interleaving apparatus 800 may also include only the processor 802.
  • the memory 801 for storing programs is located outside the interleaving device 800, and the processor 802 is connected to the memory 801 through circuits/wires for reading and executing programs stored in the memory 801.
  • the processor 802 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.
  • CPU central processing unit
  • NP network processor
  • Processor 802 can also further include a hardware chip.
  • the hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • the memory 801 may include a volatile memory such as a random-access memory (RAM); the memory 801 may also include a non-volatile memory such as a flash memory (flash) Memory), hard disk drive (HDD) or solid state drive (SSD); the memory 801 may also include a combination of the above types of memories.
  • RAM random-access memory
  • non-volatile memory such as a flash memory (flash) Memory), hard disk drive (HDD) or solid state drive (SSD); the memory 801 may also include a combination of the above types of memories.
  • an embodiment of the present application further provides an interleaving apparatus 900 for performing the interleaving method shown in FIG.
  • the interlacing device 900 includes:
  • the obtaining unit 901 is configured to acquire a bit sequence to be interleaved.
  • the bit sequence to be interleaved includes L sub-sequences, and the L sub-sequences include at least a first sub-sequence set and a second sub-sequence set, the first sub-sequence set includes at least two sub-sequences, and the second sub-sequence set includes at least one sub-sequence , L is a positive integer greater than one.
  • the interleaving unit 902 is configured to perform interleaving by using the first interleaving manner on the subsequences in the first subsequence group acquired by the obtaining unit 901, and not interleaving the subsequences in the second subsequence group or interleaving by using the second interleaving manner.
  • the results of the modulo operations performed by the respective numbers of the subsequences in the first subsequence group according to the set values are all the first operation results; the respective numbers of the subsequences in the second subsequence group are respectively set according to the setting
  • the result of the modulo operation is the second operation result.
  • the first interleaving manner is the first row and column interleaving
  • the second interleaving manner is the second row and column interleaving
  • the number of rows of the first row and column interleaving and the second row and column interleaving is different or the number of columns is different.
  • the interleaving unit 902 is configured to: input all the bits in the first sub-sequence group into the interleaver bit-by-bit for inter-row interleaving; or perform partial or all sub-sequences in the first sub-sequence group in the sub-sequence Rows and columns are interwoven.
  • the interleaving unit 902 is configured to perform interleaving processing on locations of the respective sub-sequences in the first sub-sequence group;
  • All the bits in the first sub-sequence group are input to the row-column interleaver for row-column interleaving; or each sub-sequence in the first sub-sequence group is interleaved in the sub-sequence.
  • the interleaving unit 902 is further configured to: after the acquiring unit acquires the bit sequence to be interleaved, perform interleaving on the subsequence in the first subsequence group by using a first interleaving manner, and subsequencing in the second subsequence group.
  • the interleaving unit 902 is further configured to: after the acquiring unit 901 obtains the bit sequence to be interleaved, interleave the subsequence in the first subsequence group by using a first interleaving manner, and the second subsequence Before the subsequences in the group are not interleaved or interleaved in the second interleaving manner, the L subsequences are grouped to obtain a first subsequence group and a second subsequence group.
  • the value of L is 31.
  • the interleaving unit 902 is further configured to: perform interleaving processing on locations of the first subsequence group and the second subsequence group.
  • the embodiment of the present application further provides a de-interleaving apparatus 1000, where the de-interleaving apparatus 1000 can be used to perform the de-interleaving method provided by the embodiment of the present application.
  • the de-interlacing device 1000 includes:
  • An obtaining unit 1001 configured to acquire a bit sequence to be deinterleaved
  • the deinterleaving unit 1002 is configured to perform a deinterleaving operation on the bit sequence to be deinterleaved according to a deinterleaving method, where the deinterleaving method is determined according to an interleaving method, and the deinterleaving method is an inverse operation of the interleaving method.
  • the interleaving method includes: acquiring a bit sequence to be interleaved, the bit sequence to be interleaved includes L sub-sequences, the L sub-sequences including at least a first sub-sequence group and a second sub-sequence group, the first The subsequence group includes at least two subsequences, the second subsequence group includes at least one subsequence, L is a positive integer greater than 1, and the subsequences in the first subsequence group are interleaved by using a first interleaving manner.
  • the subsequences in the second subsequence group are not interleaved or interleaved in a second interleaving manner.
  • the result of performing the modulo operation on each of the sub-sequences in the first sub-sequence group according to the set value is a first operation result
  • the results of the modulo operations of the respective numbers of the subsequences in the second subsequence group according to the set values are all the second operation results.
  • the first interleaving manner is a first row and column interleaving
  • the second interleaving manner is a second row and column interleaving
  • the first row and column interleaving and the second row and column interleaving have different numbers of rows or different column numbers.
  • the sub-sequences in the first sub-sequence group are interleaved by using a first interleaving manner, including:
  • All the bits in the first subsequence group are input to the interleaver bit by bit for interlacing;
  • Some or all of the subsequences in the first subsequence set are interlaced in a subsequence.
  • the interleaving method further includes:
  • the interleaving method further comprises: grouping the L subsequences to obtain the first subsequence group and the second subsequence group.
  • the embodiment of the present application further provides a de-interleaving device 1100, which is used to perform the above-described de-interleaving method.
  • a de-interleaving device 1100 which is used to perform the above-described de-interleaving method.
  • Some or all of the foregoing de-interleaving methods may be implemented by hardware or by software.
  • the de-interleaving apparatus 1100 includes: an input interface circuit 701, configured to acquire a bit sequence to be deinterleaved; 702, configured to perform the foregoing deinterleaving method, and output interface circuit 703, configured to output the deinterleaved sequence.
  • the de-interleaving device 1100 may be a chip or an integrated circuit when implemented.
  • the deinterleaving apparatus 1200 includes: a memory 1201 for storing a program; and a processor 1202 for executing the memory.
  • the stored program 1201 when the program is executed, causes the deinterleaver 1200 to implement the deinterleaving method provided by the above embodiments.
  • the foregoing memory 1201 may be a physically separate unit or may be integrated with the processor 1202.
  • the de-interleaving apparatus 1200 may also include only the processor 1202.
  • the memory 1201 for storing programs is located outside the deinterleaver 1200, and the processor 1202 is connected to the memory 1201 through circuits/wires for reading and executing programs stored in the memory 1201.
  • the processor 1202 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.
  • CPU central processing unit
  • NP network processor
  • the processor 1202 may further include a hardware chip.
  • the hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • the memory 1201 may include a volatile memory such as a random-access memory (RAM); the memory 1201 may also include a non-volatile memory such as a flash memory (flash) Memory), hard disk drive (HDD) or solid-state drive (SSD); the memory 1201 may also include a combination of the above types of memories.
  • RAM random-access memory
  • non-volatile memory such as a flash memory (flash) Memory), hard disk drive (HDD) or solid-state drive (SSD); the memory 1201 may also include a combination of the above types of memories.
  • the embodiment of the present application further provides a network device.
  • the foregoing interleaving device and/or deinterleaving device may be installed in the network device 110.
  • the network device 110 may further include a transceiver 1302.
  • the interleaved bit sequence is sent to the terminal 112 through the transceiver 1302 after subsequent changes or processing, or the transceiver 1302 is further used.
  • the information/data from the terminal 112 is received, and the information/data is converted into a sequence to be deinterleaved through a series of processes, and processed by the deinterleaving device to obtain a deinterleaved sequence.
  • Network device 110 may also include a network interface 1304 for communicating with other network devices.
  • the terminal 112 may further include a transceiver 1312.
  • the interleaved bit sequence is sent to the network device 110 through the transceiver 1312 after subsequent changes or processing, or the transceiver 1312 is further used.
  • the information/data from the network device 110 is received, and the information/data is converted into a sequence to be deinterleaved through a series of processes, and processed by the deinterleaving device to obtain a deinterleaved sequence.
  • the terminal 112 may further include an input/output interface 1314 for receiving information input by the user.
  • the information needs to be processed by the interleaver and then sent to the network device 110 through the transceiver 1312.
  • the deinterleaved data of the deinterleaver can also be presented to the user through the input and output interface 1314 after subsequent processing.
  • the embodiment of the present application further provides a computer storage medium storing a computer program, the computer program comprising the interleaving method shown in FIG. 3 and the deinterleaving method provided in the foregoing embodiment.
  • the embodiment of the present application further provides a Polar code encoding apparatus, including any of the above-mentioned interleaving apparatuses of FIGS. 7 to 9 and any deinterleaving apparatus of FIGS. 10 to 12.
  • the embodiment of the present application further provides a computer program product comprising instructions, which when executed on a computer, causes the computer to perform the interleaving method shown in FIG. 3 and the deinterleaving method provided by the above embodiment.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本申请涉及通信技术领域，公开了一种交织方法、解交织方法及装置，用以提高Polar码交织的随机性。该方法为：获取待交织的比特序列，所述待交织的比特序列包括L个子序列，所述L个子序列包括S个子序列组，S个子序列组中至少包括第一子序列组和第二子序列组，所述第一子序列组至少包括2个子序列，所述第二子序列组至少包括1个子序列，L为大于1的正整数，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织。

Description

一种交织方法及装置 技术领域
本申请实施例涉及通信技术领域，尤其涉及一种交织方法及装置。
背景技术
无线通信的快速演进预示着未来第五代(5th generation，5G)通信系统将呈现出一些新的特点，最典型的三个通信场景包括增强型移动互联网(enhance mobile broadband，eMBB)、海量机器连接通信(massive machine type communication，mMTC)和高可靠低延迟通信(ultra reliable low latency communication，URLLC)，这些通信场景的需求将对现有长期演进(long term evolution，LTE)技术提出新的挑战。信道编码作为最基本的无线接入技术，是满足5G通信需求的重要研究对象之一。目前，5G标准的制定已经如火如荼的展开，极化码(Polar Codes)也被选作控制信道编码方式。极化码也可以称为Polar码，是第一种、也是已知的唯一一种能够被严格证明“达到”信道容量的信道编码方法。在不同码长下，尤其对于有限码，Polar码的性能远优于Turbo码和低密度奇偶校验码(low density parity check，LDPC)码。另外，Polar码在编译码方面具有较低的计算复杂度。这些优点让Polar码在5G中具有很大的发展和应用前景。
为了进一步提高抗干扰性能，一些信道编码加入了交织模块。在许多同时出现随机错误和突发错误的复合信道上，如短波、对流层散射等信道中，往往发生一个错误时，波及后面一串数据，导致突发误码超过纠错码的纠错能力，使纠错能力下降。如果首先把突发错误离散成随机错误，然后再去纠随机错误，则系统的抗干扰性能将进一步得到提高。实际应用中，在发送端纠错编码器后接数字交织单元，接收端解调后解交织，通过交织解交织电路的作用，将突然错误信道改造成独立的随机错误信道，将突发错误展开，实现错误离散化，使突发错误散布在纠错编码器纠错范围之内，以提高信道纠错能力。
目前Polar码的交织设计的效果不够理想，较随机交织的性能相差很大。
发明内容
本申请实施例提供一种交织方法及装置，用以提高Polar码交织的随机性。
第一方面，提供一种交织方法，通过将待交织的比特序列进行一次交织或者分组，使得同一组内的比特在该待交织的比特序列上覆盖的范围较大，再将组内的比特进行交织，这样能够有助于避免组内比特交织的局限性；另外，不同组的组内交织采用不同的交织方式，例如，若采用行列交织的方式，在固定行的情况下，不同组的组内交织采用不同的行数，在固定列的情况下，不同组的组内交织采用不同的列数，这样使得交织后的序列更具有随机性。通过实验仿真发现，对于Polar码来说，对待交织的比特序列进行交织操作达到的效果越随机化，则Polar码的性能越好，本申请提供的这种交织方式的能够有效降低数据规律性，提高数据的随机性，将其应用于Polar码交织更具有效性，更有助于改善Polar码的编译性能。
在一个可能的设计中，获取待交织的比特序列，所述待交织的比特序列包括L个子序列，所述L个子序列包括S个子序列组，S个子序列组中至少包括第一子序列组和第二子序列组，所述第一子序列组至少包括2个子序列，所述第二子序列组至少包括1个子序列，L为大于1的正整数，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织。通过不同的组内交织方式，能够使得交织后的数据更加离散随机化，更加有助于改善Polar的性能。
在一个可能的设计中，所述第一子序列组中的子序列的各个编号分别按照设定值进行取模运算的结果均为第一运算结果；所述第二子序列组中的子序列的各个编号分别按照所述设定值进行取模运算的结果均为第二运算结果。第一运算结果与第二运算结果不同。例如，按照各个编号除以设定值获得余数，将余数相同的分为一组。
在一个可能的设计中，所述第一交织方式为第一行列交织，所述第二交织方式为第二行列交织，所述第一行列交织和所述第二行列交织的行数不同或列数不同。也就是，第一子序列组和第二子序列采用不同交织深度的交织方式。这样，在硬件实现上易于并行处理，寻址计算较为方便，交织后的比特序列更具有随机离散性。
在一个可能的设计中，对所述第一子序列组中的子序列采用第一交织方式进行交织，可以通过以下方式实现：将所述第一子序列组中的所有比特逐比特输入交织器进行行列交织；或者，将所述第一子序列组中的部分或全部子序列分别在子序列内进行行列交织。
在一个可能的设计中，对所述第二子序列组中的子序列采用第二交织方式进行交织，可以通过以下方式实现：将所述第二子序列组中的所有比特逐比特输入交织器进行行列交织；或者，将所述第二子序列组中的部分或全部子序列分别在子序列内进行行列交织。
在一个可能的设计中，对所述第一子序列组中的子序列采用第一交织方式进行交织，可以通过以下方式实现：将所述第一子序列组中的各个子序列的位置进行交织处理，将所述第一子序列组中的所有比特输入行列交织器进行行列交织，或者，将所述第一子序列组中的各个子序列分别在子序列内进行行列交织。
在一个可能的设计中，对所述第二子序列组中的子序列采用第二交织方式进行交织，可以通过以下方式实现：将所述第二子序列组中的各个子序列的位置进行交织处理，将所述第二子序列组中的所有比特输入行列交织器进行行列交织，或者，将所述第二子序列组中的各个子序列分别在子序列内进行行列交织。
在一个可能的设计中，在所述获取待交织的比特序列之后，在对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，将所述待交织的比特序列输入i行j列的交织器，若i＝L，一行中的比特组成一个所述子序列，则逐行读取所述第一子序列组中的子序列，以及逐行读取所述第二子序列组中的子序列；或者，若j＝L，一列中的比特组成一个所述子序列，则逐列读取所述第一子序列组中的子序列，以及逐列读取所述第二子序列组中的子序列。
在一个可能的设计中，若已知i，则
Figure PCTCN2018097782-appb-000001
所述M为所述待交织的比特序列的长度；若已知j，则
Figure PCTCN2018097782-appb-000002
所述M为所述待交织的比特序列的长度。
在一个可能的设计中，所述获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，将所述L个子序列进行分组，以获得所述第一子序列组和所述第二 子序列组。
在一个可能的设计中，可以通过以下方式获得S个子序列组：将各个子序列的编号分别进行模S运算，模S运算即对S取模，S即确定的需要分成的子序列组的组数。按照运算结果，将相同运算结果的的编号分为一组。例如，第一子序列组的各个子序列编号进行模S的运算结果均为第一运算结果，第二子序列组的各个子序列编号进行模S的运算结果均为第二运算结果。
在一个可能的设计中，可以通过以下方式获得S个子序列组：对子序列的编号1～L采用比特逆序操作，获得一个新的编号排序序列，根据确定的子序列组的组数S，按照
Figure PCTCN2018097782-appb-000003
或者
Figure PCTCN2018097782-appb-000004
运算，确定一组内的子序列数m，从获得的新的编号排序序列中按照顺序每m个编号确定为一组，按照每组的编号确定每组的子序列。其中，最后一组的子序列数可以小于或等于m。可选的，若L非2的整数次幂，则对子序列的编号1～L采用比特逆序操作获得的编号排序序列中会包括大于L的数值，将比特逆序操作获得序列按顺序重排获得位置序列，按照位置序列继续进行上述选组的流程。
在一个可能的设计中，可以通过以下方式获得S个子序列组：从1～L中按照固定间隔G选择编号，获得第一组编号，并将第一组编号在编号1～L中剔除；类似的，再从剔除后的编号中按照固定间隔G选择编号，获得第二组编号，并将第二组编号剔除；以此类推，执行上述类似的操作，直到选出最后一组编号。
在一个可能的设计中，可以通过以下方式获得S个子序列组：对子序列的编号1～L按照方式3的方法操作，根据选择的各组编号获得新的编号排序序列，根据确定的子序列组的组数S，按照
Figure PCTCN2018097782-appb-000005
或者
Figure PCTCN2018097782-appb-000006
运算，确定一组内的子序列数m，从获得的新的编号排序序列中按照顺序每m个编号确定为一组，按照每组的编号确定每组的子序列。其中，最后一组的子序列数可以小于或等于m。可选的，若L非2的整数次幂，则对子序列的编号1～L采用比特逆序操作获得的编号排序序列中会包括大于L的数值，将比特逆序操作获得序列按顺序重排获得位置序列，按照位置序列继续进行上述选组的流程。
在一个可能的设计中，可以通过以下方式获得S个子序列组：根据各个子序列的编号1～L，选择最小值、最大值和中间值为第一组编号，中间值为编号排序序列的最大值除2向上取整或向下取整，将第一组编号在编号1～L中剔除；类似的，继续从剔除后的编号中选择最小值、最大值和中间值为第二组编号，并将第二组编号剔除；以此类推，执行上述类似的操作，直到选出最后一组编号。
在一个可能的设计中，可以通过以下方式获得S个子序列组：对子序列的编号1～L按照方式5的方法操作，根据选择的各组编号获得新的编号排序序列，根据确定的子序列组的组数S，按照
Figure PCTCN2018097782-appb-000007
或者
Figure PCTCN2018097782-appb-000008
运算，确定一组内的子序列数m，从获得的新的编号排序序列中按照顺序每m个编号确定为一组，按照每组的编号确定每组的子序列。其中，最后一组的子序列数可以小于或等于m。可选的，若L非2的整数次幂，则对子序列的编号1～L采用比特逆序操作获得的编号排序序列中会包括大于L的数值，将比特逆序操作获得序列按顺序重排获得位置序列，按照位置序列继续进行上述选组的流程。
在一个可能的设计中，子序列数L和子序列组数S可以至少综合几种因素来确定。例如：其一、可以与调制阶数联系起来，子序列组数S是调制阶数的函数的形式；其二、也可以与实际硬件实现联系起来，在硬件实现中S为2的幂次相对容易操作；其三、也可以 与尽量随机化联系起来，S尽量为素数。
在一个可能的设计中，L取值为以下任一个：16，31，32，64，7，11，13,19，23,29,37,61。
在一个可能的设计中，将所述第一子序列组和所述第二子序列组的位置进行交织处理。
第二方面，提供一种交织装置，该装置具有实现上述第一方面和第一方面的任一种可能的设计中所述的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述交织装置包括：输入接口电路，用于获取待交织的比特序列；逻辑电路，用于执行上述第一方面和第一方面的任一种可能的设计中所述的行为；输出接口电路，用于输出交织后的比特序列。
可选的，所述交织装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述交织装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述交织装置可以实现如上述第一方面和第一方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述交织装置包括处理器。用于存储程序的存储器位于所述交织装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第三方面，提供了一种通信系统，该通信系统包括发送端和接收端，所述发送端可以执行如上述第一方面及其可能的设计所述的方法。
第四方面，提供了一种计算机存储介质，存储有计算机程序，该计算机程序包括用于执行第一方面和第一方面的任一可能设计中任一种所述的方法的指令。
第五方面，本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
附图说明
图1(a)和图1(b)为本申请实施例中应用的通信系统架构示意图；
图2为本申请实施例中行列交织器行进列出的示意图；
图3为本申请实施例中交织方法流程示意图；
图4为本申请实施例中子序列组获得方法示意图；
图5为本申请实施例中按照方式1的交织方发流程示意图；
图6为本申请实施例中组内交织的方法示意图；
图7为本申请实施例中交织装置结构示意图之一；
图8为本申请实施例中交织装置结构示意图之二；
图9为本申请实施例中交织装置结构示意图之三；
图10为本申请实施例中解交织装置结构示意图之一；
图11为本申请实施例中解交织装置结构示意图之二；
图12为本申请实施例中解交织装置结构示意图之三；
图13为本申请实施例中网络设备和终端的结构示意图。
具体实施方式
下面将结合附图，对本申请实施例进行详细描述。
本申请实施例提供一种交织方法及装置，通过将待交织的比特序列进行一次交织或者分组，使得同一组内的比特在该待交织的比特序列上覆盖的范围较大，再将组内的比特进行交织，这样能够有助于避免组内比特交织的局限性；另外，不同组的组内交织采用不同的交织方式，例如，若采用行列交织的方式，在固定行的情况下，不同组的组内交织采用不同的行数，在固定列的情况下，不同组的组内交织采用不同的列数，这样使得交织后的序列更具有随机性。通过实验仿真发现，对于Polar码来说，对待交织的比特序列进行交织操作达到的效果越随机化，则Polar码的性能越好，本申请提供的这种交织方式的能够有效降低数据规律性，提高数据的随机性，将其应用于Polar码交织更具有效性，更有助于改善Polar码的编译性能。
为方便对本申请实施例的理解，下面对Polar码作简单介绍。
Polar码的编码策略利用无噪信道传输用户有用的信息，全噪信道传输约定的信息或者不传信息。Polar码也是一种线性块码，其编码矩阵为G N，编码过程为
Figure PCTCN2018097782-appb-000009
其中
Figure PCTCN2018097782-appb-000010
是一个二进制的行矢量，长度为N(即码长)；G N是一个N×N的矩阵，且
Figure PCTCN2018097782-appb-000011
Figure PCTCN2018097782-appb-000012
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积。上述矩阵
Figure PCTCN2018097782-appb-000013
Polar码的编码过程中，
Figure PCTCN2018097782-appb-000014
中的一部分比特用来携带信息，称为信息比特集合，这些比特的索引的集合记作
Figure PCTCN2018097782-appb-000015
另外的一部分比特设置为接收端和发送端预先约定的固定值，称之为固定比特集合或冻结比特集合(frozen bits)，其索引的集合用
Figure PCTCN2018097782-appb-000016
的补集
Figure PCTCN2018097782-appb-000017
表示。Polar码的编码过程相当于：
Figure PCTCN2018097782-appb-000018
这里，G N(A)是G N中由集合
Figure PCTCN2018097782-appb-000019
中的索引对应的那些行得到的子矩阵，G N(A C)是G N中由集合
Figure PCTCN2018097782-appb-000020
中的索引对应的那些行得到的子矩阵。
Figure PCTCN2018097782-appb-000021
为
Figure PCTCN2018097782-appb-000022
中的信息比特集合，数量为K；
Figure PCTCN2018097782-appb-000023
为
Figure PCTCN2018097782-appb-000024
中的固定比特集合，其数量为(N-K)，是已知比特。这些固定比特通常被设置为0，但是只要接收端和发送端预先约定，固定比特可以被任意设置。从而，Polar码的编码输出可简化为：
Figure PCTCN2018097782-appb-000025
这里
Figure PCTCN2018097782-appb-000026
为
Figure PCTCN2018097782-appb-000027
中的信息比特集合，
Figure PCTCN2018097782-appb-000028
为长度K的行矢量，即
Figure PCTCN2018097782-appb-000029
|·|表示集合中元素的个数，K为信息块大小，
Figure PCTCN2018097782-appb-000030
是矩阵G N中由集合
Figure PCTCN2018097782-appb-000031
中的索引对应的那些行得到的子矩阵，
Figure PCTCN2018097782-appb-000032
是一个K×N的矩阵。
Polar码的构造过程即集合
Figure PCTCN2018097782-appb-000033
的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道，分别对应编码矩阵的N个行，计算极化信道可靠度，将可靠度较高的前K个极化信道的索引作为集合
Figure PCTCN2018097782-appb-000034
的元素，剩余(N-K)个极化信道对应的索引作为固定比特的索引集合
Figure PCTCN2018097782-appb-000035
的元素。集合
Figure PCTCN2018097782-appb-000036
决定了信息比特的位置，集合
Figure PCTCN2018097782-appb-000037
决定了固定比特的位置。
如图1(a)所示，通信系统100包括网设备110，和终端112。当无线通信网络100包 括核心网时，该网络设备110还可以与核心网相连。网络设备101还可以与IP网络200进行通信，例如，因特网(internet)，私有的IP网，或其它数据网等。网络设备为覆盖范围内的终端提供服务。例如，参见图1(a)所示，网络设备110为网络设备110覆盖范围内的一个或多个终端提供无线接入。除此之外，网络设备之间的覆盖范围可以存在重叠的区域，例如网络设备110和120。网络设备之间还可以可以互相通信，例如，网络设备110可以与网络设备120之间进行通信。
由于网络设备110或终端112发送信息或数据时均可以使本申请实施例中描述的交织方法，为方便描述，本申请实施例将通信系统100简化为如图1(b)所示的包括发送端101和接收端102的系统。发送端101可以为网络设备110，接收端102为终端112；或者，发送端101为终端112，接收端102为网络设备110。。网络设备110可以是用于与终端设备进行通信的设备。例如，可以是GSM系统或CDMA系统中的基站(Base Transceiver Station，BTS)，也可以是WCDMA系统中的基站(NodeB，NB)，还可以是LTE系统中的演进型基站(Evolved Node B，eNB或eNodeB)或未来5G网络中的网络侧设备等。或者该网络设备还可以是中继站、接入点、车载设备等。在终端对终端(Device to Device，D2D)通信系统中，该网络设备还可以是担任基站功能的终端。终端可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其他处理设备，以及各种形式的用户设备(user equipment，UE)，移动台(mobile station，MS)等。
本申请涉及的编码流程大致为：对待编码信息进行Polar码编码，将Polar码编码后的编码比特按照目标码长M进行速率匹配，将速率匹配之后的比特序列进行交织，输出交织后的比特序列。
本申请实施例涉及交织的步骤。当然，待交织的比特序列可以为上述流程中速率匹配之后的比特序列，另一种可能的实现方式中，待交织的比特序列也可以为速率匹配之前的编码比特，本申请以待交织的比特序列可以为上述流程中速率匹配之后的比特序列为例进行介绍，速率匹配之后的比特序列的长度即为目标码长M，M为2的整数次幂。
本申请实施例设计的方案中用到交织器，为方便后续内容的理解，下面对交织器进行简单的介绍。
将应用交织器进行交织的比特称为待交织比特，待交织比特写入交织器后，由交织器中读取出来，读取出来的比特较写入的比特顺序发生变化，以此起到交织的作用。写入和读取交织器的方法可以采用行进列出、列进行出、列进列出、行进列之字形读取、列进列之字形读取等等，几种写入和读取方式为现有技术，在此不再赘述。写入时，可以先固定行数，计算列数，即每行包括的比特数；也可以先固定列数，计算行数，即每列包括的比特数。若固定行数为i，则列数为进行行列交织的比特总长度除以i向上取整；若固定列数j，则行数为进行行列交织的比特总长度除以j向上取整。按行写入时，将待交织比特逐行输入交织器，每行输入的比特数为通过上述方法计算出来的列数，若最后一行不足则用null比特补齐；按列写入时，将待交织比特逐列输入交织器，每列输入的比特数为通过上述方法计算出来的行数，若最后一列不足，则用null比特补齐。如果填入了null比特，则需在交织后删除。另外，对本申请实施例应用的“交织深度”的概念进行解释，若先固定行数，交织深度是指行数的大小，若先固定列数，交织深度是指列数的大小。以行进列出为例，如图2所示，根据待交织比特产生m*n维矩阵，将待交织比特按照矩阵的行列进行行进列出的操作，数据输入顺序为[X 11，X 12,X 13,…,X 1m,X 21,X 22,X 23,…,X 2m,…,…,X n1,X n2,…,X nm]，数 据输出顺序为[X 11,X 21,X 31,…,X n1,X 12,X 22,X 32,…,X n2,…,X 1m,X 2m,X 3m,X nm]。其中，X 11为交织器中第一行第一列的比特。若先固定行数，则交织深度为m，若先固定列数，则交织深度为n。
基于图1(a)所示的通信系统架构，本申请实施例中，执行交织方法的执行主体可以为发送端101，如图3所示，本申请实施例提供的交织方法具体流程如下所述。
步骤301、获取待交织的比特序列。
该待交织的比特序列包括L个子序列，可选的，L个子序列为由待交织的比特序列分成的连续的子序列，任意两个子序列不相交。L个子序列包括S个子序列组，一个子序列组中包括至少一个子序列，但至少有一个子序列组中包括的子序列的数目大于1。L、S均为大于1的正整数。为方便说明，假设S个子序列组中包括的任意两个子序列组分别记为第一子序列组和第二子序列组。可以认为第一子序列组至少包括2个子序列，第二子序列组至少包括1个子序列。
步骤302、对第一子序列组中的子序列采用第一交织方式进行交织，对第二子序列组中的子序列不交织或者采用第二交织方式进行交织。
具体地，S个子序列组中的部分或全部子序列组进行组内的交织。组内交织的交织方式可以但不限于采用交织器进行行列交织。
上述第一交织方式和第二交织方式为不同的交织方式，意在实现各组比特的随机离散化，从而实现待交织的比特序列的随机离散化。第一交织方式和第二交织方式可以理解为不同的写入和读取行列交织器的方法，也可以理解为，在采用相同方法写入和读取行列交织器时，采用不同的交织深度，或者说采用不同行数或不同列数的行列交织。举例来说，若第一交织方式和第二交织方式均为通过交织器进行的行列交织，第一交织方式记为第一行列交织，第二交织方式记为第二行列交织，第一交织方式和第二交织方式均为行进列出。若先固定行数，则第一交织方式和第二交织方式所固定的行数不同，例如，第一交织方式固定为3行，第二交织方式固定为5行；若先固定列数，则第一交织方式和第二交织方式所固定的列数不同，例如，第一交织方式固定为3列，第二交织方式固定为5列。
S个子序列组中执行组内交织的任意两组采用的交织深度均不同，这样，交织后的比特序列更具有随机离散性。
本申请实施例中，子序列组的组内交织采用行列交织方式，在硬件实现上易于并行处理，寻址计算较为方便。
由于子序列组中可能包括两个或两个以上的子序列，针对这种情况，本申请实施例在实现组内交织时，还可以采用更多不同的处理方式，针对任一进行组内交织的子序列组来说，组内交织的方式可以但不限采用以下几种方式。
方式一：将子序列组的所有比特作为一个整体利用交织器进行行列交织。
方式二：将子序列组中的至少一个子序列分别在子序列内进行行列交织，其中，将一个子序列中的比特输入交织器进行交织。可选的，子序列组内的所有子序列均在子序列内进行行列交织，交织后的各个子序列再按顺序进行位置的排列。
方式三：将子序列组中的各个子序列的位置进行交织处理，再采用方式一的方式将子序列组的所有比特作为一个整体利用交织器进行行列交织。
方式四：将子序列组中的各个子序列的位置进行交织处理，再采用方式二的方式将子 序列组中的至少一个子序列分别在子序列内进行行列交织。
方式五：先将子序列组中的至少一个子序列分别在子序列内进行行列交织，再将交织后的各个子序列的位置进行交织处理。
上述方式一～方式五中的行列交织还可以替换为任意其他的交织方式。
可选的，在子序列组进行组内交织之前或者之后，还可以将子序列组的位置进行交织处理，即将子序列组的位置排序打乱。例如，S＝5，各个子序列组的编号为1～5，交织前，各个子序列组的位置排序为1、2、3、4、5，交织后，各个子子序列组的位置排序为3、5、4、2、1。
以上介绍了子序列组的组内交织方式，本申请实施例中，可以通过对待交织的比特序列进行分组，以获得S个子序列组，也可以通过将待交织的比特序列输入交织器中，一行或一列为一个子序列，按照分组的行顺序输出或按照分组后的列顺序输出，以获得S个子序列组。
下面具体介绍一下如何获得S个子序列组。本申请实施例可以但不限于采用以下几种方式获得S个子序列组。
假设L个子序列的编号为1、2、……、L，组成编号排序序列[1、2、……、L]。
方式1、将各个子序列的编号分别进行模S运算，模S运算即对S取模，S即确定的需要分成的子序列组的组数。按照运算结果，将相同运算结果的的编号分为一组。例如，第一子序列组的各个子序列编号进行模S的运算结果均为第一运算结果，第二子序列组的各个子序列编号进行模S的运算结果均为第二运算结果。
方式2、对子序列的编号1～L采用比特逆序操作，获得一个新的编号排序序列，根据确定的子序列组的组数S，按照
Figure PCTCN2018097782-appb-000038
或者
Figure PCTCN2018097782-appb-000039
运算，确定一组内的子序列数m，从获得的新的编号排序序列中按照顺序每m个编号确定为一组，按照每组的编号确定每组的子序列。其中，最后一组的子序列数可以小于或等于m。
一种可能的情况下，若L非2的整数次幂，则对子序列的编号1～L采用比特逆序操作获得的编号排序序列中会包括大于L的数值，将比特逆序操作获得序列按顺序重排获得位置序列，按照位置序列继续进行上述选组的流程。
方式3、从1～L中按照固定间隔G选择编号，获得第一组编号，并将第一组编号在编号1～L中剔除；类似的，再从剔除后的编号中按照固定间隔G选择编号，获得第二组编号，并将第二组编号剔除；以此类推，执行上述类似的操作，直到选出最后一组编号。
方式4、对子序列的编号1～L按照方式3的方法操作，根据选择的各组编号获得新的编号排序序列，根据确定的子序列组的组数S，按照
Figure PCTCN2018097782-appb-000040
或者
Figure PCTCN2018097782-appb-000041
运算，确定一组内的子序列数m，从获得的新的编号排序序列中按照顺序每m个编号确定为一组，按照每组的编号确定每组的子序列。其中，最后一组的子序列数可以小于或等于m。
一种可能的情况下，若L非2的整数次幂，则对子序列的编号1～L采用比特逆序操作获得的编号排序序列中会包括大于L的数值，将比特逆序操作获得序列按顺序重排获得位置序列，按照位置序列继续进行上述选组的流程。
方式5、根据各个子序列的编号1～L，选择最小值、最大值和中间值为第一组编号，中间值为编号排序序列的最大值除2向上取整或向下取整，将第一组编号在编号1～L中剔除；类似的，继续从剔除后的编号中选择最小值、最大值和中间值为第二组编号，并将第二组 编号剔除；以此类推，执行上述类似的操作，直到选出最后一组编号。
方式6、对子序列的编号1～L按照方式5的方法操作，根据选择的各组编号获得新的编号排序序列，根据确定的子序列组的组数S，按照
Figure PCTCN2018097782-appb-000042
或者
Figure PCTCN2018097782-appb-000043
运算，确定一组内的子序列数m，从获得的新的编号排序序列中按照顺序每m个编号确定为一组，按照每组的编号确定每组的子序列。其中，最后一组的子序列数可以小于或等于m。
一种可能的情况下，若L非2的整数次幂，则对子序列的编号1～L采用比特逆序操作获得的编号排序序列中会包括大于L的数值，将比特逆序操作获得序列按顺序重排获得位置序列，按照位置序列继续进行上述选组的流程。
可选的，实际应用中，获得待交织的比特序列后，可以按照顺序将待交织的比特序列分成L个子序列，也可以将待交织的比特序列输入交织器，输出L行或者L列，一行或一列为一个子序列，将L个子序列按照上述方式1～方式6中任一种方式进行分组，以获得S个子序列组。
可选的，实际应用中，也可以在获得待交织的比特序列后，将待交织的比特序列输入交织器，按照上述方式1～方式6中任一种方式获得的子序列排序对行进行重排或者对列进行重排后按序输出，或者，按照上述方式1～方式6中任一种方式获得的子序列排序逐行或者逐列输出。例如，M为待交织的比特序列的长度，将待交织的比特序列输入i行j列的交织器，其中，若令i＝L，一行中的比特组成一个子序列，列数
Figure PCTCN2018097782-appb-000044
逐行读取各个子序列组中的子序列，如逐行读取第一子序列组中的子序列，以及逐行读取第二子序列组中的子序列；或者，令j＝L，行数
Figure PCTCN2018097782-appb-000045
一列中的比特组成一个子序列，逐列读取各个子序列组中的子序列，如逐列读取第一子序列组中的子序列，以及逐列读取第二子序列组中的子序列。
下面对上述方式1～方式6的方法给出一些具体的举例。
假定L＝32，按照方式2获得子序列组。首先对[1～32]进行比特逆序操作，获得序列[1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31,2,18,10,26,6,22,14,30,4,20,12,28,8,24,16,32]。若S＝4，32/4＝8，则可以在序列中按序选择，每选择8个编号获得一组数据，得到子序列组分为为[1,17,9,25,5,21,13,29]、[3,19,11,27,7,23,15,31]、[2,18,10,26,6,22,14,30]、[4,20,12,28,8,24,16,32]。若S＝5，按照
Figure PCTCN2018097782-appb-000046
则每组包含的子序列数为6，最后多余的2个子序列可以放置在任意一组或者两组中，这里我们假定都放在最后一组，则得到子序列组分别为：第一组为[1,17,9,25,5,21],第二组为[13,29,3,19,11,27],第三组为[7,23,15,31,2,18],第四组为[10,26,6,22,14,30]，第五组数据为[4,20,12,28,8,24,16,32]。若S＝5时，按照
Figure PCTCN2018097782-appb-000047
则每组包含的子序列数为7，最后多余的4个子序列可以放置在任意至少一组中，这里我们假定都放在最后一组，则前四组包含的子序列数目均为7，而最后一组包含的子序列数目为4，得到子序列组分为为：[1,17,9,25,5,21,13]、[29,3,19,11,27,7,23]、[15,31,2,18,10,26,6]、[22,14,30,4,20,12,28]、[8,24,16,32]。
上述示例中对数值32进行操作，因为32为2的幂次，根据比特逆序可以容易获得32个数值。若数值不满足2的幂次时，将根据比特逆序操作产生序列中大于L的数值剔除，再重新排序，获得新的序列，分组按照新的序列进行操作。例如，L＝14，对[1～14]进行比特逆序操作，得到序列为q＝[1,9,5,13,3,11,7,15,2,10,6,14,4,12]，对q序列，从大到小排序获得的位置序列为：s 1＝[8,12,4,14,6,10,2,7,11,3,13,5,9,1]，从小到大排序获得的位置序列为： s 2＝[1,9,5,13,3,11,7,2,10,6,14,4,12,8]。后续则根据s 1序列或s 2序列确定分组。假定分为2组，根据s 1的排序，则第一组子序列组为[8 12 4 14 6 10 2]，第二组子序列组为[7,11,3,13,5,9,1]。
假定L＝31，按照方式2获得子序列组。首先对[1～31]进行比特逆序操作，获得序列[1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31,2,18,10,26,6,22,14,30,4,20,12,28,8,24]，按照获得的序列进行分组，分组方式与L＝32类似，在此不再赘述。
如图4所示，假定L＝31，按照方式3获得子序列组。从1～31中按照间隔5选择编号，获得第一组编号[1 6 11 16 21 26 31]，在编号1～31中将第一组的编号剔除，从剩余编号中按照间隔5选择编号，获得第二组编号[2 8 14 20 27]。以此类推，获得第三组包含的列数为[3 10 18 25]，第四组包含的列数为[4 13 23]，直至第八组数据为[12 15 19 24 30]。
假定L＝31，按照方式4获得子序列组。从1～31中按照间隔5选择编号，再从剩余编号中按照间隔5选择编号，以此类推，可以获得新的编号排序序列[1 6 11 16 21 26 31 2 8 14 20 27 3 10 18 25 4 13 23 5 17 29 7 22 9 28 12 15 19 24 30]。例如S＝5，则按
Figure PCTCN2018097782-appb-000048
或者
Figure PCTCN2018097782-appb-000049
确定每组的数目，假设每组包含的子序列数为6，最后多余的1个子序列可以放置在任意一组，或者自成一组，得到子序列组分别为：[1 6 11 16 21 26]、[31 2 8 14 20 27]、[3 10 18 25 4 13]、[23 5 17 29 7 22]、[9 28 12 15 19 24 30]。
假定L＝11，按照方式5获得子序列组。可以获得子序列组分别为[1 11 6]、[2 10 5]、[3 9 7]、[4 8]，或者获得子序列组分别为[1 11 6]、[2 10 7]、[3 9 5]、[4 8]。也可以先获得新的编号排序序列[1 11 6 2 10 5 3 9 7 4 8]或者[1 11 6 2 10 7 3 9 5 4 8]。再按照新的编号排序序列进行分组。
本申请实施例中子序列数L和子序列组数S可以至少综合几种因素来确定。例如：其一、可以与调制阶数联系起来，子序列组数S是调制阶数的函数的形式；其二、也可以与实际硬件实现联系起来，在硬件实现中S为2的幂次相对容易操作；其三、也可以与尽量随机化联系起来，S尽量为素数。
本申请实施例考虑上述几种因素，以L＝31为例，对上述交织方法做进一步详细的描述。此处考虑L为31，考虑因素主要由两个：31为素数，在随机数生成上具有先天优势；其次，31与LTE中涡轮码(即Turbo码)外交织器固定32列接近。当然，L可以选取其他任意数值，例如可以为其他在硬件上易于实现的数值，如{16,32,64}等，也可以考虑其他的素数，如{7，11，13,19，23,29,37,61}等。
首先，获取长度为M的待交织的比特序列，将待交织的比特序列输入交织器。可选的，可以固定交织器的列数为31列，按列的编号进行分组，再进行组内交织；也可以固定交织器的行数为31行，按行的编号进行分组，再进行组内交织。
以固定交织器的列数为31列为例，列数的编号为1～31，当然也可以为0～30。一列中的比特即为一个子序列，行数为M除以31向上取整或向下取整，所得结果即一列中的比特数，最后一个子序列中若不足可填充NULL。将31列分为S个子序列组，假设S的取值为5。选S值为5的考虑是：在高阶调制下，与当前的调制阶数联系起来，可以加1或者减1，若调制方式为16QAM，调制阶数为4，64QAM，调制阶数为6，若采用统一加1的方式，则S分别对应[5 7],若采用统一减1的方式，则分组数分别对应[3 5]，这里考虑统一处理，设置子序列组数为5。当使用更高阶调制时，256QAM时，子序列组数5仍然可以继续使用，因为5不仅与调制阶数可以联系，又是一素数。当然，子序列组数完全可以与调制阶数联 系起来，使得不同的调制阶数下对应的分组是不同的。
假设获得子序列组的方式为上述方式1，如图5所示，将1～31中的各个编号进行模5运算，余数分别为1、2、3、4、0。将余数为1的编号分为一组，获得子序列组S1，S1中包括的子序列为[1 6 11 16 21 26 31]；将余数为2的编号分为一组，获得子序列组S2，S2中包括的子序列为[2 7 12 17 22 27]；将余数为3的编号分为一组，获得子序列组S3，S3中包括的子序列为[3 8 13 18 23 28]；将余数为4的编号分为一组，获得子序列组S4，S4中包括的子序列为[4 9 14 19 24 29]；将余数为0的编号分为一组，获得子序列组S5，S5中包括的子序列为[5 10 15 20 25 30]。然后将各个子序列组内的比特进行组内交织，具体组内交织的方法如上述内容所述。可以发现，S1中子序列的数目为7，其余子序列组的子序列的数目为6。更一般的情况下，假定待分组的子序列数目为L，子序列组的组数为S，每组包含的子序列数最少为
Figure PCTCN2018097782-appb-000050
那么剩余的子序列数Rg为L对S取余。剩余子序列数可以按照顺序分别放到第1至Rg组内，也可以先放置偶(奇)数组内，再放置奇(偶)数组内，也可以按照某个简单函数来随机放置在前面的子序列组内。
例如，组内交织采用行列交织，行进列出的写入读取方式，至少有两组的交织深度是不同的，可选的，任意两组的交织深度均不同。一种举例如下：如图6所示，子序列组S1采用不交织，即顺序写入，顺序读出；子序列组S2采用交织深度为3，固定3行，按照行数3计算列数，按照行进列出的规则写入读出；子序列组S3采用交织深度为5，固定5行，按照行数5计算列数，按照行进列出的规则写入读出；子序列组S4采用交织深度为7，固定7行，按照行数7计算列数，按照行进列出的规则写入读出；子序列组S5采用交织深度为9，固定9行，按照行数9计算列数，按照行进列出的规则写入读出。最后，各个子序列组进行组内交织后，可以按照顺序输出，或者进行简单的位置交织后输出。图6中仅示意了按顺序输出。
可选的，子序列组数S可以取任意其他值，例如可以取值[2，3,4,6,7]，则类似的，可以分别对31按照[2,3,4,6,7]进行取模运算，以获得不同的子序列组。对每个子序列组在组内交织时选择的交织深度处理上也可以是不同的。当S＝2时，即列数据根据奇偶重排，交织深度要具有明显的差异性才更具有随机性，子序列组S1～S5的交织深度可以是{1,7}或者{3,11}或者{5,10}或者{7,11}等。当S＝3时，子序列组S1～S5的交织深度可以是{1,3,5}或者{3,5,7}或者{3,7，11}或者{5,7,11}或者{2,4,6}等。当S＝4时，子序列组S1～S5的交织深度可以是{1,3,5,7}或者{3,5,7,9}或者{3,5,7,11}或者{5,7,11,13}或者{2,4,6,8}或者{2,5,8,11}等。当S＝6时，子序列组S1～S5的交织深度可以是{1,3,5,7,9,11}或者{1,3,5,1,3,5}或者{5,7,9,5,7,9}或者{3,3,5,5,7,7}或者{3,7,11,3,7,11}或者{2,4,6,8,10,12}或者{2,4,6,6,4,2}或者{5,7,9,9,7,5}或者{11,9,7 7,9,11}等。当S＝7时，子序列组S1～S5的交织深度可以是{1,3,5,7,9,11,13}或者{1,3,5,7,7,5,3,1}或者{5,7,9,11,9,7,5}或者{3,3,5,5,7,7,9}或者{3,3,7,7,11,11,1}或者{2,4,6,8,10,12,14}或者{2,4,6,8,6,4,2}或者{5,7,9,11,9,7,5}或者{11,9,7,5,7,9,11}等。
如上文对组内交织方式的描述，可以对组内的所有比特进入交织器进行交织，也可以将组内各个子序列在子序列内进行交织，将子序列内的比特进入交织器进行交织后，输出的比特再组成交织后的子序列组。例如，S1中包括的子序列[1 6 11 16 21 26 31]的所有比特进入交织器进行交织，或者，将第1列作为待交织比特进入交织器进行交织，第6列作为待交织比特进入交织器进行交织，同样，第11列、第16列、第21列、第26列、第31列 各自进行交织。可选的，在交织前将子序列[1 6 11 16 21 26 31]的排序位置进行交织，交织方法不限定，例如，交织后子序列为[11 26 1 6 31 16 21]。
类似的，若固定交织器的行数为31行，行数的编号为1～31，一行中的比特即为一个子序列，列数为待交织比特数除以31向上取整或向下取整，所得结果即一行中的比特数，最后一个子序列中若不足可填充NULL。将31行分为S个子序列组，假设S的取值为5。将31行进行分组的方法以及组内交织的方法可以参考上述固定交织器的列数为31列时的方法，其方法类似，重复之处在此不再赘述。
上述对L＝31的举例中，以方式1获得子序列组为例，可以理解，可以选择上文中提到的任一种方式获得子序列组，举例中后续描述的子序列组内的交织方法同样可以适用。
可选的，若固定交织器的列数为L＝31列，列数的编号为1～31，一列中的比特即为一个子序列，行数为待交织比特数除以31向上取整。将31列数据分为S个子序列组，假设S的取值为5。每组内的数据按照行进行交换处理，各组所进行的行交换方式可以不同，例如第一组数据的行不进行交换处理，直接按照列或者行顺序读出，第二组数据的行按照间隔3进行交换顺序，第三组数据的行按照间隔5进行交换顺序，第四组数据的行按照间隔7进行交换顺序，第五组数据的行按照间隔11进行交换顺序，假定交织器的大小为R行L列，间隔为T,那么每组的行交换后的行顺序可以表示为[1:T:R 2:T:R 3:T:R … T:T:R]，每组间隔T的选取可以不固定，主要原则是与前面各组的行交换方式不能完全相同，例如上述五组数据的行交换间隔可以为[1 3 5 7 9]等，并不作限定。此外，每组的行交换顺序不限定上述形式，可以采用其他顺序进行交换,例如第一组数据不交换，第二组采用间隔式交换，第三组采用比特逆序式交换，第四组采用奇偶式交换，第五组采用逆序式交换等。
可选的，若固定交织器的行数为L＝31行，行数的编号为1～31，一行中的比特即为一个子序列，列数为待交织比特数除以31向上取整。将31行数据分为S个子序列组，假设S的取值为5。每组内的数据按照列进行交换处理，各组所进行的列交换方式可以不同，例如第一组数据的列不进行交换处理，直接按照列或者行顺序读出，第二组数据的列按照间隔3进行交换顺序，第三组数据的列按照间隔5进行交换顺序，第四组数据的列按照间隔7进行交换顺序，第五组数据的列按照间隔11进行交换顺序，假定交织器的大小为C列L行，间隔为T,那么每组的列交换后的列顺序可以表示为[1:T:C 2:T:C 3:T:C … T:T:C]，每组间隔T的选取可以不固定，主要原则是与前面各组的行交换方式不能完全相同，例如上述五组数据的列交换间隔可以为[1 3 5 7 9]等，并不作限定。此外，每组的列交换顺序不限定上述形式，可以采用其他顺序进行交换，例如第一组数据不交换，第二组采用间隔式交换，第三组采用比特逆序式交换，第四组采用奇偶式交换第五组采用逆序式交换等。
可选的，若固定交织器的行数为L＝31行，行数的编号为1～31，一行中的比特即为一个子序列，列数C为待交织比特数除以31向上取整。将C列数据分为S个子序列组，假设S的取值为5。每组内的数据按照行进行交换处理，各组所进行的行交换方式可以不同，例如第一组数据的行不进行交换处理，直接按照行或者列顺序读出，第二组数据的行按照间隔3进行交换顺序，第三组数据的行按照间隔5进行交换顺序，第四组数据的行按照间隔7进行交换顺序，第五组数据的行按照间隔11进行交换顺序，假定交织器的大小为C列L行，间隔为T,那么每组的行交换后的行顺序可以表示为[1:T:L 2:T:L 3:T:L … T:T:L]，每组间隔T的选取可以不固定，主要原则是与前面各组的行交换方式不能完全相同，例如 上述五组数据的行交换间隔可以为[1 3 5 7 9]等，并不作限定。此外，每组的行交换顺序不限定上述形式，可以采用其他顺序进行交换，例如第一组数据不交换，第二组采用间隔式交换，第三组采用比特逆序式交换，第四组采用奇偶式交换第五组采用逆序式交换等。
可选的，若固定交织器的列数为L＝31列，列数的编号为1～31，一列中的比特即为一个子序列，行数R为待交织比特数除以31向上取整。将R行数据分为S个子序列组，假设S的取值为5。每组内的数据按照列进行交换处理，各组所进行的列交换方式可以不同，例如第一组数据的列不进行交换处理，直接按照列或者行顺序读出，第二组数据的列按照间隔3进行交换顺序，第三组数据的列按照间隔5进行交换顺序，第四组数据的列按照间隔7进行交换顺序，第五组数据的列按照间隔11进行交换顺序，假定交织器的大小为L列R行，间隔为T,那么每组的行交换后的行顺序可以表示为[1:T:L 2:T:L 3:T:L … T:T:L]，每组间隔T的选取可以不固定，主要原则是与前面各组的列交换方式不能完全相同，例如上述五组数据的列交换间隔可以为[1 3 5 7 9]等，并不作限定。此外，每组的列交换顺序不限定上述形式，可以采用其他顺序进行交换，例如第一组数据不交换，第二组采用间隔式交换，第三组采用比特逆序式交换，第四组采用奇偶式交换第五组采用逆序式交换等。
可选的，若固定交织器的行数为L＝31行，行数的编号为1～31，一行中的比特即为一个子序列，列数为待交织比特数除以31向下取整。则在不完全整除时，剩余比特可以零散式放置在多个子序列中，或者集中式放在一个子序列中。分组方式可以采取与前述相同的方式，此处不再赘述。
综上所述，本申请实施例通过获得子序列组以及在子序列组内采用不同的交织方式，能够与Polar码结合，使得交织效果较好，Polar码的性能提高。
本申请实施例在译码端，译码流程大致为：对接收到的待译码序列进行解交织和解速率匹配，并对获得的序列进行Polar码译码。类似的，译码端可以根据编码端交织方法获得与编码端交织方法对应的解交织方法，按照获得的解交织方法进行解交织操作。解交织方法是根据交织方法确定的，解交织方法是交织方法的逆操作。例如，第一序列通过交织方法进行交织操作后获得第二序列，则对第二序列通过根据交织方法确定的解交织方法，能够获得第一序列。若交织方法采用行进列出进行交织，则解交织方法采用列进行出进行解交织。其中，编码端的交织方法如上所述，在此不再赘述。
具体的说，当接收端获取编码端的交织方法后，也就获取了交织的图样。不失一般性，将输入的数据以向量形式来表示，例如总共有A个比特(A>＝1)，经过上述编码端的交织方法后，按行写成长度为A的向量，第a_interleave(1<＝a_interleave<＝A)个比特b a_interleave由交织前的第a_original(1<＝a_original<＝A)个比特b a_original通过交织得到。那么相应的，在接收端，接收端需要知道这个交织图案(或者说映射关系)或者其他等价的表示方法，解交织的操作(也就是交织方法的逆操作)就是将待解交织的比特按行写成长度为A的向量，根据交织图案或其他等价的表示方法，将第a_interleave个比特b a_interleave解交织(或者说逆映射)到第a_original个比特的位置作为b a_original。当然，收发两端按列写成长度为A的向量的方法也同样适用，事实上，只需收发两端约定或者按照协议按同样的方法生成长度为A的向量即可。
类似的，还可以写成矩阵的方式，即把输入的数据以矩阵形式来表示，例如写成B行C列的矩阵(B>＝1,C>＝1)，那么经过上述编码端的交织方法后，第a_i_interleave行第 a_j_interleave列(1<＝a_i_interleave<＝B,1<＝a_j_interleave<＝C)的比特b a_interleave由交织前的第a_i_original行第a_j_original列的比特b a_original通过交织得到。那么相应的，在接收端，接收端需要知道这个交织图案(或者说映射关系)或者其他等价的表示方法，解交织的操作(也就是交织方法的逆操作)就是将待解交织的比特根据与发送端相同的规则写成B行C列的矩阵，根据交织图案或其他等价的表示方法，将第a_i_interleave行第a_j_interleave列的比特b a_interleave解交织(或者说逆映射)到第a_i_original行第a_j_original列的位置作为b a_original即可。例如，发送端进行行进列出操作则接收端进行列进行出操作，发送端进行列进行出操作则接收端进行行进列出操作，发送端进行行进行出操作则接收端进行行进行出操作，发送端进行列进列出操作则接收端进行列进列出操作，或者按照上述交织方法所述，B＝31或者C＝31，等等。
基于图3所示的交织方法的同一发明构思，如图7所示，本申请实施例中还提供一种交织装置700，该交织装置700用于执行图3所示的交织方法。图3所示的交织方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，交织装置700包括：输入接口电路701，用于获取待交织的比特序列；逻辑电路702，用于执行上述图3所示的交织方法，具体请见前面方法实施例中的描述，此处不再赘述；输出接口电路703，用于输出交织后的比特序列。
可选的，交织装置700在具体实现时可以是芯片或者集成电路。
可选的，当上述实施例的交织方法中的部分或全部通过软件来实现时，如图8所示，交织装置800包括：存储器801，用于存储程序；处理器802，用于执行存储器801存储的程序，当程序被执行时，使得交织装置800可以实现上述图3实施例提供的交织方法。
可选的，上述存储器801可以是物理上独立的单元，也可以与处理器802集成在一起。
可选的，当上述图3实施例的交织方法中的部分或全部通过软件实现时，交织装置800也可以只包括处理器802。用于存储程序的存储器801位于交织装置800之外，处理器802通过电路/电线与存储器801连接，用于读取并执行存储器801中存储的程序。
处理器802可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。
处理器802还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic,GAL)或其任意组合。
存储器801可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器801也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器801还可以包括上述种类的存储器的组合。
基于图3所示的交织方法的同一发明构思，如图9所示，本申请实施例中还提供一种交织装置900，该交织装置900用于执行图3所示的交织方法。该交织装置900包括：
获取单元901，用于获取待交织的比特序列。
其中，待交织的比特序列包括L个子序列，L个子序列至少包括第一子序列组和第二 子序列组，第一子序列组至少包括2个子序列，第二子序列组至少包括1个子序列，L为大于1的正整数。
交织单元902，用于对获取单元901获取的第一子序列组中的子序列采用第一交织方式进行交织，对第二子序列组中的子序列不交织或者采用第二交织方式进行交织。
可选的，第一子序列组中的子序列的各个编号分别按照设定值进行取模运算的结果均为第一运算结果；第二子序列组中的子序列的各个编号分别按照设定值进行取模运算的结果均为第二运算结果。
可选的，第一交织方式为第一行列交织，第二交织方式为第二行列交织，第一行列交织和第二行列交织的行数不同或列数不同。
可选的，交织单元902用于：将第一子序列组中的所有比特逐比特输入交织器进行行列交织；或者，将第一子序列组中的部分或全部子序列分别在子序列内进行行列交织。
可选的，交织单元902用于：将第一子序列组中的各个子序列的位置进行交织处理；
将第一子序列组中的所有比特输入行列交织器进行行列交织；或者，将第一子序列组中的各个子序列分别在子序列内进行行列交织。
可选的，交织单元902还用于：在获取单元获取待交织的比特序列之后，对第一子序列组中的子序列采用第一交织方式进行交织，对第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，将待交织的比特序列输入i行j列的交织器；若i＝L，一行中的比特组成一个子序列，逐行读取第一子序列组中的子序列，以及逐行读取第二子序列组中的子序列；或者，j＝L，一列中的比特组成一个子序列，逐列读取第一子序列组中的子序列，以及逐列读取第二子序列组中的子序列。
可选的，其特征在于，交织单元902还用于：在获取单元901获取待交织的比特序列之后，对第一子序列组中的子序列采用第一交织方式进行交织，对第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，将L个子序列进行分组，以获得第一子序列组和第二子序列组。
可选的，L取值为31。
可选的，交织单元902还用于：将第一子序列组和第二子序列组的位置进行交织处理。
基于与上述实施例提供的解交织方法同一发明构思，如图10所示，本申请实施例还提供一种解交织装置1000，解交织装置1000可用于执行本申请实施例提供的解交织方法，解交织装置1000包括：
获取单元1001，用于获取待解交织的比特序列；
解交织单元1002，用于按照解交织方法对所述待解交织的比特序列进行解交织操作，所述解交织方法是根据交织方法确定的,解交织方法是交织方法的逆操作。
其中，所述交织方法包括：获取待交织的比特序列，所述待交织的比特序列包括L个子序列，所述L个子序列至少包括第一子序列组和第二子序列组，所述第一子序列组至少包括2个子序列，所述第二子序列组至少包括1个子序列，L为大于1的正整数；对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织。
可选的，所述第一子序列组中的子序列的各个编号分别按照设定值进行取模运算的结果均为第一运算结果；
所述第二子序列组中的子序列的各个编号分别按照所述设定值进行取模运算的结果均为第二运算结果。
可选的，所述第一交织方式为第一行列交织，所述第二交织方式为第二行列交织，所述第一行列交织和所述第二行列交织的行数不同或列数不同。
可选的，对所述第一子序列组中的子序列采用第一交织方式进行交织，包括：
将所述第一子序列组中的所有比特逐比特输入交织器进行行列交织；或者，
将所述第一子序列组中的部分或全部子序列分别在子序列内进行行列交织。
可选的，所述获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，所述交织方法还包括：
将所述待交织的比特序列输入i行j列的交织器；
i＝L，一行中的比特组成一个所述子序列，逐行读取所述第一子序列组中的子序列，以及逐行读取所述第二子序列组中的子序列；或者，j＝L，一列中的比特组成一个所述子序列，逐列读取所述第一子序列组中的子序列，以及逐列读取所述第二子序列组中的子序列。
可选的，所述获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，所述交织方法还包括：将所述L个子序列进行分组，以获得所述第一子序列组和所述第二子序列组。
基于上述实施例提供的解交织方法的同一发明构思，如图11所示，本申请实施例中还提供一种解交织装置1100，该解交织装置1100用于执行上述解交织方法。上述解交织方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，解交织装置1100包括：输入接口电路701，用于获取待解交织的比特序列；逻辑电路702，用于执行上述解交织方法；输出接口电路703，用于输出解交织后的序列。
可选的，解交织装置1100在具体实现时可以是芯片或者集成电路。
可选的，当上述实施例的交织方法中的部分或全部通过软件来实现时，如图12所示，解交织装置1200包括：存储器1201，用于存储程序；处理器1202，用于执行存储器1201存储的程序，当程序被执行时，使得解交织装置1200可以实现上述实施例提供的解交织方法。
可选的，上述存储器1201可以是物理上独立的单元，也可以与处理器1202集成在一起。
可选的，当上述实施例的解交织方法中的部分或全部通过软件实现时，解交织装置1200也可以只包括处理器1202。用于存储程序的存储器1201位于解交织装置1200之外，处理器1202通过电路/电线与存储器1201连接，用于读取并执行存储器1201中存储的程序。
处理器1202可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。
处理器1202还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑 (generic array logic,GAL)或其任意组合。
存储器1201可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器1201也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器1201还可以包括上述种类的存储器的组合。
本申请实施例还提供了一种网络设备，参见图13所示，上述交织装置和/或解交织装置可以被安装在网络设备110中。除了上述交织装置和解交织装置外，网络设备110还可以包括一个收发器1302，交织装置交织后的比特序列经过后续的变化或处理后通过收发器1302发送给终端112，或者该收发器1302还用于接收来自于终端112的信息/数据，这些信息/数据经过一系列处理被转换成待解交织的序列，经过解交织装置的处理后得到解交织后的序列。当网络设备110还可以包括网络接口1304，用于与其它的网络设备进行通信。
同理，上述交织交织装置和/或解交织装置可以被安装在终端112中。除了上述交织装置和解交织装置外，终端112还可以包括一个收发器1312，交织装置交织后的比特序列经过后续的变化或处理后通过收发器1312发送给网络设备110，或者该收发器1312还用于接收来自于网络设备110的信息/数据，这些信息/数据经过一系列处理被转换成待解交织的序列，经过解交织装置的处理后得到解交织后的序列。终端112还可以包括用于输入输出接口1314，用于接收用户输入的信息，对于需要发送给网络设备110的信息，则需要经过交织器的处理后再通过收发器1312发送给网络设备110。解交织器解交织后的数据经过后续处理后也可以通过输入输出接口1314呈现给用户。
本申请实施例还提供了一种计算机存储介质，存储有计算机程序，该计算机程序包括用于执行图3所示的交织方法和上述实施例提供的解交织方法。
本申请实施例还提供了一种Polar码编码装置，包括上述图7～图9任一种交织装置和图10～图12任一种解交织装置。
本申请实施例还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行图3所示的交织方法以及上述实施例提供的解交织方法。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方 框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (26)

  1. 一种交织方法，其特征在于，包括：
    获取待交织的比特序列，所述待交织的比特序列包括L个子序列，所述L个子序列至少包括第一子序列组和第二子序列组，所述第一子序列组至少包括2个子序列，所述第二子序列组至少包括1个子序列，L为大于1的正整数；
    对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织。
  2. 如权利要求1所述的方法，其特征在于，所述第一子序列组中的子序列的各个编号分别按照设定值进行取模运算的结果均为第一运算结果；
    所述第二子序列组中的子序列的各个编号分别按照所述设定值进行取模运算的结果均为第二运算结果。
  3. 如权利要求1或2所述的方法，其特征在于，所述第一交织方式为第一行列交织，所述第二交织方式为第二行列交织，所述第一行列交织和所述第二行列交织的行数不同或列数不同。
  4. 如权利要求1～3任一项所述的方法，其特征在于，对所述第一子序列组中的子序列采用第一交织方式进行交织，包括：
    将所述第一子序列组中的所有比特逐比特输入交织器进行行列交织；或者，
    将所述第一子序列组中的部分或全部子序列分别在子序列内进行行列交织。
  5. 如权利要求1～3任一项所述的方法，其特征在于，对所述第一子序列组中的子序列采用第一交织方式进行交织，包括：
    将所述第一子序列组中的各个子序列的位置进行交织处理；
    将所述第一子序列组中的所有比特输入行列交织器进行行列交织；或者，将所述第一子序列组中的各个子序列分别在子序列内进行行列交织。
  6. 如权利要求1～5任一项所述的方法，其特征在于，所述获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，所述方法还包括：
    将所述待交织的比特序列输入i行j列的交织器；
    i＝L，一行中的比特组成一个所述子序列，逐行读取所述第一子序列组中的子序列，以及逐行读取所述第二子序列组中的子序列；或者，j＝L，一列中的比特组成一个所述子序列，逐列读取所述第一子序列组中的子序列，以及逐列读取所述第二子序列组中的子序列。
  7. 如权利要求1～5任一项所述的方法，其特征在于，所述获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，所述方法还包括：
    将所述L个子序列进行分组，以获得所述第一子序列组和所述第二子序列组。
  8. 如权利要求1～7任一项所述的方法，其特征在于，L取值为31。
  9. 如权利要求1～8任一项所述的方法，其特征在于，所述方法还包括：
    将所述第一子序列组和所述第二子序列组的位置进行交织处理。
    获取待解交织的序列；
    按照解交织方式对所述待解交织的序列进行解交织操作，所述解交织方式是根据交织 方式确定的；
    其中，所述交织方式包括：获取待交织的比特序列，所述待交织的比特序列包括L个子序列，所述L个子序列至少包括第一子序列组和第二子序列组，所述第一子序列组至少包括2个子序列，所述第二子序列组至少包括1个子序列，L为大于1的正整数；对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织。
  10. 一种交织装置，其特征在于，包括：
    获取单元，用于获取待交织的比特序列，所述待交织的比特序列包括L个子序列，所述L个子序列至少包括第一子序列组和第二子序列组，所述第一子序列组至少包括2个子序列，所述第二子序列组至少包括1个子序列，L为大于1的正整数；
    交织单元，用于对所述获取单元获取的第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织。
  11. 如权利要求10所述的装置，其特征在于，所述第一子序列组中的子序列的各个编号分别按照设定值进行取模运算的结果均为第一运算结果；
    所述第二子序列组中的子序列的各个编号分别按照所述设定值进行取模运算的结果均为第二运算结果。
  12. 如权利要求10或11所述的装置，其特征在于，所述第一交织方式为第一行列交织，所述第二交织方式为第二行列交织，所述第一行列交织和所述第二行列交织的行数不同或列数不同。
  13. 如权利要求10～12任一项所述的装置，其特征在于，所述交织单元用于：
    将所述第一子序列组中的所有比特逐比特输入交织器进行行列交织；或者，
    将所述第一子序列组中的部分或全部子序列分别在子序列内进行行列交织。
  14. 如权利要求10～13任一项所述的装置，其特征在于，所述交织单元用于：
    将所述第一子序列组中的各个子序列的位置进行交织处理；
    将所述第一子序列组中的所有比特输入行列交织器进行行列交织；或者，将所述第一子序列组中的各个子序列分别在子序列内进行行列交织。
  15. 如权利要求10～14任一项所述的装置，其特征在于，所述交织单元还用于：在所述获取单元获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，将所述待交织的比特序列输入i行j列的交织器；若i＝L，一行中的比特组成一个所述子序列，逐行读取所述第一子序列组中的子序列，以及逐行读取所述第二子序列组中的子序列；或者，j＝L，一列中的比特组成一个所述子序列，逐列读取所述第一子序列组中的子序列，以及逐列读取所述第二子序列组中的子序列。
  16. 如权利要求10～14任一项所述的装置，其特征在于，所述交织单元还用于：在所述获取单元获取待交织的比特序列之后，对所述第一子序列组中的子序列采用第一交织方式进行交织，对所述第二子序列组中的子序列不交织或者采用第二交织方式进行交织之前，将所述L个子序列进行分组，以获得所述第一子序列组和所述第二子序列组。
  17. 如权利要求10～16任一项所述的装置，其特征在于，L取值为31。
  18. 如权利要求10～17任一项所述的装置，其特征在于，所述交织单元还用于：
    将所述第一子序列组和所述第二子序列组的位置进行交织处理。
  19. 一种交织装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1～9任一项所述的方法。
  20. 如权利要求19所述的装置，其特征在于，所述交织装置为芯片或集成电路。
  21. 一种交织装置，其特征在于，包括：
    输入接口电路，用于获取待编码的比特序列；
    逻辑电路，用于基于获取的待编码的比特序列执行所述权利要求1～9任一项所述的方法，得到交织后的比特；
    输出接口电路，用于输出交织后的比特。
  22. 一种芯片，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1～9任一项所述的方法。
  23. 一种芯片，其特征在于，包括：
    输入接口电路，用于获取待编码的比特序列；
    逻辑电路，用于基于获取的待编码的比特序列执行所述权利要求1～9任一项所述的方法，得到交织后的比特；
    输出接口电路，用于输出交织后的比特。
  24. 一种通信系统，其特征在于，所述通信系统包括网络设备和终端，所述网络设备或终端执行所述权利要求1～9任一项所述的方法。
  25. 一种计算机存储介质，其特征在于，所述计算机存储介质存储有计算机程序，所述计算机程序包括用于执行所述权利要求1～9任一项所述的方法的指令。
  26. 一种包含指令的计算机程序产品，其特征在于，所述计算机程序产品在计算机上运行时，使得所述计算机执行上述所述权利要求1～9任一项所述的方法。
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