WO2017119331A1 - Solid-state image capture device, method for driving solid-state image capture device, and electronic equipment - Google Patents

Abstract

A solid-state image capture device 10 capable of expanding dynamic range by combining a plurality of readout signals. A column signal processing unit includes an ADC 410 and a comparison/selection unit 430 which compares the level of an input node [Y] to which a readout signal read from a pixel is input to a pre-set reference voltage [V20], and selects an input state of the readout signal, read from the pixel, into the input node [Y] in accordance with the result of the comparison. This configuration makes it possible to prevent a decrease in AD conversion accuracy while suppressing an increase in circuit area or processing time, and to also achieve a wide dynamic range and hence high image quality.

Description

Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus

The present invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic apparatus.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor has been put to practical use as a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates charges.
CMOS image sensors are widely applied as a part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile terminal devices (mobile devices) such as mobile phones. Yes.

The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD: Floating Diffusion) for each pixel, and the readout selects one row in the pixel array. However, a column parallel output type in which these are simultaneously read in the column direction is the mainstream.

By the way, as a pixel configuration of the solid-state imaging device (CMOS image sensor), for example, for one photodiode (photoelectric conversion element), a transfer transistor as a transfer element, a reset transistor as a reset element, and a source follower element A pixel having a four-transistor (4Tr) configuration that includes one source follower transistor and one selection transistor as a selection element can be exemplified.

The transfer transistor is selected during a predetermined transfer period and becomes conductive, and transfers the charges (electrons) photoelectrically converted and accumulated by the photodiode to the floating diffusion FD.
The reset transistor is selected during a predetermined reset period and becomes conductive, and resets the floating diffusion FD to the potential of the power supply line.
The selection transistor is selected during the reading scan and becomes conductive. As a result, the source follower transistor outputs a column output read signal obtained by converting the charge of the floating diffusion FD into a voltage signal corresponding to the charge amount (potential) to the vertical signal line.

For example, in the read scan period, after the floating diffusion FD is reset to, for example, the potential (reference potential) of the power supply line in the reset period, the charge of the floating diffusion FD is changed to a voltage signal corresponding to the amount of charge (potential) by the source follower transistor. The converted signal is output to the vertical signal line as a reference level read reset voltage (reference level signal) Vrst.
Subsequently, in a predetermined transfer period, charges (electrons) photoelectrically converted and accumulated by the photodiode are transferred to the floating diffusion FD. Then, the charge of the floating diffusion FD is converted into a voltage signal corresponding to the amount of electric charge (potential) by the source follower transistor, and is output as a read signal voltage (signal level signal) Vsig to the vertical signal line.
The output signal of the pixel is processed as a difference signal (Vsig−Vrst).

Thus, a normal pixel readout signal (hereinafter sometimes referred to as a pixel signal) PS is formed by one reference level readout reset voltage Vrst and one signal level readout signal voltage Vsig.

Incidentally, various methods for realizing a high-quality solid-state imaging device (CMOS image sensor) having a high dynamic range (HDR: High Dynamic Range) have been proposed for improving characteristics.

In the solid-state imaging device, as a method for increasing (enlarging) the dynamic range, for example, two types of signals having different accumulation times are read from the same pixel of the image sensor, and these two types of signals are combined (combined). , A method for expanding the dynamic range, a method for expanding the dynamic range by combining (combining) signals in the low illuminance area obtained with high sensitivity pixels and signals in the high illuminance area obtained with low sensitivity pixels, etc. It has been known.

For example, Patent Document 1 discloses a high dynamic range technology that divides into two or more different exposure times for imaging corresponding to a high illuminance side with a short exposure time and imaging corresponding to a low illuminance with a long exposure time. .

A pixel readout signal (pixel signal) PSD when this high dynamic range technology is adopted is a plurality of M (for example, M = 2) reference level readout reset voltages (reference level signals) Vrst and a plurality of M (M = 2). ) Signal level read signal voltage (signal level signal) Vsig.
The pixel readout signal (pixel signal) PSD in this case is processed as a so-called uninterrupted readout signal.

1A and 1B show a normal pixel readout signal (pixel signal) of a solid-state imaging device (CMOS image sensor) and an uninterrupted pixel readout signal when a high dynamic range technology is adopted (no interruption). It is a figure which shows an example of a pixel signal.
FIG. 1A shows an example of a normal pixel readout signal (pixel signal) PS, and FIG. 1B shows an example of a pixel readout signal without interruption (pixel signal without interruption) PSD.

As shown in FIG. 1A, the normal pixel signal PS [N] includes one reference level signal (hereinafter also simply referred to as a reference level) Vrst [N] and one signal level signal ( Hereinafter, it may be simply referred to as a signal level) Vsig [N].
That is, one reference level Vrst [N] and one signal level Vsig [N] are included in one pixel signal PS [N].
The output data OD [N] in this case is the reference level Vrst [N] −the signal level Vsig [N].
Similarly, one reference level Vrst [N + 1] and one signal level Vsig [N + 1] are included in one pixel signal PS [N + 1].
In this case, the output data OD [N + 1] becomes the reference level Vrst [N + 1] −the signal level Vsig [N + 1].

As shown in FIG. 1B, the uninterrupted pixel signal PSD [N] includes M (M = 2 in this example) reference levels Vrst [N, 1] in one pixel signal PSD [N]. , Vrst [N, 2] and M signal levels Vsig [N, 1] and Vsig [N, 2].
That is, in one uninterrupted pixel signal PSD [N], M reference levels Vrst [N, 1], Vrst [N, 2] and M signal levels Vsig [N, 1], Vsig [N , 2].
In this case, the output data OD [N, 1] is the reference level Vrst [N, 1] −the signal level Vsig [N, 1], and the output data OD [N, 2] is the reference level Vrst [N, 2]. The signal level Vsig [N, 2].
Similarly, in one uninterrupted pixel signal PSD [N + 1], M reference levels Vrst [N + 1, 1], Vrst [N + 1, 2] and M signal levels Vsig [N + 1, 1], Vsig [ N + 1, 2].
In this case, the output data OD [N + 1,1] is the reference level Vrst [N + 1,1] −the signal level Vsig [N + 1,1], and the output data OD [N + 1,2] is the reference level Vrst [N + 1,2]. The signal level is Vsig [N + 1, 2].

As described above, the pixel signal PSD without interruption includes M reference levels Vrst and M signal levels Vsig in one pixel signal PSD, and the arrangement order is one output data OD [N , M], a plurality of reference levels Vrst [N, M] must be input first and then the signal level Vsig [N, M] is input.
FIG. 1B shows one of M = 2 and one of the possible arrangements.

FIGS. 2A to 2D show a method for increasing (enlarging) the dynamic range in a solid-state imaging device, and there are no discontinuous pixels when the number M of readout signals to be combined is 2 (M = 2). It is a figure for demonstrating the synthetic | combination processing method of a signal.

The uninterrupted pixel signal PSD can have different amplification factors K for M signals for the same light quantity.
2A to 2D are examples in which M = 2 and the amplification factor ratio K (M = 1) / K (M = 2) = 4.

The output data OD [*, 1] and OD [*, 2] obtained from the uninterrupted pixel signal PSD shown in FIG. 1B are signals having different characteristics as shown in FIG. .
In the synthesizing process, the output data OD [*, 2] is amplified according to the ratio to obtain one synthesized final output data ODA as shown in FIG.

As the synthesis method, the first method by switching shown in FIG. 2C or the second method by averaging shown in FIG. 2D is adopted, and the final output data ODA is obtained.

For this reason, conventionally, in the first method, the error significantly emphasizes the boundary (joining position (point)) [X], and the operation in the second method for relaxing the error always requires two output data OD [*]. , 1] and OD [*, 2], which further complicates signal processing.

Hereinafter, a configuration for reducing (deleting) individual variations and the like in a circuit system that processes pixel readout signals (pixel signals) will be described.
Here, a description will be given in association with a configuration for generating output data for a normal pixel signal.

FIG. 3 is a diagram illustrating an example of a readout circuit including a new reference level setting function in a normal pixel readout signal (pixel signal) processing system.
In FIG. 3, pixels PXL (N) and PXL (N + 1) in the same column are connected to a common readout signal line LS. A clamp circuit 1 for setting a new reference level is disposed at an input stage between the signal line LS and an input node [Y] of an analog digital converter (ADC) (not shown).
The clamp circuit 1 includes an amplifier AMP1, capacitors C1 and C2, and a switch SW1.

For example, in the processing of the normal pixel readout signal (pixel signal) PS shown in FIG. 1A, the reference level Vrst [N] and the reference level Vrst [N + 1] may have different levels due to individual variations of the pixel PXL.
Therefore, in the example of FIG. 3, individual variations of pixels are deleted using a new reference level [V1] by the clamp circuit 1 in the readout circuit.

4A and 4B are diagrams illustrating an example of a normal pixel readout signal (pixel signal) when a new reference level Vrst [V1] by the clamp circuit 1 is applied.
4A shows the clamp circuit of FIG. 3 in a simplified manner with a capacitor C and a switch SW1, and FIG. 4B shows an example of a normal pixel readout signal (pixel signal).

As shown in FIGS. 4A and 4B, when the switch SW1 is turned on by the clamp signal CLP in the clamp circuit 1, the reference level Vrst appearing at the node [Y] using the new reference level [V1]. To change.
At this time, the signal level Vsig [N] becomes a new signal level Vsig [N ′] based on the new reference level [V1].
Even in this case, the difference between the reference level [V1] and the signal level Vsig [N ′] is constant.

FIGS. 5A and 5B are diagrams for explaining a configuration for deleting individual variations generated in the ADC.
FIG. 5A shows an example of a state of AD conversion and output processing of a normal pixel readout signal (pixel signal), and FIG. 5B shows a configuration example of a column parallel processing unit including an ADC. .

In the readout circuit of the column parallel output type solid-state imaging device, as shown in FIG. 5B, ADCs 2 are arranged in each column corresponding to the column output of the pixel portion, and a switch is connected to the output side of each ADC 2. A holding unit 3-1 that holds the reference level Vrst and a holding unit 3-2 that holds the signal level Vsig are arranged via SW3-1 and SW3-2, and further calculates the difference between the signal level Vsig and the reference level Vrst. A vessel 4 is arranged.

In column parallel reading, individual variations also occur in the ADC.
Therefore, the reference level [V1] and the signal level Vsig [N ′] generated at the input node [Y] in FIG. 4A are each AD-converted by the ADC 2, and one output data OD [N] is obtained by digital arithmetic processing. ] Is generated.
Thereby, the individual variation of ADC2 is deleted.

FIG. 6 is a diagram illustrating an example of a column readout system having a configuration for deleting individual variations corresponding to a pixel readout signal without interruption (a pixel signal without interruption).
FIG. 7 is a diagram illustrating an example of a state of AD conversion processing of an uninterrupted pixel readout signal (an uninterrupted pixel signal).

In the readout circuit of FIG. 6, ADCs 2A are arranged in each column corresponding to the column output of the pixel portion, and the reference level Vrst and the signal level Vsig are provided on the output side of the ADC 2A via the switches SW3-1 to SW3-2M. Holding units 3-1 to 3-2M are arranged, and a synthesis processing unit 5 for synthesizing the signals held in the holding units 3-1 to 3-2M is arranged.

The ADC 2A includes a clamp circuit 1A having the same configuration as that in FIG. 4A and a conversion unit 2-1 connected to the input node [Y].

Japanese Patent No. 3998414

However, the readout system of FIG. 6 described above has three disadvantages as shown below.

First, as shown in FIG. 6, the readout system of FIG. 6 requires 2M holding units for M uninterrupted pixel signals. In addition, since this requires 2M AD conversion operations, there is a disadvantage that the circuit area increases and the processing time becomes longer.

The second disadvantage will be described with reference to FIG. 7 taking M = 2 as an example.
Although the clamping operation is desired to be performed twice within the same pixel signal, if the clamping operation is performed at the reference level Vrst [N, 2], the state at the first reference level Vrst [N, 1] is lost. That is, the clamping operation can be performed only once.
For this reason, the readout system of FIG. 6 degrades AD conversion accuracy.

The third disadvantage is in the synthesis process.
As described above, as the synthesis method, the first method by switching shown in FIG. 2C or the second method by averaging shown in FIG. 2D is adopted. In signal processing for combining, the second method is superior to the first method, but the processing time of the second method is increased because the processing is complicated.

The present invention can prevent degradation of AD conversion accuracy while suppressing an increase in circuit area and processing time, and can also realize a wide dynamic range and thus high image quality. An object of the present invention is to provide a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic apparatus.

A first aspect of the present invention is a solid-state imaging device capable of expanding a dynamic range by synthesizing a plurality of readout signals, and is arranged corresponding to a pixel unit in which pixels are arranged and a column output of the pixel unit A read unit including a column signal processing unit, wherein the column signal processing unit converts the plurality of read signals read from the pixels and input to an input node from analog signals to digital signals. An analog / digital converter (ADC) that performs (AD) conversion, a level of the input node to which the readout signal read out from the pixel is input, and a preset reference voltage are compared, and the reference voltage is set according to a comparison result A comparison / selection unit that selects an input state of the readout signal read from the pixel to the input node.

A second aspect of the present invention includes a pixel unit in which pixels are arranged, and a readout unit including a column signal processing unit arranged corresponding to a column output of the pixel unit, and the column signal processing unit Includes an analog-to-digital converter (ADC) that converts the plurality of readout signals read from the pixels and input to the input node from analog signals to digital signals, and synthesizes the plurality of readout signals. In the AD conversion of the ADC, the level of the input node to which the readout signal read from the pixel is input and a preset reference are provided. The voltage is compared, and the input state of the read signal read from the pixel to the input node is selected according to the comparison result.

An electronic apparatus according to a third aspect of the present invention includes a solid-state imaging device capable of expanding a dynamic range by combining a plurality of readout signals, and an optical system that forms a subject image on the solid-state imaging device, The solid-state imaging device includes a pixel unit in which pixels are arranged, and a reading unit including a column signal processing unit arranged corresponding to the column output of the pixel unit, and the column signal processing unit includes the column signal processing unit, An analog-to-digital converter (ADC) that converts the plurality of readout signals read from the pixels and input to the input node from analog signals to digital signals by analog-to-digital (AD), and the readout signals read from the pixels The input node of the readout signal read out from the pixel according to the comparison result by comparing the level of the input node inputted with a preset reference voltage Comprising a comparison selector for selecting the input state of the.

According to the present invention, it is possible to prevent the deterioration of AD conversion accuracy while suppressing an increase in circuit area and an increase in processing time, and further, it is possible to realize a wide dynamic range and thus to realize a high image quality. Can do.

FIG. 1 shows an example of a normal pixel readout signal (pixel signal) of a solid-state imaging device (CMOS image sensor) and an uninterrupted pixel readout signal (non-interrupted pixel signal) when a high dynamic range technology is employed. FIG. FIG. 2 is a method for increasing (enlarging) the dynamic range in a solid-state imaging device, and illustrates a method for combining pixel signals without interruption when the number M of readout signals to be combined is 2 (M = 2). It is a figure for doing. FIG. 3 is a diagram illustrating an example of a readout circuit including a new reference level setting function in a normal pixel readout signal (pixel signal) processing system. FIG. 4 is a diagram illustrating an example of a normal pixel readout signal (pixel signal) when a new reference level is applied by the clamp circuit. FIG. 5 is a diagram for explaining a configuration for deleting individual variations generated in the ADC. FIG. 6 is a diagram illustrating an example of a column readout system having a configuration for deleting individual variations corresponding to a pixel readout signal without interruption (a pixel signal without interruption). FIG. 7 is a diagram illustrating an example of a state of AD conversion processing of an uninterrupted pixel readout signal (an uninterrupted pixel signal). FIG. 8 is a block diagram illustrating a configuration example of the solid-state imaging device according to the first embodiment of the present invention. FIG. 9 is a circuit diagram illustrating an example of a pixel according to the first embodiment. FIG. 10 is a diagram for explaining a configuration example of a column output readout system of the pixel unit of the solid-state imaging device according to the embodiment of the present invention. FIG. 11 illustrates an ADC that forms a column output readout system of the pixel unit of the solid-state imaging device according to the first embodiment of the present invention, a comparison / selection unit, a holding unit arranged on the output side of the ADC, and a synthesis process It is a figure which shows the structural example of a part. FIG. 12 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 2 (M = 2). FIG. 13 is a method for increasing (enlarging) the dynamic range in a solid-state imaging device, and a method for combining pixel signals without interruption when the number M of readout signals to be combined is 4 (M = 4). It is a figure for doing. FIG. 14 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 4 (M = 4). FIG. 15 is a diagram illustrating a configuration example of a clamp circuit disposed in an input unit of an ADC that forms a column output readout system of a pixel unit of a solid-state imaging device according to the second embodiment of the present invention. FIG. 16 is a diagram illustrating an operation example of the circuit of FIG. FIG. 17 is a diagram illustrating a configuration example of a clamp circuit and a comparison / selection unit arranged in an input unit of an ADC forming a column output readout system of a pixel unit of a solid-state imaging device according to the third embodiment of the present invention. is there. FIG. 18 is a diagram illustrating an operation example of the circuit of FIG. FIG. 19 illustrates an ADC forming a column output readout system of a pixel unit of a solid-state imaging device according to the fourth embodiment of the present invention, a comparison / selection unit, a holding unit arranged on the output side of the ADC, and a combining process It is a figure which shows the structural example of a part. FIG. 20 is a diagram illustrating an example of the configuration of an electronic apparatus to which the solid-state imaging device according to the embodiment of the present invention is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 8 is a block diagram illustrating a configuration example of the solid-state imaging device according to the first embodiment of the present invention.
In the present embodiment, the solid-state imaging device 10 is configured by, for example, a CMOS image sensor.

As shown in FIG. 8, the solid-state imaging device 10 includes a pixel unit 20 as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, and a horizontal scanning circuit (column scanning circuit) 50. A timing control circuit 60 and a digital signal processor (DSP) unit 70 including a function as a signal synthesis processing unit, for example, are included as main components.
Among these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout unit 80.

In the present embodiment, as will be described in detail later, the solid-state imaging device 10 is configured to be able to expand a dynamic range by synthesizing a plurality (M) of readout signals (pixel signals) read from the pixel unit 20. Yes.

As a method for increasing (enlarging) the dynamic range, the reading unit 80 reads, for example, a plurality of M (for example, M = 2) types of signals having different accumulation times from the same pixel of the image sensor, and outputs the M types of signals. A method of expanding the dynamic range by combining (combining) is applied.
In addition, the reading unit 80 applies a method of expanding a dynamic range by combining (synthesizing) a signal of a low illuminance region obtained by a high sensitivity pixel and a signal of a high illuminance region obtained by a low sensitivity pixel. Is possible.

In this embodiment, the pixel readout signal (pixel signal) PSD when this high dynamic range technology is adopted is a readout reset voltage (reference level of a plurality of M (M = 2, 4,...)). Signal) Vrst and a read signal voltage (signal level signal) Vsig having a plurality of M signal levels.
The pixel readout signal (pixel signal) PSD in this case is processed as a so-called uninterrupted readout signal.

As described above, in this embodiment, an uninterrupted pixel signal PSD includes M reference levels (reference level signals) Vrst and M signal levels (signal level signals) Vsig in one pixel signal PSD. include.
In this embodiment, the arrangement order of the pixel signals PSD without interruption is, for example, the signal level Vsig [after the reference level Vrst [N, M] constituting one output data OD [N, M] is always input first. N, M] are input, and there are a plurality of such restrictions.

The readout unit 80 includes a plurality of column signal processing units arranged corresponding to the column (column) output of the pixel unit 20, and each column signal processing unit converts a plurality of readout signals read from the pixels from analog signals. It includes an ADC (analog-digital converter) that converts AD (analog-digital) into a digital signal.
The readout unit 80 compares the input node [Y] to which each readout signal read from the pixel is input with the level of the input node [Y] and a preset reference voltage [V20], and the comparison result is obtained. And a comparison / selection unit that selects an input state of the read signal read from the pixel to the input node [Y].
The ADC receives the signal level signal Vsig after the reference level signal Vrst is input first, for example.
The comparison / selection unit compares the signal level of the input node [Y] with a preset reference voltage V [20] when a signal of a signal level appears at the input node [Y], and compares According to the result, the input state of the read signal read from the pixel to the input node [Y] is selected.

In this embodiment, as will be described in detail later, when the level of the input node [Y] is higher (or lower) than the reference voltage [V20], the comparison / selection unit reads the current comparison target read signal. A state in which subsequent read signals are continuously input to the input node [Y] is selected, and the subsequent read signals are controlled to be AD conversion targets to be held.
When the level of the input node [Y] is lower (or higher) than the reference voltage V20, the comparison selection unit selects a state in which a subsequent read signal is not input to the input node as the current comparison target read signal, and Control is performed so that the read signal to be compared becomes an AD conversion target to be held.

As will be described later, the ADC includes a clamp unit that fixes a signal of a reference level that is input at least first to the input node [Y] to a clamp level [V10] set in advance according to the clamp signal CLP. It has a clamp circuit.

Hereinafter, after describing the outline of the configuration and functions of each unit of the solid-state imaging device 10, the configuration of the ADC including the clamp circuit, the readout processing related thereto, and the like will be described in detail.

(Configuration of the pixel unit 20 and the pixel PXL)
In the pixel unit 20, a plurality of pixels including photodiodes (photoelectric conversion elements) and in-pixel amplifiers are arranged in a two-dimensional matrix (matrix) of n rows × m columns.

FIG. 9 is a circuit diagram illustrating an example of a pixel according to the present embodiment.

The pixel PXL includes, for example, a photodiode (PD) that is a photoelectric conversion element.
For this photodiode PD, a transfer transistor TG-Tr as a transfer element, a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element, and a select transistor SEL-Tr as a select element Each one.

The photodiode PD generates and accumulates signal charges (electrons here) in an amount corresponding to the amount of incident light.
Hereinafter, a case where the signal charge is an electron and each transistor is an n-type transistor will be described. However, the signal charge may be a hole or each transistor may be a p-type transistor.
This embodiment is also effective when a plurality of photodiodes share each transistor or when a three-transistor (3Tr) pixel that does not have a selection transistor is employed.

The transfer transistor TG-Tr is connected between the photodiode PD and a floating diffusion FD (floating diffusion layer), and is controlled through a control line TG.
The transfer transistor TG-Tr is selected when the control line TG is at the high level (H) and becomes conductive, and transfers the charges (electrons) photoelectrically converted and accumulated by the photodiode PD to the floating diffusion FD.

The reset transistor RST-Tr is connected between the power supply line VRst and the floating diffusion FD, and is controlled through the control line RST.
The reset transistor RST-Tr may be connected between the power supply line VDD and the floating diffusion FD, and may be configured to be controlled through the control line RST.
The reset transistor RST-Tr is selected during the period when the control line RST is at the H level, and becomes conductive, and resets the floating diffusion FD to the potential of the power supply line VRst (or VDD).

The source follower transistor SF-Tr and the selection transistor SEL-Tr are connected in series between the power supply line VDD and the vertical signal line LSGN.
A floating diffusion FD is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled through a control line SEL.
The selection transistor SEL-Tr is selected during the period when the control line SEL is at the H level and becomes conductive. As a result, the source follower transistor SF-Tr serves as a signal path for transmitting a column output pixel readout signal (pixel signal) VSL (PSD) obtained by converting the charge of the floating diffusion FD into a voltage signal corresponding to the charge amount (potential). Output to the vertical signal line LSGN.
In this embodiment, the pixel readout signal (pixel signal) PSD in this case is processed as a so-called uninterrupted readout signal.
For example, the gates of the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in units of rows. Is called.

Since the pixel PXL includes n rows × m columns, the pixel unit 20 includes n control lines SEL, RST, and TG, and m vertical signal lines LSGN.
In FIG. 1, each control line SEL, RST, TG is represented as one row scanning control line.

The vertical scanning circuit 30 drives the pixels through the row scanning control lines in the shutter row and the readout row in accordance with the control of the timing control circuit 60.
In addition, the vertical scanning circuit 30 outputs a row selection signal of a row address of a read row that reads out the signal and a shutter row that resets the charge accumulated in the photodiode PD in accordance with the address signal.

Usually, in the pixel readout operation, a shutter scan is performed by driving by the vertical scanning circuit 30 of the readout unit 80, and then the readout scan is performed.

The readout circuit 40 includes a plurality of column signal processing units (not shown) arranged corresponding to the respective column outputs of the pixel unit 20, and is configured such that column parallel processing can be performed by the plurality of column signal processing units.
The read circuit 40 can be configured to include, for example, an ADC and a memory.

As described above, the column signal processing unit 400 of the readout circuit 40 includes, for example, an ADC 410 that converts the readout signal VSL output from each column of the pixel unit 20 into a digital signal, as shown in FIG.

The horizontal scanning circuit 50 scans the signals processed by the plurality of column signal processing units 400 such as ADCs of the reading circuit 40, transfers them in the horizontal direction, and outputs them to the DSP unit 70.

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

The outline of the configuration and function of each unit of the solid-state imaging device 10 has been described above.
Next, the ADC 410 including the clamp circuit according to the first embodiment, the configuration of the holding unit arranged on the output side of the ADC 410, the composition processing unit, the readout processing related thereto, and the like will be described in detail.

FIG. 11 illustrates an ADC that forms a column output readout system of the pixel unit of the solid-state imaging device according to the first embodiment of the present invention, a comparison / selection unit, a holding unit arranged on the output side of the ADC, and a synthesis process It is a figure which shows the structural example of a part.

FIG. 11 shows one readout system including a column signal processing unit 400 corresponding to one column output of the pixel unit 20 in order to simplify the drawing and facilitate understanding. The readout system including the column signal processing unit 400 corresponding to another column output of the pixel unit 20 has the same configuration.

In the readout system of FIG. 11, the ADC 410 is arranged in each column with respect to the vertical signal line LSGN which is the column output line and signal path of the pixel unit 20, and the AD conversion state of the ADC 410 is selected in parallel with the ADC 410. A comparator 420 constituting a part of the comparison selection unit 430 to be controlled is arranged.
On the output side of the ADC 410, holding units 440-1 and 440-2 for holding the reference level Vrst and the signal level Vsig are arranged via the switches SW440-1 and SW440-2, and further holding units 440-1 and 440- A synthesis processing unit 450 that synthesizes the signals held in 2 is arranged.
Note that the composition processing unit 450 is disposed in the DSP unit 70, for example.

The ADC 410 includes an input node [Y], an input switch (S) 411, a clamp circuit 412, and a conversion unit 413 as main components.

The ADC 410 AD converts a plurality of readout signals read from the pixel PXL and input to the input node [Y] from analog signals to digital signals.

As described above, each of the plurality of readout signals is formed by a reference level signal and a signal level signal, and the ADC 410 receives the signal level signal Vsig after the reference level signal Vrst is input first. The

The input switch 411 includes a connection state (on state) and a non-connection state (off state) of the signal path to the input node [Y] of the readout signal read from the pixel PXL in accordance with the signal S420 indicating the comparison result of the comparator 420. Switch status).
The input switch 411 and the comparator 420 constitute a comparison / selection unit 430.

The clamp circuit 412 includes a clamp unit 412A that fixes a reference level signal Vrst input at least first to the input node [Y] to a clamp level [V10] set in advance according to the clamp signal CLP.
As shown in FIG. 3, the clamp circuit 412 includes an amplifier AMP1, capacitors C1 and C2, and a switch SW1.
A clamp circuit 412 in FIG. 11 is illustrated by simplifying the clamp circuit in FIG. 3 with a capacitor C11 and a switch SW11, and the clamp unit 412A includes the capacitor C11 and the switch SW11.

In the ADC 410, the clamp circuit 412 turns on the switch SW11 with the clamp signal CLP, thereby changing the reference level Vrst appearing at the node [Y] using the new reference level [V10].
At this time, the signal level Vsig [N] becomes a new signal level Vsig [N ′] based on the new reference level [V10].
In this case, the difference between the reference level [V10] and the signal level Vsig [N ′] is constant.

The conversion unit 413 AD converts a plurality of read signals read from the pixel PXL and input to the input node [Y] from analog signals to digital signals.

The comparator 420 constitutes a comparison / selection unit 430 together with the input switch 411.
The comparator 420 included in the comparison / selection unit 430 includes a signal level of the input node [Y] and a preset reference voltage [V20] when the signal level signal Vsig appears at the input node [Y]. The input switch 411 is switched on and off so as to select the input state of the read signal read from the pixel to the input node [Y] by the signal S420 corresponding to the comparison result.

In this embodiment, the reference voltage [V20] is a level (for example, the coupling position X in FIG. 2B) corresponding to the coupling position of a plurality of readout signals to be synthesized.

For example, when the level of the input node [Y] is higher than the reference voltage [V20], the comparison / selection unit 430 continuously inputs the read signal subsequent to the current comparison target read signal to the input node [Y]. Is selected and control is performed so that the subsequent read signal becomes an AD conversion target to be held.
In this case, the output signal S420 of the comparator 420 is “1”, for example, and the input switch 411 is controlled to be in an on state (connected state).

For example, when the level of the input node [Y] is lower than the reference voltage V20, the comparison selection unit 430 selects a state in which a subsequent read signal is not input to the input node [Y] as the current comparison target read signal. Control is performed so that the current comparison target read signal becomes the AD conversion target to be held.
In this case, the output signal S420 of the comparator 420 is “0”, for example, and the input switch 411 is controlled to be in an off state (non-connected state).

The holding units 440-1 and 440-2 are connected in parallel to the output of the ADC 410 via the switches SW 440-1 and SW 440-2, and a reference level signal or a signal level signal AD-converted by the ADC 410 is selected. Retained,
At least one of the holding units 440-1 and 440-2 is configured to be overwritten while the ADC 410 performs AD conversion processing.
Note that the number of holding units is set to a number corresponding to a number smaller than 2M, which is twice the number of read signals to be combined. In this embodiment, the minimum two holding units 440-1 and 440-2 are arranged.

The synthesis processing unit 450 generates output data OD by synthesizing the digital signals held in the plurality of holding units 440-1 and 440-2.

FIG. 12 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 2 (M = 2).
Here, the operation of the circuit in FIG. 11 when the number M of read signals to be combined is 2 (M = 2) will be described with reference to FIG.

In this case, the pixel read signal (pixel signal) PSD [N] without interruption is M (M = 2 in this example) reference level Vrst in one pixel signal PSD [N] as shown in FIG. [N, 1], Vrst [N, 2] and M signal levels Vsig [N, 1], Vsig [N, 2].
That is, in one uninterrupted pixel signal PSD [N], M reference levels Vrst [N, 1], Vrst [N, 2] and M signal levels Vsig [N, 1], Vsig [N , 2].
Similarly, in one uninterrupted pixel signal PSD [N + 1], M reference levels Vrst [N + 1, 1], Vrst [N + 1, 2] and M signal levels Vsig [N + 1, 1], Vsig [ N + 1, 2].

As described above, the pixel signal PSD without interruption includes M reference levels Vrst and M signal levels Vsig in one pixel signal PSD, and the arrangement order is one output data OD [N , M], a plurality of reference levels Vrst [N, M] must be input first and then the signal level Vsig [N, M] is input.

In the example of FIG. 12, two reference levels Vrst [N, 1] and Vrst [N, 2] are input to the uninterrupted pixel signal PSD [N], and then two signal levels Vsig [N, 1], Vsig [N, 2] are input.
Similarly, in one uninterrupted pixel signal PSD [N + 1], two signal levels Vsig [N + 1,1] are input after two reference levels Vrst [N + 1,1] and Vrst [N + 1,2] are input. ], Vsig [N + 1, 2] are input.

As described above, in the pixel signal PSD [N] without interruption, first, the reference levels Vrst [N, 1] and Vrst [N, 2] are input first. The comparator 420 is in a reset state without performing comparison processing, and its output is “1”.
As a result, the input switch 411 of the ADC 410 is held in the on state (connected state).

In this state, in the ADC 410, the first input reference level Vrst [N, 1] is transmitted to the input node [Y] via the input switch 411. In the ADC 410, the reference level Vrst appearing at the node [Y] is changed using the new reference level [V10] by turning on the switch SW11 of the clamp circuit 412 by the clamp signal CLP.
At this time, the signal level Vsig [N] becomes a new signal level Vsig [N ′] based on the new reference level [V10].
In this case, the difference between the reference level [V10] and the signal level Vsig is constant.

In the ADC 410, the reference level Vrst [N] of the level V10 appearing at the input node [Y] is converted from an analog signal to a digital signal by the conversion unit 413 (first AD conversion (ADCNV) -1).
The digital signal is written and held in the holding unit 440-1 via, for example, the switch SW440-1.

Next, in the ADC 410, the input switch 411 is held in the ON state, and the reference level Vrst [N, 2] is input to the input node [Y].
In the ADC 410, the reference level Vrst [N, 2] that appears subsequently at the input node [Y] is converted from an analog signal to a digital signal by the conversion unit 413 (second AD conversion (ADCNV) -2).
The digital signal is written and held in the holding unit 440-2 through the switch SW440-2, for example.

Next, in the ADC 410, the signal level Vsig [N, 1] is input to the input node [Y] while the input switch 411 is held in the on state.
Here, since the signal level Vsig appears at the input node [Y] of the ADC 410, the signal level Vsig [N] appearing at the input node [Y] and the reference voltage [N] in the comparator 420 of the comparison / selection unit 430. V20] and the input switch 411 is controlled to be turned on / off by a signal S420 indicating the result.

When the input switch 411 is kept on, the signal level Vsig of the pixel signal PSD continues to appear at the input node [[Y]. When the input switch 411 is selected to be off, the input node [Y] Holds the state of the input node [Y] as it is.

The above processing is similarly performed for a pixel signal [N + 1] following the pixel signal PSD [N]. Therefore, the detailed description is abbreviate | omitted.

In the pixel signal PSD [N] in the example of FIG. 12, since the signal level Vsig [N, 1] input to the input node [Y] is higher than the reference voltage [V20], AD of the signal level Vsig [N, 1] The conversion result becomes unnecessary.
That is, in the example of the pixel signal PSD [N] in FIG. 12, the input switch 411 remains in the ON state, and the signal level Vsig [N, 2] is input subsequently to the signal level Vsig [N, 1]. The signal level Vsig [N, 2] is the target of the third AD conversion (ADCNV) -3.

In this case, since the AD conversion result of the signal level Vsig [N, 1] is unnecessary, the reference level Vrst [N, 1] paired therewith is not required. As a result, the digital reference level Vrst [N, 1] already held in the holding unit 440-1 becomes unnecessary.
Therefore, in the circuit of FIG. 11, the signal level Vsig [N, 2] converted into a digital signal by the conversion unit 413 is overwritten and held in the holding unit 440-1 via, for example, the switch SW440-1.

Further, in the pixel signal PSD [N + 1] in the example of FIG. 12, since the signal level Vsig [N + 1, 1] input to the input node [Y] is lower than the reference voltage [V20], the output signal S420 of the comparator 420 is It becomes “0”, and the input switch 411 is controlled to be in the OFF state. As a result, the AD conversion result of the signal level Vsig [N + 1, 1] subsequent to the signal level Vsig [N + 1, 1] becomes unnecessary.
That is, in the example of the pixel signal PSD [N + 1] in FIG. 12, the input switch 411 is turned off, the signal level Vsig [N + 1, 1] is continuously held at the input node [Y], and the signal level Vsig [N + 1, 1] is the target of the third AD conversion (ADCNV) -3.

In this case, the AD conversion result of the signal level Vsig [N + 1, 2] is unnecessary, and therefore, the reference level Vrst [N + 1, 2] paired therewith is unnecessary. As a result, the digital reference level Vrst [N + 1, 2] already held in the holding unit 440-2 becomes unnecessary.
Therefore, in the circuit of FIG. 11, the signal level Vsig [N + 1, 1] converted into a digital signal by the conversion unit 413 is overwritten and held in the holding unit 440-2 via the switch SW440-2, for example.

As described above, according to the circuit of FIG. 11 according to the present embodiment, the AD conversion operation that is conventionally required four times is performed three times, and the number of holding units 440 is basically changed from four to three.
At this time, other than the reference level that is paired with the signal level selected for the third AD conversion (ADCNV) -3 is not necessary. By overwriting 440-1 or 440-2, the number of holding units becomes two.
That is, according to the circuit of FIG. 11 according to the present embodiment, the number of holding units is not increased, and a minimum of two can be reduced.

The operation of the circuit in FIG. 11 when the number M of read signals to be combined is 2 (M = 2) has been described above with reference to FIG.
The present invention can be applied not only when the number M of read signals to be combined is 2 (M = 2) but also when combining a larger number of read signals, for example, 4 (M = 4). .

FIGS. 13A and 13B show a method for increasing (enlarging) the dynamic range in a solid-state imaging device, and a pixel without interruption when the number M of readout signals to be combined is 4 (M = 4). It is a figure for demonstrating the synthetic | combination processing method of a signal.

The uninterrupted pixel signal PSD can have different amplification factors K for M (= 4) signals for the same light quantity.
FIGS. 13A and 13B show that M = 4 and the ratio of amplification factors K (1) / K (2) = 2, the ratio K (1) / K (3) = 3, and the ratio K (1 ) / K (4) = 4.

Similar to the example of FIG. 2, the output data OD [*, 1], OD [*, 2], OD [*, 3], OS [*, 4] obtained by the uninterrupted pixel signal PSD are shown in FIG. Signals having different characteristics as shown in FIG.
In the synthesizing process, the output data OD [*, 2], OD [*, 3], OS [*, 4] are amplified according to the ratio, and one synthesized as shown in FIG. The final output data ODA is obtained.

At this time, as shown in FIG. 13B, the coupling position (point) [X] becomes three points [X1], [X2], and [X3].
[X1] indicates a connection point between the output data OD [*, 1] and OD [*, 2], [X2] indicates a connection point between the output data OD [*, 2] and OD [*, 3], [X3] indicates a connection point between the output data OD [*, 3] and OD [*, 4].
Accordingly, the reference voltage [V20] is set to [V20   1], [V20   2], [V20   3].

FIGS. 14A and 14B are diagrams for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 4 (M = 4).
FIG. 14A shows a case where the signal level Vsig [N, 2] is selected as the target of the third AD conversion (ADCNV) -3. FIG. 14B shows the case where the signal level Vsig [N, 3] is selected as the target of the third AD conversion (ADCNV) -3.

Here, the operation of the circuit in FIG. 11 when the number M of read signals to be combined is 4 (M = 4) will be described with reference to FIGS. 14 (A) and 14 (B).
However, since the processing for the reference level Vrst is basically the same as the case of FIG. 12, the processing for the signal level Vsig will be mainly described.

In the examples of FIGS. 14A and 14B, the arrangement order is such that the arrangement of M = 2 is repeated twice, and a pixel signal PSD [N] without interruption of M = 4 is formed.
14A and 14B, the comparator operations in the comparator 420 of the comparison / selection unit 430 are the signal levels Vsig [N, 1], Vsig [N, 2], Vsig [N, 3 ] Is performed.

The example of FIG. 14A is a case where the signal level Vsig [N, 2] is selected as the target of the third AD conversion-3 as described above.
In this case, in the comparator 420, the first comparison operation is performed at the signal level Vsig [N, 1] and the reference voltage [V20_1].
In the example of FIG. 14A, since the signal level Vsig [N, 1] is higher than the reference voltage [V20_1], the AD conversion result of the signal level Vsig [N, 1] becomes unnecessary.
That is, in the example of the pixel signal PSD [N] in FIG. 14A, the signal level Vsig [N, 2] is input subsequent to the signal level Vsig [N, 1] while the input switch 411 remains on. The

In the comparator 420, the second comparison operation is performed at the signal level Vsig [N, 2] and the reference voltage [V20_2].
In the example of FIG. 14A, since the signal level Vsig [N, 2] is lower than the reference voltage [V20_2], all subsequent signal processing is unnecessary.
That is, the input switch 411 is held in the OFF state, the signal level Vsig [N, 2] is held at the input node [Y] until the third AD conversion-3, and the conversion operation is performed by the conversion unit 413.

Hereinafter, this operation will be considered in association with the holding unit.
As described in the example of FIG. 12, the holding unit 440-1 temporarily holds the reference level Vrst [N, 1], and the holding unit 440-2 holds the reference level Vrst [N, 2]).
However, since the signal level Vsig [N, 2] is selected as the target of the third AD conversion-3 by the second comparison operation, the reference level Vrst [N, 1] held in the holding unit 440-1 is unnecessary. become.
As a result, the holding unit 440-1 is overwritten with the signal level Vsig [N, 2] by the third AD conversion-3.

The example of FIG. 14B is a case where the signal level Vsig [N, 3] is selected as the target of the third AD conversion-3 as described above.
In this case, in the comparator 420, the signal level Vsig is higher than the reference voltages [V20_1] and [V20_2] in the first and second comparison operations, and thus the input switch 411 is held in the on state.
In the comparator 420, the third comparison operation is performed with the signal level Vsig [N, 3] and the reference voltage [V20_3].
In the example of FIG. 14B, since the signal level Vsig [N, 3] is lower than the reference voltage [V20_3], all subsequent signal processing becomes unnecessary.
That is, the input switch 411 is held in the OFF state, the signal level Vsig [N, 3] is held at the input node [Y] until the third AD conversion-3, and the conversion operation is performed by the conversion unit 413.

Hereinafter, this operation will be considered in association with the holding unit.
When the switch 411 remains on by the first and second comparison operations, the reference levels Vrst [N, 1] and Vrst [N, 2] temporarily held in the holding units 440-1 and 440-2 Is no longer necessary.
That is, the holding unit 440-1 is overwritten with the reference level Vrst [N, 3], and the holding unit 440-2 is overwritten with the reference level Vrst [N, 4].
Since the signal level Vsig [N, 3] is selected as the target of the third AD conversion-3 by the third comparison operation, the reference level Vrst [N, 4] held and stored in the holding unit 440-2 becomes unnecessary. Become.
That is, the holding unit 440-2 is overwritten with the signal level Vsig [N, 3] by the third AD conversion-3.
As a result, even when the number of uninterrupted pixel signals formed by the expansion of repeating the M = 2 array is M, the number of holding units remains two. That is, there is no increase in the holding portion.

As described above, according to the first embodiment, the reading unit 80 includes the comparator 420 that constitutes the ADC 410 and the comparison / selection unit 430.
The comparison selection unit 430 compares the signal level of the input node [Y] with a preset reference voltage [V20] when the signal level signal Vsig appears at the force node [Y], and the comparison result In response to the signal S420, the input switch 411 is switched on and off so as to select the input state of the readout signal read from the pixel to the input node.
Specifically, when the level of the input node [Y] is higher than the reference voltage [V20], the comparison / selection unit 430 receives the subsequent read signal continuously from the read signal to be compared to the input node [Y]. The state to be input to is selected, and control is performed so that the subsequent read signal becomes the AD conversion target to be held.
When the level of the input node [Y] is lower than the reference voltage [V20], the comparison selection unit 430 selects a state in which the subsequent readout signal is not input to the input node [Y] as the readout signal to be compared. Then, control is performed so that the current comparison target read signal becomes the AD conversion target to be held.

Therefore, according to the first embodiment, it is possible to cope with M uninterrupted pixel signals with 2 or more holding units less than 2M, and to perform AD conversion operation less than 2M times. It is possible to suppress an increase in circuit area and an increase in processing time.
Further, the comparison operation using the reference voltage [V20] can prevent the boundary from being emphasized by its own analog noise, and prevents the deterioration of the AD conversion accuracy while suppressing an increase in circuit area and an increase in processing time. It becomes possible.

That is, according to the first embodiment, it is possible to prevent the deterioration of the AD conversion accuracy while suppressing an increase in circuit area and an increase in processing time, and it is possible to realize a wide dynamic range. It becomes possible to realize image quality.

(Second Embodiment)
FIG. 15 is a diagram illustrating a configuration example of a clamp circuit disposed in an input unit of an ADC that forms a column output readout system of a pixel unit of a solid-state imaging device according to the second embodiment of the present invention.
FIG. 15 shows an example in which the input stage of the clamp circuit is extracted, and the clamp circuit 412B is not simplified and is shown as an example including an amplifier AMP11, capacitors C11 and C12, and a switch SW11. .
FIG. 16 is a diagram illustrating an operation example of the circuit of FIG.

The reading system of the second embodiment is different from the reading system of the first embodiment as follows.
The readout system of the second embodiment basically has two clamp circuits.
In the second embodiment, an example in which no comparison / selection unit is provided is shown. However, it is also possible to provide a comparison / selection unit 430 as in a third embodiment described later.

In the clamp circuit 412B, the amplifier AMP11, the capacitor C12, and the switch SW11 are shared to form a clamp unit 412A, and only the path selection switches 462-1 and 462-2 and the capacitors C11-1 and C11-2 are added. Is provided.
As a result, an increase in circuit area is suppressed.

In the circuit of FIG. 15, a path selection unit 460 is disposed on the input side of the clamp unit 412A of the clamp circuit 412B.
The path selection unit 460 selects a plurality of signal paths 461-1 [A] and 461-2 [B] through which each of a plurality (2 in this example) of readout signals to be combined read from the pixel PXL is individually transmitted. In addition, a read signal transmitted through any one of the signal paths 461-1 and 461-2 is supplied to the clamp unit 412A according to the path selection signal.
The route selection unit 460 is disposed in each of the signal routes 461-1 [A] and 461-2 [B], and the connection state of the signal routes 461-1 and 461-2 according to the corresponding route selection signals WA and WB. A plurality of route selection switches 462-1 and 462-2 for switching the non-connected state are included.
A capacitor C11-1 is arranged in the signal path 461-1, and a capacitor C11-2 is arranged in the signal path 461-2.

The clamp circuit 412B in FIG. 15 is connected to the input node [Y] through the signal path 461-1 [A] or 461-2 [B] by the path selection signals WA and WB.
As a result, the two reference levels are held through the signal path 461-1 [A] or 461-2 [B], respectively, so that AD conversion can be performed with high accuracy even for a pixel signal without interruption.

(Third embodiment)
FIG. 17 is a diagram illustrating a configuration example of a clamp circuit and a comparison / selection unit arranged in an input unit of an ADC forming a column output readout system of a pixel unit of a solid-state imaging device according to the third embodiment of the present invention. is there.
FIG. 17 shows an example in which the input stage of the clamp circuit is extracted, and the clamp circuit 412C shows the clamp unit 412A in a simplified manner as in FIG.
FIG. 18 is a diagram illustrating an operation example of the circuit of FIG.

The read system of the third embodiment is different from the read system of the second embodiment as follows.
In the readout system of the third embodiment, the comparison / selection unit 430 described in the first embodiment is arranged, and the output signal S420 of the comparator 420 of the comparison / selection unit 430 and the path selection signals WA and WB are obtained. In association therewith, the path selection switches 462-1 and 462-2 are switched on and off (connected state and non-connected state).

In the third embodiment, the path selection switch and the input switch are shared, and the shared switches 462-1 and 462-2 indicate the comparison result of the comparator and the state of the corresponding path selection signals WA and WB. The connection state and the non-connection state are switched in association.

In the example of FIG. 17, the route selection signals WA and WB necessary for route selection are ANDed with the outputs of the comparators 420 in AND gates 470-1 and 470-2, and AND gates 470-1 and 470-2. The path selection switches 462-1 and 462-2 that also have the function of the input switch are controlled by the output of.

In the circuit of FIG. 17, as shown in FIG. 18, when the output signal S420 of the comparator 420 is “1”, the path selection signals WA and WB are valid, and the state of the input node [Y] itself is obtained.
However, since the output signal S420 of the comparator 420 becomes “0” at the signal level Vsig [N + 1, 2], the immediately subsequent path selection signal WB becomes invalid.
That is, the signal level Vsig [N + 1, 1] is held at the input node [Y].

According to the third embodiment, the same effects as those of the first and second embodiments described above can be obtained.

(Fourth embodiment)
FIG. 19 illustrates an ADC forming a column output readout system of a pixel unit of a solid-state imaging device according to the fourth embodiment of the present invention, a comparison / selection unit, a holding unit arranged on the output side of the ADC, and a combining process It is a figure which shows the structural example of a part.

The difference between the read system of the fourth embodiment and the read system of the first embodiment is that the level of the reference voltage [V20] can be changed with time.

The simplest method for combining a plurality of read signals is the first method shown in FIG.
However, when the configuration according to FIG. 11 is used, the combination point [X] of a plurality of read signals is determined by the reference voltage [V20].
That is, the state in which the reference voltage [V20] changes with time is equivalent to changing the coupling point [X], and the emphasis on the boundary can be relaxed.

FIG. 19 shows a configuration example for changing the reference voltage [V20] with time.
In the example of FIG. 19, as the reference voltage [V20], voltage waveforms [V20_A], [V20_B], and [V20_C] can be selected through the switches 480-1, 480-2, and 480-3.
[V20_A] is a sine wave, [V20_B] is a square wave having a plurality of levels, and [V20_C] is a noise waveform.
Each waveform is centered on the level of the reference voltage [V20] originally required.

According to the fourth embodiment, not only can the same effect as in the first embodiment described above be obtained, but also the boundary due to analog noise can be not emphasized, and as a result, the boundary is not emphasized. Complex signal processing becomes unnecessary, and it becomes possible to suppress an increase in circuit area and an increase in processing time.

The solid-state imaging device 10 described above can be applied as an imaging device to an electronic apparatus such as a digital camera, a video camera, a portable terminal, a monitoring camera, or a medical endoscope camera.

FIG. 20 is a diagram illustrating an example of a configuration of an electronic device equipped with a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

As shown in FIG. 20, the electronic apparatus 100 includes a CMOS image sensor 110 to which the solid-state imaging device 10 according to the present embodiment can be applied.
The electronic device 100 further includes an optical system (lens or the like) 120 that guides incident light (forms a subject image) to the pixel region of the CMOS image sensor 110.
The electronic device 100 includes a signal processing circuit (PRC) 130 that processes an output signal of the CMOS image sensor 110.

The signal processing circuit 130 performs predetermined signal processing on the output signal of the CMOS image sensor 110.
The image signal processed by the signal processing circuit 130 can be displayed as a moving image on a monitor composed of a liquid crystal display or the like, or output to a printer, or directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-described solid-state imaging device 10 as the CMOS image sensor 110, it is possible to provide a high-performance, small, and low-cost camera system.
Electronic devices such as surveillance cameras and medical endoscope cameras are used for applications where the camera installation requirements include restrictions such as mounting size, number of connectable cables, cable length, and installation height. Can be realized.

DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device, 20 ... Pixel part, 30 ... Vertical scanning circuit, 40 ... Reading circuit, 410 ... ADC, 411 ... Input switch, 412, 412B, 412C ... · Clamp circuit, 412A ... Clamping unit, 413 ... Conversion unit, 420 ... Comparator, 430 ... Comparison selection unit, 440-1, 440-2 ... Holding unit, 450 ... Synthesis processing unit, 460... Route selection unit, 461-1, 461-2 ... signal route, 462-1, 462-2 ... route selection switch, 470-1, 470-2 ... AND Gates, 480-1, 480-2, 480-3 ... switches, 50 ... horizontal scanning circuit, 60 ... timing control circuit, 70 ... DSP unit, 80 ... reading unit, 100. ..Electronic equipment, 110 ... C OS image sensor, 120 ... optical system, 130 ... signal processing circuit (PRC).

Claims (14)

1. A solid-state imaging device capable of expanding a dynamic range by combining a plurality of readout signals,
   A pixel portion in which pixels are arranged;
   A readout unit including a column signal processing unit arranged corresponding to the column output of the pixel unit,
   The column signal processor is
   An analog-to-digital converter (ADC) that converts the plurality of readout signals read from the pixels and input to an input node from analog signals to digital signals;
   The level of the input node to which the read signal read from the pixel is input is compared with a preset reference voltage, and the input node of the read signal read from the pixel according to a comparison result A comparison / selection unit that selects an input state to the solid-state imaging device.
2. The comparison / selection unit includes:
   When the level of the input node is higher or lower than the reference voltage, a state in which a subsequent read signal is continuously input to the current comparison target read signal is selected and the subsequent read signal is selected. Control to be AD conversion target to be retained,
   When the level of the input node is lower or higher than the reference voltage, a state in which a subsequent read signal is not input to the input node is selected as the read signal to be compared, and the read signal to be currently compared is held. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is controlled so as to be an AD conversion target.
3. Each of the plurality of read signals is formed by a reference level signal and a signal level signal,
   The ADC is
   The signal of the signal level is input after the signal of the reference level is input first,
   The comparison / selection unit includes:
   When the signal level signal appears at the input node, the signal level of the input node is compared with a preset reference voltage, and the readout signal read from the pixel according to the comparison result The solid-state imaging device according to claim 1, wherein an input state to the input node is selected.
4. A reference level signal or a signal level signal that is connected in parallel to the output of the ADC and AD-converted by the ADC is selectively held. A small number of holding parts,
   The solid-state imaging device according to claim 3, further comprising: a synthesis processing unit that generates output data by synthesizing digital signals held in the plurality of holding units.
5. At least one of the holding parts is
   The solid-state imaging device according to claim 4, wherein the ADC can be overwritten during AD conversion processing.
6. The ADC is
   The solid-state imaging device according to claim 3, further comprising: a clamp circuit including a clamp unit that fixes a signal of a reference level that is input at least first to the input node to a clamp level that is set in advance according to a clamp signal.
7. The clamp circuit is on the input side of the clamp unit,
   Each of the plurality of readout signals to be combined read out from the pixels includes a plurality of signal paths that are individually transmitted, and the readout signal transmitted through any one of the signal paths according to a path selection signal is clamped. The solid-state imaging device according to claim 6, further comprising a path selection unit that supplies the unit.
8. The route selection unit
   The solid-state imaging device according to claim 7, further comprising: a plurality of path selection switches that are arranged in the signal paths and switch a connection state and a non-connection state of the signal path according to a corresponding path selection signal.
9. The comparison / selection unit includes:
   A comparator that compares the level of the input node with a preset reference voltage;
   The solid-state imaging device according to claim 1, further comprising: an input switch that switches a connection state and a non-connection state of a signal path to the input node of the readout signal read from the pixel according to a comparison result of the comparator. .
10. The route selection unit
    A plurality of path selection switches that are arranged in each signal path and switch a connection state and a non-connection state of the signal path according to a corresponding path selection signal;
    The comparison / selection unit includes:
    A comparator that compares the level of the input node with a preset reference voltage;
    An input switch for switching a connection state and a non-connection state of a signal path to the input node of the readout signal read from the pixel according to a comparison result of the comparator;
    8. The path selection switch and the input switch are shared, and the shared switch is switched between a connection state and a non-connection state in association with a comparison result of the comparator and a state of the corresponding path selection signal. Solid-state imaging device.
11. The reference voltage is
    The solid-state imaging device according to claim 1, wherein the level corresponds to a combination position of a plurality of readout signals to be synthesized.
12. The solid-state imaging device according to claim 11, wherein the reference voltage can change the level with time.
13. A pixel portion in which pixels are arranged;
    A readout unit including a column signal processing unit arranged corresponding to the column output of the pixel unit,
    The column signal processor is
    An analog-to-digital converter (ADC) that performs analog-to-digital (AD) conversion of the plurality of readout signals read from the pixels and input to the input node from analog signals to digital signals;
    A driving method of a solid-state imaging device capable of expanding a dynamic range by combining a plurality of readout signals,
    In the AD conversion of the ADC,
    Comparing the level of the input node to which the readout signal read from the pixel is input and a preset reference voltage,
    A method for driving a solid-state imaging device, wherein an input state of the readout signal read from the pixel to the input node is selected according to a comparison result.
14. A solid-state imaging device capable of expanding a dynamic range by combining a plurality of readout signals;
    An optical system that forms a subject image on the solid-state imaging device,
    The solid-state imaging device
    A pixel portion in which pixels are arranged;
    A readout unit including a column signal processing unit arranged corresponding to the column output of the pixel unit,
    The column signal processor is
    An analog-to-digital converter (ADC) that converts the plurality of readout signals read from the pixels and input to an input node from analog signals to digital signals;
    The level of the input node to which the read signal read from the pixel is input is compared with a preset reference voltage, and the input node of the read signal read from the pixel according to the comparison result And a comparison / selection unit for selecting an input state of the electronic device.

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