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WO2017181778A1 - 一种双主控设备主控之间链路扩展方法及装置 - Google Patents

一种双主控设备主控之间链路扩展方法及装置 Download PDF

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Publication number
WO2017181778A1
WO2017181778A1 PCT/CN2017/075763 CN2017075763W WO2017181778A1 WO 2017181778 A1 WO2017181778 A1 WO 2017181778A1 CN 2017075763 W CN2017075763 W CN 2017075763W WO 2017181778 A1 WO2017181778 A1 WO 2017181778A1
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WIPO (PCT)
Prior art keywords
master
line card
link
proxy
standby
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PCT/CN2017/075763
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English (en)
French (fr)
Inventor
郭宇
Original Assignee
中兴通讯股份有限公司
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Publication of WO2017181778A1 publication Critical patent/WO2017181778A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications
    • H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports

Definitions

  • the present application relates to, but is not limited to, the field of communications, and more particularly to a method and apparatus for link extension between dual master devices.
  • the main control board functions as a hub.
  • the modules involved include multiple management cores, service planes, and control planes.
  • the master master is the master currently working, and the standby master is the master used to back up the current module information.
  • each module of the standby master requires real-time "mastery" of the information of the corresponding module working in the active master, that is, data synchronization between the dual masters. This data may come from peripherals (such as hard drives, flash (Flash), SD (Secure Digital Memory Card), etc.) or from memory/cache.
  • the standby master immediately transitions to the active master, and each module starts working according to the data that was previously synchronized. If the hot backup data is not complete at this time, it affects the stable operation of the device service. Therefore, the accuracy and real-time nature of data synchronization between dual masters is critical.
  • each equipment supplier mostly uses two direct-connected high-speed buses to complete the communication between the dual masters.
  • the two communication links may still have a certain degree of link anomaly, and the number of ports controlled by the master switching chip cannot be more straight. Connected to the link. Even with the further reduction of hardware costs and the increase in the number of switch chip ports, more direct links can be added to the new devices.
  • more direct links can be added to the new devices.
  • how to ensure the accuracy and real-time performance of data synchronization between the dual masters of the old devices is still The main problem currently facing.
  • the accuracy and real-time performance of data synchronization between the dual master devices of the old device can be improved.
  • the method for extending the link between the main control devices of the dual-master device includes the main control, the standby main control, and the line card, and the method includes:
  • a line card is selected as a proxy exchange line card for data synchronization
  • the direct link When it is detected that an abnormality occurs in the direct link, the direct link is disabled, and the data exchange between the primary master and the standby master is implemented by the proxy switching line card.
  • the step of selecting a line card as a proxy exchange line card for data synchronization includes:
  • the line card with the smallest determined service configuration is used as the proxy exchange line card.
  • the step of disabling the direct link includes:
  • the switch chip port of the standby master directly connected to the active master is disabled.
  • the step of implementing data synchronization between the primary master and the standby master by using the proxy switch line card includes:
  • the port connected to the primary master by the proxy switch line card receives synchronization data from the active master, and the port connected to the standby master by the proxy switch line card will synchronize the data. Forward to the alternate master.
  • the method further includes:
  • another line card is selected as a new proxy exchange.
  • a line card to enable data synchronization between the primary master and the standby master via the new proxy switch line card.
  • the method further includes:
  • the direct link When the direct link is detected to be normal, the direct link is enabled to implement data synchronization between the primary master and the standby master.
  • a storage medium stores a program for implementing a link extension method between the dual master device masters.
  • a link extension device between two main control devices includes an active main control, a standby main control, and a line card, and the device includes:
  • a proxy selection module configured to select a line card as a proxy exchange line card for data synchronization during data synchronization using a direct link between the primary master and the standby master;
  • a link detection module configured to detect a direct link between the primary master and the standby master
  • a data synchronization module configured to disable the direct link when the link detection module detects that the direct link is abnormal, and exchange the line card through the proxy to implement the primary master and Data synchronization between the alternate masters.
  • the proxy selection module is configured to sort the service configuration quantity of the line card of the dual master device, determine a line card with the least amount of service configuration, and minimize the determined service configuration amount.
  • the card acts as a proxy exchange line card.
  • the link detecting module is further configured to: perform, by using the proxy switch line card, a communication link for implementing data synchronization between the active master and the standby master
  • the agent selection module is further configured to: when the link detection module detects that the communication link is abnormal, select another line card as a new proxy exchange line card, so that the data synchronization module passes the The new proxy exchange line card implements data synchronization between the active master and the standby master.
  • the data synchronization module is further configured to: when the link detection module detects that the direct link is normal, enable the direct link to implement the active master and the host The data synchronization between the alternate masters is described.
  • a computer readable storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the link extension method between the dual master device masters is implemented.
  • the link between the dual masters can be made through the link between the master control and the line card without changing the physical link between the dual master (ie, the primary master and the standby master). Effectively expanded to ensure that data synchronization between the two masters is normal.
  • FIG. 1 is a block diagram of a method for link extension between main control devices of a dual master device according to an embodiment of the present invention
  • FIG. 2 is a block diagram of a link extension device between main control devices of a dual master device according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a system communication link of a dual master device according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of forwarding, by the line card CPU, synchronization data after an abnormality occurs in the direct link 1 of the dual master control according to the embodiment of the present invention
  • FIG. 5 is a schematic diagram of forwarding synchronization data by a line card switching chip after an abnormality occurs in the direct link 1 of the dual master control according to an embodiment of the present invention
  • FIG. 6 is a flowchart of an operating system of a switch chip port after an abnormality occurs in the direct link 1 of the dual master control according to the embodiment of the present invention
  • FIG. 7(a) is a schematic diagram of a path of a keepalive detection packet when a communication link alarm detection point is transferred between a main control and a line card according to an embodiment of the present invention
  • FIG. 7(b) is a schematic diagram of a path for supporting a three-layer communication between a main control and a line card, and a keep-alive detection message when a communication link alarm detection point is transferred according to an embodiment of the present invention
  • FIG. 8 is a flowchart of a system for reporting an alarm on an active main control in the case of a new link abnormality according to an embodiment of the present invention (the MUX represents an allowable number of times that a keep-alive detection message is not received).
  • the dual-master device includes an active main control, a standby main control, and a line card. As shown in FIG. 1 , the steps include:
  • Step S101 During data synchronization using the direct link between the primary master and the standby master, one line card is selected as the proxy exchange line card for data synchronization.
  • the service configuration quantity of the line card of the dual-master device is sorted, the line card with the smallest service configuration quantity is determined, and the line card with the determined service configuration quantity is minimized as the proxy exchange line card.
  • Step S102 detecting a direct link between the primary master and the standby master.
  • Step S103 When it is detected that an abnormality occurs in the direct link, the direct link is disabled, and the line card is exchanged by the proxy to form an extended communication link between the primary master and the standby master, thereby utilizing the extended The communication link realizes data synchronization between the primary master and the standby master.
  • the switch chip port directly connected to the standby master is disabled, and the switch chip port of the standby master directly connected to the active master is disabled, thereby Disable the direct link.
  • the dual masters forward the synchronous data through the proxy exchange line card.
  • the active master sends the synchronous data to the proxy exchange line card through the port connected to the proxy exchange line card, and the proxy exchange line card communicates with the active owner through the port.
  • the control-connected port receives the synchronization data from the active master and forwards the synchronized data to the standby master via its port connected to the standby master.
  • the proxy switch line card For a proxy switch line card, if it only supports Layer 2 communication, the proxy switch line card reports the data received by its switch chip to its Central Processing Unit (CPU), and then according to the destination MAC (Media Access Control, Media access control) address, through which the switch chip and the standby master control port forward the corresponding synchronous data to the standby master; if the proxy switch line card supports Layer 3 communication, the proxy switch line card is based on the destination IP (Internet Protocol, The Internet Protocol (IP) address processes the data received by its switching chip. If the destination IP is its own, it sends the data to its CPU. If the destination IP is the standby master, its switching chip directly connects to the port connected to the standby master. The data is forwarded to the alternate master.
  • IP Internet Protocol
  • the direct link is enabled by enabling the corresponding port connected to the master master and the standby master, thereby implementing the master master and Data synchronization between alternate masters.
  • the storage medium may be a ROM (Read-Only Memory)/RAM (Random Access Memory), a magnetic disk, an optical disk, or the like.
  • the dual-master device includes an active main control, a standby main control, and a line card. As shown in FIG. 2, the device includes:
  • the proxy selection module 21 is arranged to select a line card as a proxy exchange line card for data synchronization during data synchronization using the direct link between the primary master and the standby master.
  • the agent selection module 21 is configured to sort the service configuration quantity of the line card of the dual master device, determine the line card with the least service configuration amount, and use the line card with the determined service configuration quantity as the proxy exchange line card.
  • the link detection module 22 is configured to detect a direct link between the primary master and the standby master.
  • the data synchronization module 23 is configured to disable the direct link when the link detection module 22 detects that the direct link is abnormal, and exchange the line card through the proxy to implement data synchronization between the primary master and the backup master. .
  • the link detecting module 22 detects that an abnormality occurs in the direct link
  • the data synchronization module 23 first disables the switch chip port directly connected to the standby master of the master host, and uses the standby master and the master.
  • the switch chip port of the master direct connection is disabled, thereby disabling the direct link; then, the proxy exchanges the line card to form an extended communication link between the dual masters, thereby realizing the real-time synchronization data between the dual masters. Sex and accuracy.
  • the link detecting module 22 detects a communication link formed by the proxy switching line card for realizing data synchronization between the primary master controller and the standby master controller, and when detecting that the communication link is abnormal, the proxy selects The module 21 selects another line card as the new agent exchange line card, so that the data synchronization module exchanges the line card through the new agent to realize data synchronization between the master main controller and the standby master controller.
  • the link detection module 22 detects that the direct link is normal, the data synchronization module 23 enables the direct link to implement data synchronization between the primary master and the standby master.
  • the dual-master device includes an active main control, a standby main control, and multiple line cards (for example, in FIG. 3 Line card 1 to line card 4), wherein the main master and the standby master are connected through the direct link 1, and the data synchronization between the dual masters is realized through the direct link 1.
  • each line card is connected to the standby main control through the corresponding port respectively, thereby realizing data communication between the main control and the line card, for example, the line card 2 performs data communication with the main control through the communication link 2. And communicate with the alternate master via communication link 3.
  • the line card can be used to forward the synchronization data between the masters.
  • 4 is a schematic diagram of forwarding synchronization data by a line card CPU after an abnormality occurs in the direct link 1 of the dual master control according to the embodiment of the present invention. As shown in FIG. 4, it is assumed that the line card 2 shown in FIG. 3 is selected as a proxy. Exchange line card.
  • the port ge1 of the switch chip of the master master is connected with the port ge2 of the switch chip of the standby master to form a direct link 1; the port ge3 of the switch chip of the master switch and the port ge4 of the switch chip of the proxy switch line card
  • the connection forms a link 2;
  • the port ge7 of the switch chip of the standby master is connected to the port ge6 of the switch chip of the proxy switch line card to form a direct link 3.
  • the alarm module of the active master reports an alarm message about the abnormal link of the direct link.
  • the system disables port ge1 and port ge2 according to the alarm message, and forwards the synchronization data between the masters via link 2 and link 3.
  • the port ge4 of the switching chip of the proxy switching line card receives the synchronization data via the link 2, and sends the synchronization data to the CPU, and then the CPU forwards the synchronization data via the port ge6, that is, sends the synchronization data to the via 3 Port ge7 of the alternate master switch chip. Alternate After receiving the synchronization data via the link 3, the port ge7 of the master switching chip sends the data to its CPU.
  • FIG. 5 is a schematic diagram of forwarding synchronization data by a line card switching chip after an abnormality occurs in the direct link 1 of the dual master control according to the embodiment of the present invention.
  • the line card 2 of FIG. 5 supports three layers of communication.
  • the synchronization data of the master master is transmitted via the port ge3 of the switch chip.
  • the port ge4 of the switching chip of the switching line card exchanges the synchronization data received via the link 2 and forwards the synchronization data directly via the port ge6, that is, the synchronization data is transmitted via the link 3 to the port ge7 of the switching chip of the standby master.
  • the port ge7 of the standby master switching chip After receiving the synchronization data via the link 3, the port ge7 of the standby master switching chip sends the data to its CPU.
  • FIG. 6 is a flowchart of an operating system of a switch chip port after an abnormality occurs in the direct link 1 of the dual master control according to the embodiment of the present invention. As shown in FIG. 6, the steps include:
  • Step S201 Perform timing detection on the direct link between the dual masters.
  • Step S202 It is determined whether the direct link between the dual masters is abnormal. If the fault is abnormal, step 205 is performed; otherwise, step S203 is performed.
  • Step S203 It is judged whether the direct exchange chip port (for example, port ge1 and port ge2 of FIG. 4) between the dual masters has been disabled. If it has been disabled, step S204 is performed, otherwise step S201 is performed.
  • the direct exchange chip port for example, port ge1 and port ge2 of FIG. 4
  • Step S204 Enable the direct exchange switch chip port, and execute step S201.
  • Step S205 Disabling the direct exchange switch chip port, and executing step S201.
  • FIG. 7(a) is a schematic diagram showing the path of the keepalive detection packet when the communication link alarm detection point is transferred between the main control and the line card according to the embodiment of the present invention, as shown in FIG. 7(a).
  • the master-master CPU sends the keep-alive probe message to the port ge4 of the switch chip of the proxy switch line card via the port ge3 of the switch chip, and the CPU of the proxy switch line card receives the keep-alive probe message sent by the switch chip.
  • the packet is forwarded to the port ge7 of the switch chip of the standby master through the port ge6 of the switch chip, and the standby master CPU generates the keep-alive probe response of the response after receiving the keep-alive probe packet sent by the switch chip.
  • the message is sent to the port ge6 of the switching chip of the proxy switching line card via the port ge7 of the switching chip, and the CPU of the proxy switching line card receives the keep-alive probe response message sent by the switching chip, and is sent via the port ge4 of the switching chip
  • the message is forwarded to the main master On the port ge3 of the switch chip, the CPU of the main control host receives the keep-alive probe response message sent by the switch chip.
  • FIG. 7(b) is a schematic diagram showing the path of the keepalive detection packet when the communication link alarm detection point is transferred, and the path of the keepalive detection packet is transmitted between the main control and the line card according to the embodiment of the present invention, as shown in FIG. 7(b).
  • the master-master CPU sends the keep-alive probe message to the port ge4 of the switch chip of the proxy switch line card via the port ge3 of its switch chip, and the switch chip of the proxy switch line card forwards the message to the standby via its port ge6.
  • the port ge7 of the master switching chip receives the keep-alive probe packet sent by the switch chip after receiving the keep-alive probe packet sent by the switch chip, and generates a response keep-alive probe response packet, and sends it to the proxy switch line via the port ge7 of the switch chip.
  • the port ge6 of the switching chip of the card, the switching chip of the proxy switching line card forwards the message to the port ge3 of the switching chip of the main control via its port ge4, and the CPU of the main controlling host receives the keep-alive sent by the switching chip. Probe response message.
  • FIG. 8 is a flowchart of a system for reporting an alarm on an active main control in the case of a new link abnormality according to an embodiment of the present invention. As shown in FIG. 8, the steps include:
  • Step S301 The active master sends a keep-alive probe message.
  • Step S302 Perform timing detection on the extended communication link between the dual masters (ie, the communication link between the dual masters formed by the proxy exchange line card).
  • Step S303 The primary master determines whether a response is received. If yes, step S304 is performed, otherwise step S305 is performed.
  • Step S305 adding 1 to the counter value to obtain a new count value.
  • Step S306 It is determined whether the current new count value is greater than the allowable number of times MUX of the response of the keep-alive detection message is not received. If it is greater than the MUX, step S307 is performed; otherwise, step S301 is performed.
  • Step S307 The main master reports a communication abnormality alarm.
  • the forwarding of the synchronization data between the master control by a certain line card may affect the data communication between the original master control and the line card, so the system needs to adaptively select the agent according to the actual service situation.
  • Switching line cards the amount of service configuration is small, which means that the board and the main control There is less communication interaction between them. Selecting it as a proxy forwarding line card can make the interference smaller, that is, sorting according to the line card service configuration quantity, and preferentially selecting the line card with a small service configuration amount as the proxy switching line card.
  • the unicast communication between the main control and the line card, the main control and the main control is used.
  • the main control and the main control are disabled at the same time as the network management alarm is triggered.
  • the switch chip port is controlled, and the data is forwarded by the switch chip port of the master switch and the proxy switch line card, that is, the switch chip of the proxy switch line card also receives the synchronization data between the master controllers.
  • the switching chip of the proxy switching line card After the switching chip of the proxy switching line card receives the data sent by the master control, if the switching chip supports the three-layer communication, the data is forwarded to the line card CPU or another master according to the IP address, that is, if the purpose of the data
  • the IP address is the proxy switching line card itself, and the switching chip of the proxy switching line card sends the data to the line card CPU. If the destination IP address of the data is another master, the switching chip of the proxy switching line card will The data is forwarded to the other host; if the switch chip only supports Layer 2 communication, the data is sent to the line card CPU uniformly, and then transferred by the line card CPU to another host according to the data content.
  • the new link between the two masters increases the communication abnormality detection alarm point.
  • the active master and the standby master control have the interaction of the keepalive detection packets.
  • the active master reports the communication abnormality.
  • the alarm is generated.
  • the system selects another line card as the proxy switching line card according to the order of the line card service configuration.
  • the dual master device has one master master, one spare master, and four line cards.
  • the communication link between each other is shown in Figure 3.
  • the system configures the current service settings for all line cards. Sorting, wherein the line card 2 has the least amount of service configuration, and the link between the two masters and the line card 2 is not abnormal, so it is preferentially selected as the proxy exchange line card.
  • the direct link between the dual masters is link 1, the link between the line card 2 and the active master is link 2, and the link between the line card 3 and the standby master is link 3.
  • the system is powered on, and the system sorts the current service configuration of all line cards.
  • the service configuration of line card 2 is the least, and the link between the two main control and line card 2 is abnormal, so it is preferred.
  • the ge4 of the line card 2 receives the message sent from the main controller, if the main control and the line card only support the Layer 2 communication, the message will be sent to the CPU of the board for processing, and the CPU of the board is based on the CPU.
  • the routing table forwards the packets with the destination IP address of 192.168.0.14 to the standby master through ge6. The process is shown in Figure 4.
  • the alarm detection point of the communication link between the two masters is transferred to the new link, and the active master sends a keep-alive probe every few seconds.
  • the message is forwarded to the standby master by the line card 2, and then the standby master responds to the keep-alive probe message, and then forwards to the master master through the line card 2, and the flow is as shown in Fig. 7(a) and Fig. 7(b).
  • the curve arrow indicates that if the primary master does not receive the response of the keep-alive probe message sent by itself for several consecutive times, it determines that the new link is abnormal, and the primary master reports the communication abnormal alarm.
  • the system sorts all current line card service configurations, and selects the line card with the smallest service configuration except line card 2 as the proxy forwarding line card.
  • the system detects that the direct link between the two masters is normal.
  • the communication link between the two masters is changed to the original direct link.
  • the system enables the active master and backup masters. Directly connected
  • the switching chip port ge1 and the switching chip port ge2 directly connected to the active main control side of the standby main control side are shown in FIG. 6.
  • the link between the master control and the line card is borrowed without additional cost, and the switch chip of the line card can be adaptively selected to “bridge” to forward the synchronization data, so that the two masters can Keep communication normal;
  • the bottom layer module determines the real path of synchronous data transmission between the two master controls, and the upper layer application does not need to be aware.
  • the embodiment of the invention further provides a computer readable storage medium storing computer executable instructions, which are implemented by the processor to implement the link extension method between the dual master device masters.
  • each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
  • Embodiments of the invention are not limited to any specific form of combination of hardware and software.
  • the link between the dual masters can be made through the link between the master control and the line card without changing the physical link between the dual master (ie, the primary master and the standby master). Effectively expanded to ensure that data synchronization between the two masters is normal.

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Abstract

本文公布一种双主控设备主控之间链路扩展方法及装置，所述双主控设备包括主用主控、备用主控和线卡，所述方法包括：在利用所述主用主控和所述备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡；对所述主用主控和所述备用主控之间的直连链路进行检测；当检测到所述直连链路发生异常时，禁用所述直连链路，并通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。

Description

一种双主控设备主控之间链路扩展方法及装置 技术领域
本申请涉及但不限于通讯领域，尤指一种双主控设备主控之间链路扩展方法及装置。
背景技术
对于采用集中式管理架构的运用在通讯领域的双主控设备，主控单板起到枢纽的作用，涉及的模块包括管理平面、业务平面、控制平面等多个核心模块。其中，主用主控是当前正在工作的主控，备用主控是用于备份当前各模块信息的主控。对于要求热备份的设备，备用主控的各模块要求实时“掌握”工作在主用主控的对应模块的信息，即双主控之间的数据同步。这些数据可能来自外设(例如硬盘、flash(闪存)、SD卡(Secure Digital Memory Card，安全数码卡)等)，也可能来自内存/缓存。一旦主用主控发生异常并触发主备倒换，则备用主控立刻转变为主用主控，各模块依据之前实时同步的数据开始工作。如果此时的热备份数据不完备，则影响设备业务的稳定运行。因此，双主控之间的数据同步的准确性和实时性是至关重要的。
目前通讯领域的双主控设备，各设备供应商大多采用两条直连高速总线来完成双主控之间的通信。而在实践中发现，两条通信链路，无论采用主备方式，还是负荷分担方式，仍可能存在一定程度链路异常情况，而受制于主控的交换芯片的端口数量，不能采用更多直连链路。即使随着硬件成本的进一步降低，交换芯片端口数量的增加，可以在新设备里增加更多直连链路，但如何保证老设备的双主控间数据同步的准确性和实时性，仍是目前面临的主要问题。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求 的保护范围。
根据本发明实施例提供的双主控设备主控之间链路扩展方法及装置，可以提高老设备的双主控间数据同步的准确性和实时性。
根据本发明实施例提供的双主控设备主控之间链路扩展方法，所述双主控设备包括主用主控、备用主控和线卡，所述方法包括：
在利用所述主用主控和所述备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡；
对所述主用主控和所述备用主控之间的直连链路进行检测；
当检测到所述直连链路发生异常时，禁用所述直连链路，并通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。
在一实施方式中，所述的选取一个线卡作为用于数据同步的代理交换线卡的步骤包括：
对所述双主控设备的线卡的业务配置量进行排序，确定业务配置量最少的线卡；
将所确定的业务配置量最少的线卡作为代理交换线卡。
在一实施方式中，所述的禁用所述直连链路的步骤包括：
将所述主用主控的与备用主控直连的交换芯片端口禁用；
将所述备用主控的与主用主控直连的交换芯片端口禁用。
在一实施方式中，所述的通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步的步骤包括：
所述代理交换线卡与所述主用主控相连的端口接收来自所述主用主控的同步数据，以及，所述代理交换线卡与所述备用主控相连的端口将所述同步数据转发至所述备用主控。
在一实施方式中，还包括：
对经由所述代理交换线卡形成的用于实现所述主用主控和所述备用主控之间数据同步的通信链路进行检测；
当检测到所述通信链路发生异常时，选取另一线卡作为新的代理交换 线卡，以便通过所述新的代理交换线卡实现所述主用主控和所述备用主控之间的数据同步。
在一实施方式中，还包括：
当检测到所述直连链路正常时，启用所述直连链路，实现所述主用主控和所述备用主控之间的数据同步。
根据本发明实施例提供的存储介质，其存储用于实现上述双主控设备主控之间链路扩展方法的程序。
根据本发明实施例提供的一种双主控设备主控之间链路扩展装置，所述双主控设备包括主用主控、备用主控和线卡，所述装置包括：
代理选取模块，设置为在利用所述主用主控和所述备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡；
链路检测模块，设置为对所述主用主控和所述备用主控之间的直连链路进行检测；
数据同步模块，设置为当所述链路检测模块检测到所述直连链路发生异常时，禁用所述直连链路，并通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。
在一实施方式中，所述代理选取模块设置为对所述双主控设备的线卡的业务配置量进行排序，确定业务配置量最少的线卡，并将所确定的业务配置量最少的线卡作为代理交换线卡。
在一实施方式中，所述链路检测模块还设置为：对经由所述代理交换线卡形成的用于实现所述主用主控和所述备用主控之间数据同步的通信链路进行检测；所述代理选取模块还设置为：当所述链路检测模块检测到所述通信链路发生异常时，选取另一线卡作为新的代理交换线卡，以供所述数据同步模块通过所述新的代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。
在一实施方式中，所述数据同步模块还设置为：当所述链路检测模块检测到所述直连链路正常时，启用所述直连链路，实现所述主用主控和所 述备用主控之间的数据同步。
根据本发明实施例提供的一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被处理器执行时实现上述双主控设备主控之间链路扩展方法。
本发明实施例提供的技术方案具有如下有益效果：
本发明实施例能够在不改变双主控(即主用主控和备用主控)之间物理链路的情况下，通过主控与线卡间的链路，使双主控之间链路得到有效拓展，确保双主控之间数据同步正常。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1是本发明实施例提供的双主控设备主控之间链路扩展方法框图；
图2是本发明实施例提供的双主控设备主控之间链路扩展装置框图；
图3是本发明实施例提供的双主控设备的系统通信链路示意图图；
图4是本发明实施例提供的双主控间直连链路1出现异常后，由线卡CPU转发同步数据的示意图；
图5是本发明实施例提供的双主控间直连链路1出现异常后，由线卡交换芯片转发同步数据的示意图；
图6是本发明实施例提供的双主控间直连链路1出现异常后，由交换芯片端口操作系统流程图；
图7(a)是本发明实施例提供的主控与线卡间只支持二层通信，且通信链路告警检测点转移时保活探测报文的路径示意图；
图7(b)是本发明实施例提供的主控与线卡间支持三层通信，且通信链路告警检测点转移时保活探测报文的路径示意图；
图8是本发明实施例提供的新链路异常情况下，主用主控上报告警的系统流程图(MUX代表可容许的没有收到保活探测报文次数)。
详述
以下结合附图对本发明的实施例进行详细说明，应当理解，以下所说明的实施例仅用于说明和解释本申请，并不用于限定本申请。
图1是本发明实施例提供的双主控设备主控之间链路扩展方法框图，双主控设备包括主用主控、备用主控和线卡，如图1所示，步骤包括：
步骤S101：在利用主用主控和备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡。
其中，对双主控设备的线卡的业务配置量进行排序，确定业务配置量最少的线卡，并将所确定的业务配置量最少的线卡作为代理交换线卡。
步骤S102：对主用主控和备用主控之间的直连链路进行检测。
步骤S103：当检测到直连链路发生异常时，禁用直连链路，并通过代理交换线卡，形成主用主控和备用主控之间的扩展的通信链路，从而利用该扩展的通信链路，实现主用主控和备用主控之间的数据同步。
当检测到直连链路发生异常时，首先将主用主控的与备用主控直连的交换芯片端口禁用，并将备用主控的与主用主控直连的交换芯片端口禁用，从而使直连链路禁用。然后，双主控间通过代理交换线卡转发同步数据，例如主用主控通过其与代理交换线卡相连的端口将同步数据发送至代理交换线卡，代理交换线卡经由其与主用主控相连的端口接收来自主用主控的同步数据，并经由其与备用主控相连的端口将同步数据转发至备用主控。
对于代理交换线卡，如果其仅支持二层通信，则代理交换线卡将其交换芯片收到的数据上报至其中央处理器(Central Processing Unit，CPU)，然后根据目的MAC(Media Access Control，介质访问控制)地址，经由其交换芯片与备用主控连接的端口将相应的同步数据转发至备用主控；如果代理交换线卡支持三层通信，则代理交换线卡根据目的IP(Internet Protocol，网际协议)地址处理其交换芯片收到的数据，若目的IP是自己，则将数据发送至其CPU，若目的IP是备用主控，则其交换芯片直接经由与备用主控连接的端口将该数据转发至备用主控。
其中，在利用经由代理交换线卡形成的扩展的通信链路实现主用主控和备用主控之间数据同步的同时，对该通信链路进行链路检测，当检测到该通信链路发生异常时，选取另一线卡作为新的代理交换线卡，以便通过新的代理交换线卡实现主用主控和备用主控之间的数据同步。
当检测到主用主控和备用主控之间的直连链路正常时，通过启用主用主控和备用主控相连的相应的端口，启用直连链路，从而实现主用主控和备用主控之间的数据同步。
本领域普通技术人员可以理解，实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，所述程序可以存储于计算机可读取存储介质中，该程序在执行时，包括步骤S101至步骤S103。其中，的存储介质可以为ROM(Read-Only Memory，只读存储器)/RAM(Random Access Memory，随机存取存储器)、磁碟、光盘等。
图2是本发明实施例提供的双主控设备主控之间链路扩展装置框图，双主控设备包括主用主控、备用主控和线卡，如图2所示，装置包括：
代理选取模块21，设置为在利用主用主控和备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡。其中，代理选取模块21设置为对双主控设备的线卡的业务配置量进行排序，确定业务配置量最少的线卡，并将所确定的业务配置量最少的线卡作为代理交换线卡。
链路检测模块22，设置为对主用主控和备用主控之间的直连链路进行检测。
数据同步模块23，设置为当链路检测模块22检测到直连链路发生异常时，禁用直连链路，并通过代理交换线卡，实现主用主控和备用主控之间的数据同步。其中，当链路检测模块22检测到直连链路发生异常时，数据同步模块23首先将主用主控的与备用主控直连的交换芯片端口禁用，并将备用主控的与主用主控直连的交换芯片端口禁用，从而使直连链路禁用；然后，通过代理交换线卡，形成双主控之间的扩展的通信链路，从而实现双主控间的同步数据的实时性和准确性。
其中，链路检测模块22对经由代理交换线卡形成的用于实现主用主控和备用主控之间数据同步的通信链路进行检测，当检测到该通信链路发生异常时，代理选取模块21选取另一线卡作为新的代理交换线卡，以供数据同步模块通过新的代理交换线卡，实现主用主控和备用主控之间的数据同步。
其中，当链路检测模块22检测到直连链路正常时，数据同步模块23启用直连链路，实现主用主控和备用主控之间的数据同步。
图3是本发明实施例提供的双主控设备的系统通信链路示意图图，如图3所示，双主控设备包括主用主控、备用主控和多个线卡(例如图3中的线卡1至线卡4)，其中，主用主控与备用主控之间通过直连链路1连接，并通过直连链路1实现双主控间的数据同步。同时，每个线卡通过相应的端口分别于主用主控与备用主控连接，实现主控和线卡间的数据通信，例如线卡2通过通信链路2与主用主控进行数据通信，并通过通信链路3与备用主控进行数据通信。
当图3所示的直连链路1异常出现异常时，主用主控与备用主控无法通过直连链路1实现数据同步，此时可以利用线卡转发主控间的同步数据。图4是本发明实施例提供的双主控间直连链路1出现异常后，由线卡CPU转发同步数据的示意图，如图4所示，假设选取图3所示的线卡2作为代理交换线卡。主用主控的交换芯片的端口ge1与备用主控的交换芯片的端口ge2连接，形成直连链路1；主用主控的交换芯片的端口ge3与代理交换线卡的交换芯片的端口ge4连接，形成链路2；备用主控的交换芯片的端口ge7与代理交换线卡的交换芯片的端口ge6连接，形成直连链路3。当直连链路1异常时，主用主控的告警模块上报关于直连链路异常的告警消息。系统根据该告警消息禁用端口ge1和端口ge2，并经由链路2和链路3转发主控间的同步数据。
图4假设线卡2仅支持二层通信，主用主控的同步数据经由交换芯片的端口ge3发送。代理交换线卡的交换芯片的端口ge4经由链路2收到同步数据，并将该同步数据上送至CPU，然后CPU再经由端口ge6转发该同步数据，即经由链路3将同步数据发送至备用主控的交换芯片的端口ge7。备用 主控的交换芯片的端口ge7经由链路3收到同步数据后，将该数据上送至其CPU。
图5是本发明实施例提供的双主控间直连链路1出现异常后，由线卡交换芯片转发同步数据的示意图，如图5所示，图5的线卡2支持三层通信，主用主控的同步数据经由交换芯片的端口ge3发送。代理交换线卡的交换芯片的端口ge4经由链路2收到的同步数据，并直接经由端口ge6转发该同步数据，即经由链路3将同步数据发送至备用主控的交换芯片的端口ge7。备用主控的交换芯片的端口ge7经由链路3收到同步数据后，将该数据上送至其CPU。
图6是本发明实施例提供的双主控间直连链路1出现异常后，由交换芯片端口操作系统流程图，如图6所示，步骤包括：
步骤S201：对双主控间的直连链路进行定时检测。
步骤S202：判断双主控间的直连链路是否异常，若异常则执行步骤205，否则执行步骤S203。
步骤S203：判断双主控间的直连交换芯片端口(例如图4的端口ge1和端口ge2)是否已被禁用，若已被禁用则执行步骤S204，否则执行步骤S201。
步骤S204：启用直连交换芯片端口，执行步骤S201。
步骤S205：禁用直连交换芯片端口，执行步骤S201。
图7(a)是本发明实施例提供的主控与线卡间只支持二层通信，且通信链路告警检测点转移时保活探测报文的路径示意图，如图7(a)所示，主用主控的CPU经由其交换芯片的端口ge3将保活探测报文发送至代理交换线卡的交换芯片的端口ge4，代理交换线卡的CPU接收交换芯片上送的保活探测报文，并经由交换芯片的端口ge6将该报文转发至备用主控的交换芯片的端口ge7，备用主控的CPU收到交换芯片上送的保活探测报文后，生成响应的保活探测响应报文，并经由交换芯片的端口ge7发送至代理交换线卡的交换芯片的端口ge6，代理交换线卡的CPU接收交换芯片上送的保活探测响应报文，并经由交换芯片的端口ge4将该报文转发至主用主控的 交换芯片的端口ge3，主用主控的CPU接收交换芯片上送的保活探测响应报文。
图7(b)是本发明实施例提供的主控与线卡间支持三层通信，且通信链路告警检测点转移时保活探测报文的路径示意图，如图7(b)所示，主用主控的CPU经由其交换芯片的端口ge3将保活探测报文发送至代理交换线卡的交换芯片的端口ge4，代理交换线卡的交换芯片经由其端口ge6将该报文转发至备用主控的交换芯片的端口ge7，备用主控的CPU收到交换芯片上送的保活探测报文后，生成响应的保活探测响应报文，并经由交换芯片的端口ge7发送至代理交换线卡的交换芯片的端口ge6，代理交换线卡的交换芯片经由其端口ge4将该报文转发至主用主控的交换芯片的端口ge3，主用主控的CPU接收交换芯片上送的保活探测响应报文。
图8是本发明实施例提供的新链路异常情况下，主用主控上报告警的系统流程图，如图8所示，步骤包括：
步骤S301：主用主控发送保活探测报文。
步骤S302：对双主控间的扩展的通信链路(即经由代理交换线卡形成的双主控间的通信链路)进行定时检测。
步骤S303：主用主控判断是否收到应答，若收到则执行步骤S304，否则执行步骤S305。
步骤S304：将计数器清零，即计数值K＝0，执行步骤S301。
步骤S305：将计数器的计数值加1，得到新的计数值。
步骤S306：判断当前的新的计数值是否大于可容许的没有收到保活探测报文的应答的次数MUX，若大于MUX则执行步骤S307，否则执行步骤S301。
步骤S307：主用主控上报通信异常告警。
对于选取代理交换线卡的步骤，由于借用某线卡转发主控之间的同步数据，可能会影响原有的主控与线卡间的数据通信，所以系统要根据实际业务情况自适应选择代理交换线卡，业务配置量小，意味着该单板与主控 之间的通讯交互较少，选择其作为代理转发线卡，可以使干扰更小，即按照线卡业务配置量排序，优先选择业务配置量小的线卡作为代理交换线卡。
正常情况下，主控与线卡、主控与主控之间采用单播通讯，当检测到主控与主控之间直连链路异常，在触发网管告警的同时，禁用主控与主控的交换芯片端口，并改由主控与代理交换线卡的交换芯片端口转发数据，即代理交换线卡的交换芯片也接收主控之间的同步数据。
当代理交换线卡的交换芯片收到主控发来的数据后，若该交换芯片支持三层通讯，则根据IP地址将数据转发给线卡CPU或者另一主控，即若该数据的目的IP地址是代理交换线卡本身，则代理交换线卡的交换芯片将该数据上送至线卡CPU，若该数据的目的IP地址是另一主控，则代理交换线卡的交换芯片将该数据转发给该另一主控；若该交换芯片只支持二层通讯，则统一将数据上送线卡CPU，再由线卡CPU根据数据内容转发给另一主控。
双主控之间新的链路增加通信异常检测告警点，主用主控与备用主控之间有保活探测报文的交互，当检测到链路异常时，主用主控上报通信异常告警，同时，系统根据线卡业务配置量的排序，选择另一块线卡单板作为代理交换线卡。
当故障恢复，系统检测到主控与主控之间直连链路恢复正常时，主控之间改回原有直连通信链路。
下面结合图3至图8的实施对本申请作进一步的说明。
不失一般性，假设双主控设备有一块主用主控、一块备用主控和四块线卡，彼此之间的通信链路如图3所示，系统对当前所有线卡的业务配置量做排序，其中线卡2的业务配置量最少，且两个主控与线卡2之间的链路无异常，所以被优先选择为代理交换线卡。双主控之间的直连链路为链路1，线卡2与主用主控之间的链路为链路2，线卡3与备用主控之间的链路为链路3。
实现的过程如下：
1.系统上电，系统对当前所有线卡的业务配置量做排序，其中线卡2的业务配置量最少，且两个主控与线卡2之间的链路无异常，所以被优先选择为代理交换线卡。
2.当双主控间直连链路1出现异常后，如图4所示，主用主控触发告警模块上报告警，同时系统禁用主用主控侧与备用主控直连的交换芯片端口ge1和备用主控侧与主用主控直连的交换芯片端口ge2，系统示意图如图6所示。
3.以从主用主控发送数据到备用主控为例，在主用主控侧，所有通过ge1发送的报文，改由与线卡2直连的交换芯片端口ge3发送。
4.线卡2与主用主控直连的交换芯片端口ge4收到从主用主控发送来的报文后，若主控与线卡间采用三层通信，不失一般性，假设线卡2被分配的设备内IP地址为192.168.0.2，备用主控被分配的设备内IP地址为192.168.0.14，当收到的报文目的ip为192.168.0.2，则报文上送本板CPU处理，当收到的报文目的IP为192.168.0.14，则报文通过与备用主控直连的交换芯片端口ge6转发给备用主控，该流程如图5所示。
5.当线卡2的ge4收到从主用主控发送来的报文后，若主控与线卡间只支持二层通信，则报文一律上送本板CPU处理，由本板CPU根据路由表，将目的IP为192.168.0.14的报文通过ge6转发给备用主控，该流程如图4所示。
6.当双主控间直连链路1出现异常后，两个主控之间通信链路的告警检测点转移到新的链路上，每隔若干秒，主用主控发送保活探测报文，经线卡2转发给备用主控，再由备用主控应答该保活探测报文，再经过线卡2转发给主用主控，流程如图7(a)和图7(b)的曲线箭头所示，如果主用主控连续若干次没有收到自己发送的保活探测报文的应答，则判定新的链路异常，主用主控上报通信异常告警，系统示意图如图8所示，同时系统再对当前所有线卡业务配置量排序，选择除线卡2之外业务配置量最小的线卡作为代理转发线卡。
7.当故障恢复，系统检测到两个主控之间直连链路正常后，两个主控之间通信链路改为原有直连链路，系统启用主用主控侧与备用主控直连的 交换芯片端口ge1和备用主控侧与主用主控直连的交换芯片端口ge2，系统示意图如图6所示。
综上，本发明的实施例具有以下技术效果：
1、本发明实施例在不增加额外成本的情况下，借用主控与线卡间的链路，能够自适应选择某个线卡的交换芯片“搭桥”转发同步数据，使两个主控之间保持通信正常；
2、本发明实施例的两个主控之间的直连链路异常情况下，底层模块决策两个主控之间同步数据发送的真实路径，上层应用不需要感知。
本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被处理器执行时实现上述双主控设备主控之间链路扩展方法。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本发明实施例不限制于任何特定形式的硬件和软件的结合。
尽管上文对本申请进行了详细说明，但是本申请不限于此，本技术领域技术人员可以根据本申请的原理进行各种修改。因此，凡按照本申请原理所作的修改，都应当理解为落入本申请的保护范围。
工业实用性
本发明实施例能够在不改变双主控(即主用主控和备用主控)之间物理链路的情况下，通过主控与线卡间的链路，使双主控之间链路得到有效拓展，确保双主控之间数据同步正常。

Claims (10)

  1. 一种双主控设备主控之间链路扩展方法，所述双主控设备包括主用主控、备用主控和线卡，所述方法包括：
    在利用所述主用主控和所述备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡；
    对所述主用主控和所述备用主控之间的直连链路进行检测；
    当检测到所述直连链路发生异常时，禁用所述直连链路，并通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。
  2. 根据权利要求1所述的方法，其中，所述的选取一个线卡作为用于数据同步的代理交换线卡的步骤包括：
    对所述双主控设备的线卡的业务配置量进行排序，确定业务配置量最少的线卡；
    将所确定的业务配置量最少的线卡作为代理交换线卡。
  3. 根据权利要求1所述的方法，其中，所述的禁用所述直连链路的步骤包括：
    将所述主用主控的与备用主控直连的交换芯片端口禁用；
    将所述备用主控的与主用主控直连的交换芯片端口禁用。
  4. 根据权利要求1所述的方法，其中，所述的通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步的步骤包括：
    所述代理交换线卡与所述主用主控相连的端口接收来自所述主用主控的同步数据，以及，所述代理交换线卡与所述备用主控相连的端口将所述同步数据转发至所述备用主控。
  5. 根据权利要求1-4任意一项所述的方法，还包括：
    对经由所述代理交换线卡形成的用于实现所述主用主控和所述备用主控之间数据同步的通信链路进行检测；
    当检测到所述通信链路发生异常时，选取另一线卡作为新的代理交换线卡，以便通过所述新的代理交换线卡实现所述主用主控和所述备用主控之间 的数据同步。
  6. 根据权利要求1-4任意一项所述的方法，还包括：
    当检测到所述直连链路正常时，启用所述直连链路，实现所述主用主控和所述备用主控之间的数据同步。
  7. 一种双主控设备主控之间链路扩展装置，所述双主控设备包括主用主控、备用主控和线卡，所述装置包括：
    代理选取模块，设置为在利用所述主用主控和所述备用主控之间的直连链路进行数据同步期间，选取一个线卡作为用于数据同步的代理交换线卡；
    链路检测模块，设置为对所述主用主控和所述备用主控之间的直连链路进行检测；
    数据同步模块，设置为当所述链路检测模块检测到所述直连链路发生异常时，禁用所述直连链路，并通过所述代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。
  8. 根据权利要求7所述的装置，其中，所述代理选取模块设置为对所述双主控设备的线卡的业务配置量进行排序，确定业务配置量最少的线卡，并将所确定的业务配置量最少的线卡作为代理交换线卡。
  9. 根据权利要求7或8所述的装置，其中，所述链路检测模块还设置为：对经由所述代理交换线卡形成的用于实现所述主用主控和所述备用主控之间数据同步的通信链路进行检测；所述代理选取模块还设置为：当所述链路检测模块检测到所述通信链路发生异常时，选取另一线卡作为新的代理交换线卡，以供所述数据同步模块通过所述新的代理交换线卡，实现所述主用主控和所述备用主控之间的数据同步。
  10. 根据权利要求7或8所述的装置，其中，所述数据同步模块还设置为：当所述链路检测模块检测到所述直连链路正常时，启用所述直连链路，实现所述主用主控和所述备用主控之间的数据同步。
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