WO2017171891A1

WO2017171891A1 - Systems, methods, and apparatuses for modeling reticle compensation for post lithography processing using machine learning algorithms

Info

Publication number: WO2017171891A1
Application number: PCT/US2016/025781
Authority: WO
Inventors: Vasudev LAL; Hyungjin MA; Seongtae Jeong; Erik N. HOGGAN
Original assignee: Intel Corporation
Priority date: 2016-04-02
Filing date: 2016-04-02
Publication date: 2017-10-05

Abstract

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for modeling reticle compensation for post lithography processing using machine learning algorithms. For instance, in accordance with one embodiment, there are means described for patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process; creating a model of the photo-resist using physical parameters of the lithography process used to pattern the photo-resist, the model specifying contours of the plurality of features of the photo-resist; performing a post-lithography process on the photo-resist of the physical silicon wafer; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed. Other related embodiments are disclosed.

Description

SYSTEMS, METHODS, AND APPARATUSES FOR MODELING RETICLE COMPENSATION FOR POST LITHOGRAPHY PROCESSING USING MACHINE

LEARNING ALGORITHMS CLAIM OF PRIORITY [0001] None.

COPYRIGHT NOTICE

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. TECHNICAL FIELD

[0003] The subject matter described herein relates generally to the field of

semiconductor and electronics manufacturing, and more particularly, to systems, methods, and apparatuses for modeling reticle compensation for post lithography processing using machine learning algorithms.

BACKGROUND

[0004] The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.

[0005] Currently there are no standard full chip production tools used for modeling post lithographic process operations such as chemical slimming and etching. Any compensation for post lithographic processes required the formulation of rules based on geometry. The geometric classification for such rules involves considerable engineering time for both formulation and implementation. Moreover, such a geometric approach is limited to 'binning' and is not able to accurately describe a continuous spectrum of geometries.

[0006] The present state of the art may therefore benefit from the systems, methods, and apparatuses for modeling reticle compensation for post lithography processing using machine learning algorithms as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments are illustrated by way of example, and not by way of limitation, and will be more fully understood with reference to the following detailed description when considered in connection with the figures in which:

[0008] Figure 1A depicts a process flow for training a neural network according to described embodiments;

[0009] Figure IB depicts a process flow implementing the trained neural network to obtain a new post lithography model in accordance with described embodiments;

[0010] Figure 2A depicts an SEM image representation having a nested-Iso bias of chemical slimming having been accurately predicted via an appropriate amount of contour shift by the new model generated by the trained neural network in accordance with described embodiments;

[0011] Figure 2B depicts SEM image representations depicting both a post slim model and also the base OPC model in accordance with described embodiments;

[0012] Figure 3A depicts an SEM image representation having therein the lengths of a transistor contact layer after etch in accordance with described embodiments;

[0013] Figure 3B depicts an SEM image representation having therein a significantly longer transistor contact layer post etch in accordance with described embodiments;

[0014] Figure 4 is a flow diagram illustrating a method for modeling reticle compensation for post lithography processing using machine learning algorithms in accordance with described embodiments;

[0015] Figure 5 illustrates a computing device in accordance with described embodiments; and

[0016] Figure 6 illustrates an interposer that includes one or more described embodiments.

DETAILED DESCRIPTION [0017] Described herein are systems, methods, and apparatuses for modeling reticle compensation for post lithography processing using machine learning algorithms. For instance, in accordance with one embodiment, there are means described for patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process; creating a model of the photo-resist using physical parameters of the lithography process used to partem the photo-resist, the model specifying contours of the plurality of features of the photoresist; performing a post-lithography process on the photo-resist of the physical silicon wafer; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

[0018] The techniques described herein enable a reticle to be corrected for any post lithographic process operation using a model-based approach and further provide for a flexible way to combine the influence of optical image models with geometric parameters to predict post lithography process data. Such flexibility is realized in a model form which is easy to calibrate from process data, and the resulting model is fast enough to deploy in high volume full chip correction by guiding the model generation through non-linear parametric regression.

[0019] Post lithographic techniques such as chemical slimming, Directed Self- Assembly (DSA), etc., will necessarily become increasingly utilized for future process nodes as semiconductor fabrication moves farther into the nanometer realm so as to achieve the critical dimension (CD) scaling and circuit density as demanded by Moore's law. Means by which to accurately model process biases from these post lithographic techniques is vital. Reticle compensation for such processes is imperative to meet the design targets of currently

manufactured semiconductor wafers.

[0020] Conventional solutions which relied upon geometric rule based compensation has been employed for correcting post lithography process biases in high volume full chip reticle correction but is no longer viable for new technologies.

[0021] The residuals left from the geometric rule based compensations for processes like chemical slimming and etching are not sustainable for the currently manufactured semiconductor wafers and higher advanced process nodes, if the final wafer is to meet the specified design parameters, manufacturing yields, and profitability targets. [0022] The techniques described herein may be formulated to provide model based compensation for any post lithography process operation and in testing, silicon process data utilizing the described methodologies has already been demonstrated to provide a vast improvement over conventional solutions including the geometric rule based compensation approach.

[0023] In the same way that Optical Proximity Correction (OPC) models are used to correct for the optical and resist development effects, the described models for post lithographic techniques such as chemical slimming may be used for correcting the reticle for the process biases associated with such post lithographic operations. The difference being that models do not exist for such post lithographic operations whereas OPC base models are readily available and well understood. It is necessary therefore to develop a process by which such models for post lithographic operations may be created before they can be employed by the fabrication process.

[0024] Machine learning techniques such as Artificial Neural Network (ANN) algorithms are utilized according to certain embodiments to establish a contour shift required from a base Optical Proximity Correction (OPC) model to describe the post-lithography contour. According to such embodiments, the trained neural network is then used to distort the intensity image of the base OPC model, a new model is obtained which describes the post-lithography process operation. The new model is then utilized to correct reticle and in so doing, it corrects or adjusts for the post lithographic process biases attributable to the post lithography operations.

[0025] According to such embodiments, adjustments for the post lithographic process biases utilizing the new model are compensated for in the mask.

[0026] In the following description, numerous specific details are set forth such as examples of specific systems, languages, components, etc., in order to provide a thorough understanding of the various embodiments. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the embodiments disclosed herein. In other instances, well known materials or methods have not been described in detail in order to avoid unnecessarily obscuring the disclosed embodiments.

[0027] In addition to various hardware components depicted in the figures and described herein, embodiments further include various operations which are described below. The operations described in accordance with such embodiments may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software.

[0028] Any of the disclosed embodiments may be used alone or together with one another in any combination. Although various embodiments may have been partially motivated by deficiencies with conventional techniques and approaches, some of which are described or alluded to within the specification, the embodiments need not necessarily address or solve any of these deficiencies, but rather, may address only some of the deficiencies, address none of the deficiencies, or be directed toward different deficiencies and problems which are not directly discussed.

[0029] Figure 1A depicts a process flow 100 for training a neural network according to described embodiments. In particular, the process flow depicts at block 105 providing a reticle layout 105 which is input into each of blocks 110 and 115.

[0030] For block 110, the reticle layout 105 is provided as input from which to generate the simulated optical image as depicted. The simulated optical image and also optical image parameters are generated using a base OPC model in accordance with described embodiments.

[0031] For block 115, the reticle layout 105 is provided as input from which the geometrical parameters 115 are established.

[0032] Given a reticle layout 105 for a mask it is possible to generate the simulated optical image 110 of any structure using the semi-physical model as provided by the base OPC model, although a semi-physical model is not necessarily required for this process as any model which describes the contours of the features of the mask will suffice. Once the simulated optical image 110 is generated it is then possible to extract a variety of patterns either directly from the reticle layout 105 or from the simulated optical image 110 providing a full feature set that may then be input into the machine learning algorithms of the neural network for training purposes 120.

[0033] The simulated optical image is then distorted locally to produce the necessary contour shift from the base OPC model contour to the observed SEM contour for a given post lithographic process.

[0034] At block 125 there is depicted the fabrication data characterizing post lithography process bias. Ultimately, the artificial neural network training 120 is based upon these three inputs, the simulated optical image and its optical image parameters generated using the base OPC model 110, the geometrical parameters 115, and the fabrication data characterizing post lithography process bias 125.

[0035] Also referred to as calibration, the inputs into the artificial neural network train the neural network, or permit the neural network to utilize its machine learning, to generate equation functions to represent a delta by which to shift the contours of the of the OPC base model to represent post lithographic observations, that is to say, the post lithographic reality as represented by the fabrication data as indicated at block 125. [0036] In accordance with described embodiments, a base OPC model is built which describes the final critical dimensions for structures and features as a result of a lithographic process.

[0037] Resist patterns generated by lithographic processes are the results of complicated optical, chemical and physical phenomenon, which can be modeled based on optical image parameters and geometric parameters. Model predictions, which are represented in the form of contours, are generated based on the distorted image maps, which are numerically stable and efficient enough to be used for high volume manufacturing. To generate an accurate and yet numerically efficient model, machine learning algorithms such as Artificial Neural Network (ANN) algorithms are employed in accordance with certain embodiments.

[0038] As the structures and features of a semiconductor wafer are designed smaller and smaller, the conventional lithographic processes are no longer sufficient to develop those features. As the dimensions of the features are reduced in size, the smallest feature to be incorporated into any given chip becomes so small that it has a size which is beyond the limits of such lithographic processes, and thus, post-lithographic operations are further employed, such as chemical slimming, etching, and so forth, until the designed critical dimensions for the various structures and features are attained.

[0039] Base OPC models are utilized to describe the results of the standard lithographic processes, but such base OPC models simply have no capability by which to predict or describe the results of post-lithographic processes.

[0040] Current semiconductor fabrication processes were found to require many post- lithographic operations in order to attain the design critical dimensions. Semi-physical models used to predict the final result of the lithographic processes failed to accurately predict the final result of the semiconductor wafer structures and features after processes such as chemical slimming and etching yet it remained necessary to model the final result of the polymer photoresist layer such that deficiencies in the patterning could be addressed before transferring the partem into the silicon to produce an actual functioning electrical device.

[0041] Such a polymer photo-resist layer acts as a temporary sacrificial layer which is then used to mask for the other post-lithographic processing operations.

[0042] Regardless of what model is utilized for the photo-resist, it is necessary to accurately predict the results of subsequent operations which as stated above, is beyond the capabilities of the base OPC model or any conventionally available solutions.

[0043] Making assumptions such as global sizing adjustments to adjust all contours of the features and structures, for instance, 5 nm larger or 5 nm smaller, simply fail to account for the complexity of these processes and result in significant error. [0044] The transfer of the pattern onto silicon is not an exact match nor is it so simplistic as to permit a global sizing adjustment, although such crude assumptions have been attempted in other models.

[0045] In reality, the transfer of the patterns onto the silicon results in contour variations that are far more complex than a simple global sizing adjustment or other blanket assumptions. Performing the artificial neural network training 120 therefore permits the machine learning capabilities of the neural network to develop its own arbitrary equation functions to accurately describe the differences between what is observed from actual fabrication data characterizing the post lithography process biases 125 as compared to the simulated optical image generated using a base OPC model 110 such that a contour shift may be defined to accommodate the change.

[0046] Through this training of the neural network it is then possible to have the neural network apply its developed equation functions to new mask features and structures and output a new model predicting the contours of the features and structures of that new mask in any or all of the multiple post-lithographic processes with far greater accuracy than is possible with such global sizing adjustments or other known geometric rule based compensation strategies.

[0047] Figure IB depicts a process flow 101 implementing the trained neural network to obtain a new post lithography model in accordance with described embodiments. In particular, a new reticle layout 135 is provided as an input to block 140 from which a new simulated optical image is generated using a base OPC model 140. At block 145, image distortion is performed using the trained neural network to achieve an appropriate contour shift. At block 150, a new model is provided with a model contour describing the post lithography operation.

[0048] The process bias for any post lithographic operation in the fab has a deterministic relationship with the mask pattern. A specific pattern on the reticle will have a specific etch bias, or the resist will slim using chemical means by a specific amount.

[0049] According to described embodiments, the neural network implements machine learning techniques to train the new model provided by the neural network to predict the deterministic post lithography process bias for any given mask layout.

[0050] Optical image parameters calculated from the OPC base model have intrinsic information about the layout embedded within the simulated optical image. These optical image parameters, along with the geometric parameters 115 serve as the inputs that are used to train artificial neural networks to predict the process bias of the post lithographic steps.

[0051] Once the neural network is trained, it is used to distort the intensity of the OPC model as depicted at block 145. In such a way, the contour of the simulated optical image generated using the OPC base model is thus shifted to obtain a new model contour that describes the outcome after the desired post lithography operation as set forth by block 150. By training the neural network with a known before and after example, the neural network is able to generate the necessary adaptations to the base OPC model by which to arrive up on the actually observed fabrication results. These adaptations may then be applied to new reticle layouts 135 to provide a predicted contour as represented by the new model contour at block 150. The new model contours as predicted by the trained neural network have been demonstrated in testing to provide significantly improved results over prior solutions.

[0052] In such a way, use of the new model contour describing the post lithography process operation 150 may be utilized transparently by existing correction infrastructure already in place to correct reticles for OPC effects, but with much improved results as provided by the new model contours for post lithographic operations as a result of the trained neural network.

[0053] Moreover, the reticle can be corrected for any process bias capable of being characterized post lithography by, for example, capturing SEM images of the photo resist, the mask, or the structures and features physically embodied within the in-process physical silicon wafer being fabricated through the etch, slimming, buildup, and other post lithographic processes.

[0054] Previously it was not necessary to model the post-lithographic processes to correct for reticle because the physically larger sizes of the structures and features permitted a greater margin of error which sufficiently accounted for existing process variances.

[0055] As the physical sizes of these structures and features become smaller the margin for error is reduced and thus, even small errors lead to defects.

[0056] Different features and structures respond differently to the various post- lithographic processes which affect the resulting contours of those features after such processes which vary according to a complex confluence of factors which is extremely difficult to predict. Nonetheless, it is necessary to predict the shift in the contours at each of the post-lithographic operations so as to stay within the much smaller margin of error present at these smaller physical dimensions.

[0057] When transferring from the photo-resist to the final etch and after the resisted etch is complete it is necessary to compensate for these effects or the device simply will not operate due to the inadvertent creation of shorts and opens not designed into the circuit.

[0058] The trained neural network is able to compensate for these effects by producing a new model which can comprehend differential etched layers and differential slimming from structure to structure on the chip and then apply its equation functions developed through the machine learning and training process of the neural network to describe such differences to new design features and structures input into the neural network via reticle layout 135. The neural network is then able perform the image distortion based on the developed equation functions to achieve the appropriate contour shift and output the new model contour shift describing the new contour at any of the post lithography operations employed.

[0059] Figure 2 A depicts an SEM image representation 201 having a nested-Iso bias of chemical slimming having been accurately predicted via an appropriate amount of contour shift by the new model generated by the trained neural network in accordance with described embodiments. In particular, the SEM image representation 201 depicts both the base model contour 225 as represented by the thick bold line and also the new model contour 220 as represented by the thin black line. For both the Iso 255 and the nested 250 structures, the trained neural network predicts a new model contour 220 through appropriate contour shift which is significantly more accurate and more tightly bound to the observed structures in actual SEM images than conventional solutions.

[0060] Isolated features 255 usually slim more than nested 250 features. The trained neural network accurately predicts the contour shift required to the base model contour 225 depicted by the thick bold line in order to account for the post chemical slim data as represented by the new model contour 220.

[0061] With a dimensional lithography process a photo-resist is created but because the new technologies require the smaller dimensions which are unattainable via lithography, the photo-resist is subjected to a post-lithography chemical slimming process which is depicted via the SEM image representation 201.

[0062] The chemical slimming process is performed to reduce the features and structures in size beyond that which is feasible with lithography, however, it has been observed that the chemical slimming exhibits a nested-Iso bias in which the chemical slimming shrinks the photoresist to a greater degree for isolated 255 features as depicted on the left and shrinks the photoresist to a lesser degree for those features on the nested 250 side.

[0063] In accordance with one embodiment, SEM images collected to provide actually observed fabrication data characterizing the post lithography process biases. For instance, SEM images may be taken of a photo-resist post chemical slimming or post etching or at any stage or operation after the lithography process for which the neural network needs to be trained to predict the contour shifting or adaptations from the base OPC model to attain the observed post lithography process biases captured by the SEM images at those stages.

[0064] According such embodiments, SEM images of a photo-resist having final structures and features embodied therein is captured and analyzed to measure for critical dimensions of the structures and features of the photo-resist after a post lithography stage. Such analysis and determination of the critical dimensions for the structure and features of the photo- resist at that stage thus constitute an input into the training process of the neural network. [0065] In accordance with a particular embodiment, post-DCCD (post developer check critical dimensions) are obtained from the SEM images and input into the neural network for training purposes.

[0066] Stated differently, after the lithographic process creates a photo-resist, the critical dimensions of several features on the photo-resist are measured from the SEM images and input into the neural network to represent the post lithographic process biases for that particular post- lithographic stage of processing. Such collection of SEM images, measuring of the critical dimensions from the photo-resist, and inputting of those SEM images or measured critical dimensions into the neural network may performed at each of many post lithographic stages. For instance, there may be multiple chemical slimming stages, multiple etching stages, or other post lithographic stages to develop the appropriate dimensions of the features and structures on the photo-resist which cannot be attained directly through lithography.

[0067] According to a particular embodiment, a base OPC model is then utilized to render a model of the features and structures of the photo-resist which will most closely represent the results of the lithographic process. The neural network is then trained using the collected critical dimension measurements from the SEM images of the photo-resist at the post lithographic process to be modeled and the neural network generates through a machine learning process its equation functions necessary to shift the contour provided by the base OPC model for the structures and features at the post lithographic stage to the observed fab data measured for those structures and features using the measured critical dimensions from the SEM images of the photo-resist having undergone the post lithographic process in question.

[0068] Once trained, the neural network is able to make its own prediction of the contours and critical dimensions for the structures and features of the photo-resist at the post lithographic process, however, more importantly, the trained neural network is able to predict the contours and critical dimensions for new features as embodied within a photo-resist at the same post lithographic process, even though those features have not necessarily been observed within SEM image data from the fab.

[0069] It is these predictions which render the new model contour 220 and provide the new model which is then utilized to correct reticles at the post lithographic operations for new masks and for the resulting photo-resists from those new masks which must undergo the post lithographic processing.

[0070] According to certain embodiments, geometric information from the reticile layout is additionally utilized to directly train the neural network to predict the amount of contour shift necessary to attain the observed geometry. Once trained, the neural network provides an accurate model which can then be implemented by shifting a base OPC model contour by an amount predicted by the neural network. For instance, once trained, a provided reticle layout is used to develop the simulated optical image using the base OPC model, from which the contour shifting is applied by the trained neural network to produce the new model and new model contour 220 for the photo-resist at the applicable post lithographic stage based on the trained neural network's predicted contour shift from the base model contour 225.

[0071] Because the model, the structures, the features, the mask, and the post lithographic photo-resist is so complex it simply is not practical to manually determine what function or adaptations to the incoming base OPC model are necessary to conform that model to the reality as observed in the SEM imagery taken from the photo-resists. Use of the neural network to apply machine learning therefore provides a significant advantage as the neural network is leveraged to determine the complexity and learn the necessary adaptations.

[0072] According to such an embodiment, a delta between the base OPC model contour and the SEM contour characterizing fab data is determined and the neural network is trained to be able to generate a contour shift prediction from the base OPC model contour to compensate for the delta so as to produce the new model or the new model contour representing the predicted contours of the features and structures of the photo-resist at the applicable post lithographic stage.

[0073] Figure 2B depicts SEM image representations 202 and 203 depicting both a post slim model and also the base OPC model in accordance with described embodiments.

[0074] As depicted, post slim models such as that shown by SEM image representation

202 which are calibrated using the new model contour as provided by the trained neural network result in more accurate post slim data than that which is provided by the base OPC model.

[0075] Notably, the error bars as represented by the thickness of the white lines are reduced in the SEM image representation 202 as compared to the SEM image representation 203 of the base OPC model. For instance, around the curves and the isolated features it can be seen that the contours are tighter and the error is reduced.

[0076] Some post lithographic processes result in relatively large changes to the contours and critical dimensions of the features and structures within the photo-resist or within the deeper layers of the fabricated silicon wafers between post lithographic operations.

Consequently, larger corrections to the base OPC model are sometimes necessary, resulting in significant predicted contour shift from the base OPC model contour to the predicted new model contour as provided by the trained neural network.

[0077] Such contour shift amounts between post lithographic processes may be on the order of 20 nanometers per etch as the patterns are etched down to their final dimensions.

However, such shift is not consistent amongst the features and structures for any given post lithographic etch phase or chemical slimming operation. For instance, within the same operation, it is possible that one structure undergoes a shift of 20 nanometers whereas other structures shift their contours or critical dimensions by only 5 nanometers. These large variances can result in the trained neural network predicting somewhat chaotic and highly abrupt changes to the contour resulting in spatial instability of the new model.

[0078] These corrections or contour shifts between the base OPC model and the predicted contour provided by the new model can lead to problems with stability and also over fitting by the trained neural network.

[0079] Therefore, it is in accordance with particular embodiments that criteria of the new model contour are checked at the full chip level to ensure a stable contour generation as provided by the trained neural network.

[0080] According to additional embodiments, problems with over-fit and contour stability are prevented at the neural network training level via the introduction of a regularization technique either outside of the neural network in which case a smoothed contour which is a result of the regularization technique is input into the neural network or alternatively, the smoothing of the contour is performed by the neural network which implements the

regularization technique.

[0081] Therefore, in accordance with certain embodiments, regularization is applied during the training of the neural network improve spatial stability of the new model and also to prevent over-fitting of the new model contour.

[0082] In particular, spatially, the neural network is trained to predict the contour shift at the contour locations as a predicted delta, variance, or adaptation from the base OPC model contour. However, the entire two dimensional image map is distorted to achieve the contour shift in the new model. Consequently, it is important for the contour shift prediction to exhibit stability via characteristics such as slowly varying and varying within bounds, at spatial locations away from the contours. Otherwise, the contour shift prediction could result in a seemingly chaotic result which may be mathematically accurate but pragmatically unrealistic for the application of the prediction to the OPC base model so as to render the post lithographic stage contours.

[0083] Secondly, neural networks, especially those of high complexity, are prone to over-fitting. It is therefore in accordance with certain embodiments that a safeguard is provided against over-fitting by the trained neural network by imposing a physical condition mandating within the model that any contour shift prediction must be a slowly varying function of space.

[0084] Such regularization is achieved by having spatial sites in the target function, in which the values of the contour shift at the spatial sites are obtained by a distance-weighted sum of the desired contour shift at other nearby contour locations. Through application of such a regularization technique, it has been demonstrated that both predictive capability is increased and also model stability is increased for the models obtained utilizing the methodologies described herein.

[0085] According to described embodiments, any target variable to the contour location is a determination of best fit for vector length from an OPC base model contour to the SEM contour representing the actual fabrication data for post lithographic process biases. The delta between these two points represents the shift from the base OPC model contour to the observed SEM contour. Determining the length of the vector for every one of a series of points making up the contour thus establishes the shift to the base OPC model contour to attain the final result.

[0086] Due to the manner by which the contour is shifted, the entire mask is locally distorted. Both the contour and the shifted contour represent a 2D quantity and the regularization process applies a smoothing function to the shifted contour to avoid problems such as over fitting. Otherwise, the shifting of the contour may provide a result which is not useful.

[0087] While the input parameters are provided for only target locations using the SEM images, in accordance with certain embodiments, additional points are additionally extrapolated to nearby pseudo target points, distinct from the actual target locations provided. By determining the delta between the base OPC model's initial contour and the SEM contour and additionally introducing the pseudo target locations for the nearby points extrapolated from the target locations, the resulting shift is smoothed. Stated differently, the contour shifting for the model error is determined on the basis of the delta from the initial contour to not just the actually measured points of the SEM image input into the neural network, but additionally based on the delta to the pseudo target locations extrapolated as nearby points to the actually measured points of the SEM image.

[0088] According to one embodiment, the predicted new model contour represents an intermediate result and a final contour for the new model is generated through the smoothing function by fitting the base OPC model contour to both the SEM contour points and also the extrapolated pseudo nearby points.

[0089] According to a particular embodiment, the neural network generates the intermediate contour using preferential locations for each of the points on the contour which are best possible matches without regard to over-fitting problems or model stability and the final contour is regularized to enhance model stability and remove or smooth out over-fitting of the contour to the measured SEM contour points.

[0090] The predicted new model contour must be useable for the post lithographic fabrication processes and therefore the predictive new models must not only be accurate, but also stable. Therefore, a candidate new model may be evaluated on a full chip basis for stability before it is utilized to correct the reticle in the post lithographic processes.

[0091] Figure 3A depicts an SEM image representation 301 having therein the lengths of a transistor contact layer after etch in accordance with described embodiments.

[0092] The thin interior line represents the actual length of the transistor contact layer after etch. The exterior thick bold line has been obtained using the trained neural network to shift the contour of the OPC base model for the transistor contact layer to the post etch contour for the transistor contract layer resulting in an accurate prediction for the length sought. In particular, element 335 depicts the model determined length.

[0093] Figure 3B depicts an SEM image representation 302 having therein a significantly longer transistor contact layer post etch in accordance with described embodiments.

[0094] Longer TCN's 325 pull back more after etch and this effect is accurately described in the by the trained neural network having correctly shifted the new model contour

330 from the base OPC model as depicted by the thick white new model contour 330 line predicted by the trained neural network.

[0095] Note however that length is not the only factor contributing to the etch bias.

Residuals differ between post etch models due to a dependence of the measured etch bias on

TCN length. The trained neural network model accurately describes the complex relationship between bias and TCN length through nonlinear regression training over multiple optical image and geometric parameters. Consequently, the trained neural network is able to render a new contour model having an appropriate contour shift to predict the process biases that physically occur due to complex interactions of multiple modulators.

[0096] Current silicon wafer fabrication processes were improved through the elimination of a dedicated scanner for the depicted transistor contact layer and additionally through a larger registration window. During testing, the improved process described herein as enabled by the trained neural network successfully addressed problems of shorts and opens in the transistor contact layer which were contributing to yields below target.

[0097] Test results using the described methodologies demonstrate improvements over prior solutions. Use of the new contour models generated by the trained neural network for post- lithographic operations therefore provides for improved tools at both design and fabrication of semiconductor wafers over prior solutions.

[0098] Figure 4 is a flow diagram illustrating a method 400 for modeling reticle compensation for post lithography processing using machine learning algorithms in accordance with described embodiments. Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from method 400 may be utilized in a variety of combinations.

[0099] At block 405 the method for modeling reticle compensation for post lithography processing using machine learning algorithms begins with patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process.

[00100] At block 410 the method includes creating a model of the photo-resist using physical parameters of the lithography process used to pattern the photo-resist, the model specifying contours of the plurality of features of the photo-resist.

[00101] At block 415 the method includes performing a post-lithography process on the photo-resist of the physical silicon wafer.

[00102] At block 420 the method includes capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

[00103] At block 425 the method includes quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process.

[00104] At block 430 the method includes shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

[00105] In accordance with another embodiment, method 400 further includes:

patterning a new photo-resist of a new physical silicon wafer with different features as defined by a new mask via the lithography process; predicting the contours of the different features of the new photo-resist of the new physical silicon wafer after undergoing the post-lithography process using the new model; and applying the reticle compensation to the new photo-resist during the post-lithography process based on the predicted contours.

[00106] In accordance with another embodiment of method 400, the post-lithography process includes one of: a chemical slimming process; an etching process; a wafer build up process; a post slimming process after wafer buildup; a process to shrink the photo-resist; a subsequent iteration of the chemical slimming process; or a subsequent iteration of the etching process.

[00107] In accordance with another embodiment, method 400 further includes:

performing a regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model. [00108] In accordance with another embodiment of method 400, shifting of the contours of the plurality of features as specified by the model distorts a two dimensional (2D) quantity representing the model of the photo-resist; and in which the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the photo-resist within the model.

[00109] In accordance with another embodiment, method 400 further includes: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model.

[00110] In accordance with another embodiment of method 400, training the neural network includes: inputting SEM image data of the physical silicon wafer after the post- lithography process is performed into the neural network; and inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.

[00111] In accordance with another embodiment of method 400, training the neural network includes: inputting SEM images of the physical silicon wafer after the post-lithography process is performed into the neural network; and generating smoothed shifted contours of the plurality of features of the photo-resist as specified by the model via a regularization process; and inputting the smoothed shifted contours of the plurality of features into the neural network.

[00112] In accordance with another embodiment of method 400, training the neural network includes: inputting into the neural network a simulated optical image generated using a base Optical Proximity Correction (OPC) model from a reticle layout for performing the lithography process used to pattern the photo-resist; inputting into the neural network geometrical parameters generated from the reticle layout; and inputting into the neural network fabrication data characterizing a process bias associated with the post-lithography process of the physical silicon wafer.

[00113] In accordance with another embodiment, method 400 further includes:

providing via the trained neural network a new model contour for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; and validating the new model contour at a full chip level for the physical silicon wafer to verify the shifted contours of the new model are spatially stable.

[00114] In accordance with another embodiment of method 400, training the neural network includes: inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a reticle layout of the contours of the plurality of features of the photo-resist as specified by the model and an optical transfer function; and in which the trained neural network generates a deterministic relationship between the reticle layout of the contours of the plurality of features of the photo-resist as specified by the model and the quantified differences.

[00115] In accordance with another embodiment of method 400, the trained neural network performs contour fitting of the contours of the plurality of features of the photo-resist as specified by the model to the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed as represented within the captured SEM images.

[00116] In accordance with another embodiment of method 400, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer after the post- lithography process is performed as captured by the SEM images; and in which the neural network generates the new model of the photo-resist specifying the contours of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

[00117] In accordance with another embodiment of method 400, the neural network performs a regularization process to smooth the shifted contour, in which the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model requiring that any contour shift prediction be a slowly varying function of space.

[00118] In accordance with another embodiment, method 400 further includes: using the new model generated by the trained neural network to predict new and different features of a new photo-resist created by a different mask based on a predicted contour shift generated by the trained neural network to contours of the new and different features of the new photo-resist as determined by the model.

[00119] In accordance with another embodiment of method 400, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features as specified by the model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer after the post-lithography process as represented by the SEM images; and in which the neural network smoothes the shift of the contours of the plurality of features as specified by the model through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance-weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.

[00120] In accordance with another embodiment of method 400, any target variable to the contour target location is a determination of best fit for vector length from a predicted contour of a base Optical Proximity Correction (OPC) model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer after the post-lithography process.

[00121] In accordance with another embodiment of method 400, quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process includes: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer after the post- lithography process as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the photo- resist as specified by the model to determine the differences.

[00122] In accordance with another embodiment of method 400, quantifying differences includes: measuring critical dimensions of the features from thousands of the SEM images of multiple physical silicon wafers having undergone the post-lithography process, in which the measuring of the critical dimensions includes measuring at each of a plurality of target points along the contours of the plurality of features of the photo-resist as specified by the model and comparing to the plurality of features embodied by the multiple physical silicon wafers captured by the thousands of SEM images to generate millions of data points quantifying the differences between the SEM images and the model.

[00123] In accordance with a particular embodiment there is a non-transitory computer readable storage medium having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for modeling reticle compensation for post lithography processing, in which operations include: patterning a photoresist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process; creating a model of the photo-resist using physical parameters of the lithography process used to pattern the photo-resist, the model specifying contours of the plurality of features of the photo-resist; performing a post-lithography process on the photo-resist of the physical silicon wafer; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

[00124] In accordance with a related embodiment there is a system having means by which to model reticle compensation for post lithography processes, in which such an exemplary system includes: a photo-resist of a physical silicon wafer patterned with a plurality of features as defined by a mask via a lithography process; a model of the photo-resist created using physical parameters of the lithography process used to pattern the photo-resist, the model specifying contours of the plurality of features of the photo-resist; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the photo-resist of the physical silicon wafer is subjected to a post-lithography process; an analysis unit to quantify differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and the analysis unit to shift the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

[00125] Described embodiments may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.

Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the described embodiments.

[00126] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various described embodiments, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the described embodiments may also be carried out using nonplanar transistors.

[00127] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiC ) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[00128] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

[00129] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[00130] In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further described embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[00131] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[00132] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or

phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[00133] One or more interlay er dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or

polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[00134] Figure 5 illustrates a computing device 500 in accordance with described embodiments. The computing device 500 houses a board 502. The board 502 may include a number of components, including but not limited to a processor 504 and at least one

communication chip 506. The processor 504 is physically and electrically coupled to the board 502. In some implementations the at least one communication chip 506 is also physically and electrically coupled to the board 502. In further implementations, the communication chip 506 is part of the processor 504.

[00135] Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to the board 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[00136] The communication chip 506 enables wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[00137] The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some described embodiments, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with described embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[00138] The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In accordance with other described embodiments, the integrated circuit die of the communication chip includes one or more devices, such as MOS- FET transistors built in accordance with described embodiments.

[00139] In further implementations, another component housed within the computing device 500 may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with described embodiments.

[00140] In various implementations, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

[00141] Figure 6 illustrates an interposer 600 that includes one or more described embodiments. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.

[00142] The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[00143] The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600. In accordance with described embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.

[00144] While the subject matter disclosed herein has been described by way of example and in terms of the specific embodiments, it is to be understood that the claimed embodiments are not limited to the explicitly enumerated embodiments disclosed. To the contrary, the disclosure is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosed subject matter is therefore to be determined in reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[00145] It is therefore in accordance with the described embodiments that:

[00146] According to one embodiment, there is a method for modeling reticle compensation for post lithography processing, comprising: patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process; creating a model of the photo-resist using physical parameters of the lithography process used to partem the photo-resist, the model specifying contours of the plurality of features of the photoresist; performing a post-lithography process on the photo-resist of the physical silicon wafer; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process.

[00147] According to embodiments, patterning a new photo-resist of a new physical silicon wafer with different features as defined by a new mask via the lithography process;

predicting the contours of the different features of the new photo-resist of the new physical silicon wafer after undergoing the post-lithography process using the new model; and applying the reticle compensation to the new photo-resist during the post-lithography process based on the predicted contours. [00148] According to embodiments, the post-lithography process comprises one of: a chemical slimming process; an etching process; a wafer build up process; a post slimming process after wafer buildup; a process to shrink the photo-resist; a subsequent iteration of the chemical slimming process; or a subsequent iteration of the etching process.

[00149] According to embodiments, performing a regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model.

[00150] According to embodiments, shifting of the contours of the plurality of features as specified by the model distorts a two dimensional (2D) quantity representing the model of the photo-resist; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the photo-resist within the model.

[00151] According to embodiments, training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model.

[00152] According to embodiments, training the neural network comprises: inputting SEM image data of the physical silicon wafer after the post-lithography process is performed into the neural network; and inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.

[00153] According to embodiments, training the neural network comprises: inputting

SEM images of the physical silicon wafer after the post-lithography process is performed into the neural network; and generating smoothed shifted contours of the plurality of features of the photo-resist as specified by the model via a regularization process; and inputting the smoothed shifted contours of the plurality of features into the neural network.

[00154] According to embodiments, training the neural network comprises: inputting into the neural network a simulated optical image generated using a base Optical Proximity Correction (OPC) model from a reticle layout for performing the lithography process used to partem the photo-resist; inputting into the neural network geometrical parameters generated from the reticle layout; and inputting into the neural network fabrication data characterizing a process bias associated with the post-lithography process of the physical silicon wafer.

[00155] According to embodiments, providing via the trained neural network a new model contour for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; and validating the new model contour at a full chip level for the physical silicon wafer to verify the shifted contours of the new model are spatially stable.

[00156] According to embodiments, training the neural network comprises: inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a reticle layout of the contours of the plurality of features of the photo-resist as specified by the model and an optical transfer function; and wherein the trained neural network generates a deterministic relationship between the reticle layout of the contours of the plurality of features of the photo-resist as specified by the model and the quantified differences.

[00157] According to embodiments, the trained neural network performs contour fitting of the contours of the plurality of features of the photo-resist as specified by the model to the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed as represented within the captured SEM images.

[00158] According to embodiments, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed as captured by the SEM images; and wherein the neural network generates the new model of the photo-resist specifying the contours of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

[00159] According to embodiments, the neural network performs a regularization process to smooth the shifted contour, wherein the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model requiring that any contour shift prediction be a slowly varying function of space.

[00160] According to embodiments, using the new model generated by the trained neural network to predict new and different features of a new photo-resist created by a different mask based on a predicted contour shift generated by the trained neural network to contours of the new and different features of the new photo-resist as determined by the model.

[00161] According to embodiments, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features as specified by the model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer after the post-lithography process as represented by the SEM images; and wherein the neural network smoothes the shift of the contours of the plurality of features as specified by the model through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance-weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.

[00162] According to embodiments, any target variable to the contour target location is a determination of best fit for vector length from a predicted contour of a base Optical Proximity Correction (OPC) model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer after the post- lithography process.

[00163] According to embodiments, quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process comprises: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer after the post-lithography process as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the photo-resist as specified by the model to determine the differences.

[00164] According to embodiments, quantifying differences comprises: measuring critical dimensions of the features from thousands of the SEM images of multiple physical silicon wafers having undergone the post-lithography process, wherein the measuring of the critical dimensions comprises measuring at each of a plurality of target points along the contours of the plurality of features of the photo-resist as specified by the model and comparing to the plurality of features embodied by the multiple physical silicon wafers captured by the thousands of SEM images to generate millions of data points quantifying the differences between the SEM images and the model.

[00165] According to embodiments, there is a system to model reticle compensation for post lithography processes, wherein the system comprises: a photo-resist of a physical silicon wafer patterned with a plurality of features as defined by a mask via a lithography process; a model of the photo-resist created using physical parameters of the lithography process used to partem the photo-resist, the model specifying contours of the plurality of features of the photoresist; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the photo-resist of the physical silicon wafer is subjected to a post-lithography process; an analysis unit to quantify differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and the analysis unit to shift the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

[00166] According to embodiments, the analysis unit is to further perform a

regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model, wherein shifting of the contours of the plurality of features as specified by the model distorts a two dimensional (2D) quantity representing the model of the photo-resist; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the photoresist within the model.

[00167] According to embodiments, the analysis unit is to further train a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model; wherein training the neural network comprises: inputting SEM image data of the physical silicon wafer after the post-lithography process is performed into the neural network and inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.

[00168] According to embodiments, there is non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for modeling reticle compensation for post lithography processing, wherein operations comprise: patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process; creating a model of the photo-resist using physical parameters of the lithography process used to partem the photoresist, the model specifying contours of the plurality of features of the photo-resist; performing a post-lithography process on the photo-resist of the physical silicon wafer; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed; quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post- lithography process is performed.

[00169] According to embodiments, the instructions cause the processor to perform operations further comprising: performing a regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model; wherein shifting of the contours of the plurality of features as specified by the model distorts a two dimensional (2D) quantity representing the model of the photo-resist; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the photo-resist within the model.

[00170] According to embodiments, the instructions cause the processor to perform operations further comprising: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model; and wherein training the neural network comprises inputting SEM image data of the physical silicon wafer after the post-lithography process is performed into the neural network and inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.

Claims

CLAIMS What is claimed is:

1. A method for modeling reticle compensation for post lithography processing, comprising: patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process;

creating a model of the photo-resist using physical parameters of the lithography process used to partem the photo-resist, the model specifying contours of the plurality of features of the photo-resist;

performing a post-lithography process on the photo-resist of the physical silicon wafer;

capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed;

quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process.

2. The method of claim 1 , further comprising:

patterning a new photo-resist of a new physical silicon wafer with different features as defined by a new mask via the lithography process;

predicting the contours of the different features of the new photo-resist of the new physical silicon wafer after undergoing the post-lithography process using the new model; and applying the reticle compensation to the new photo-resist during the post-lithography process based on the predicted contours.

3. The method of claim 1 , wherein the post-lithography process comprises one of:

a chemical slimming process;

an etching process;

a wafer build up process;

a post slimming process after wafer buildup;

a process to shrink the photo-resist;

a subsequent iteration of the chemical slimming process; or

a subsequent iteration of the etching process.

4. The method of claim 1 , further comprising:

performing a regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model.

5. The method of claim 4:

wherein shifting of the contours of the plurality of features as specified by the model distorts a two dimensional (2D) quantity representing the model of the photo-resist; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the photo-resist within the model.

6. The method of claim 1, further comprising:

training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model.

7. The method of claim 6, wherein training the neural network comprises:

inputting SEM image data of the physical silicon wafer after the post-lithography process is performed into the neural network; and

inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.

8. The method of claim 6, wherein training the neural network comprises:

inputting SEM images of the physical silicon wafer after the post-lithography process is

performed into the neural network; and

generating smoothed shifted contours of the plurality of features of the photo-resist as specified by the model via a regularization process; and

inputting the smoothed shifted contours of the plurality of features into the neural network.

9. The method of claim 6, wherein training the neural network comprises:

inputting into the neural network a simulated optical image generated using a base Optical Proximity Correction (OPC) model from a reticle layout for performing the lithography process used to pattern the photo-resist;

inputting into the neural network geometrical parameters generated from the reticle layout; and inputting into the neural network fabrication data characterizing a process bias associated with the post-lithography process of the physical silicon wafer.

10. The method of claim 6, further comprising:

providing via the trained neural network a new model contour for the plurality of features

embodied within the physical silicon wafer after the post-lithography process is performed; and

validating the new model contour at a full chip level for the physical silicon wafer to verify the shifted contours of the new model are spatially stable.

1 1. The method of claim 6, wherein training the neural network comprises:

inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a reticle layout of the contours of the plurality of features of the photo-resist as specified by the model and an optical transfer function; and wherein the trained neural network generates a deterministic relationship between the reticle layout of the contours of the plurality of features of the photo-resist as specified by the model and the quantified differences.

12. The method of claim 6, wherein the trained neural network performs contour fitting of the contours of the plurality of features of the photo-resist as specified by the model to the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed as represented within the captured SEM images.

13. The method of claim 6:

wherein the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed as captured by the SEM images; and

wherein the neural network generates the new model of the photo-resist specifying the contours of the plurality of features embodied within the physical silicon wafer after the post- lithography process is performed shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

14. The method of claim 13, wherein the neural network performs a regularization process to smooth the shifted contour, wherein the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model requiring that any contour shift prediction be a slowly varying function of space.

15. The method of claim 13, further comprising:

using the new model generated by the trained neural network to predict new and different

features of a new photo-resist created by a different mask based on a predicted contour shift generated by the trained neural network to contours of the new and different features of the new photo-resist as determined by the model.

16. The method of claim 6:

wherein the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features as specified by the model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer after the post-lithography process as represented by the SEM images; and wherein the neural network smoothes the shift of the contours of the plurality of features as

specified by the model through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance-weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.

17. The method of claim 16, wherein any target variable to the contour target location is a

determination of best fit for vector length from a predicted contour of a base Optical Proximity Correction (OPC) model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer after the post-lithography process.

18. The method of claim 1, wherein quantifying differences between (a) the contours of the

plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process comprises:

collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer after the post-lithography process as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the photo-resist as specified by the model to determine the differences.

19. The method of claim 1, wherein quantifying differences comprises:

measuring critical dimensions of the features from thousands of the SEM images of multiple physical silicon wafers having undergone the post-lithography process, wherein the measuring of the critical dimensions comprises measuring at each of a plurality of target points along the contours of the plurality of features of the photo-resist as specified by the model and comparing to the plurality of features embodied by the multiple physical silicon wafers captured by the thousands of SEM images to generate millions of data points quantifying the differences between the SEM images and the model.

20. A system to model reticle compensation for post lithography processes, wherein the system comprises:

a photo-resist of a physical silicon wafer patterned with a plurality of features as defined by a mask via a lithography process;

a model of the photo-resist created using physical parameters of the lithography process used to partem the photo-resist, the model specifying contours of the plurality of features of the photo-resist; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer after the photo-resist of the physical silicon wafer is subjected to a post-lithography process;

an analysis unit to quantify differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and

the analysis unit to shift the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

21. The system of claim 20:

wherein the analysis unit is to further perform a regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model,

22. The system of claim 20:

wherein the analysis unit is to further train a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model;

wherein training the neural network comprises: inputting SEM image data of the physical silicon wafer after the post-lithography process is performed into the neural network and inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.

23. Non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for modeling reticle compensation for post lithography processing, wherein operations comprise:

patterning a photo-resist of a physical silicon wafer with a plurality of features as defined by a mask via a lithography process;

creating a model of the photo-resist using physical parameters of the lithography process used to pattern the photo-resist, the model specifying contours of the plurality of features of the photo-resist;

quantifying differences between (a) the contours of the plurality of features of the photo-resist as specified by the model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images after the post-lithography process; and shifting the contours of the plurality of features as specified by the model based on the quantified differences to generate a new model having new contours for the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed.

24. The non-transitory computer readable media of claim 23, wherein the instructions cause the processor to perform operations further comprising:

performing a regularization operation to smooth the shifting of the contours of the plurality of features as specified by the model;

25. The non-transitory computer readable media of claim 23, wherein the instructions cause the processor to perform operations further comprising:

training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer after the post-lithography process is performed and the contours of the plurality of features of the photo-resist as specified by the model; and

wherein training the neural network comprises inputting SEM image data of the physical silicon wafer after the post-lithography process is performed into the neural network and inputting the shifted contours of the plurality of features of the photo-resist as specified by the model based on the quantified differences.