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WO2016000369A1 - 发射电极扫描电路、阵列基板和显示装置 - Google Patents

发射电极扫描电路、阵列基板和显示装置 Download PDF

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Publication number
WO2016000369A1
WO2016000369A1 PCT/CN2014/089904 CN2014089904W WO2016000369A1 WO 2016000369 A1 WO2016000369 A1 WO 2016000369A1 CN 2014089904 W CN2014089904 W CN 2014089904W WO 2016000369 A1 WO2016000369 A1 WO 2016000369A1
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WO
WIPO (PCT)
Prior art keywords
thin film
field effect
film field
effect transistor
signal
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Application number
PCT/CN2014/089904
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English (en)
French (fr)
Inventor
谭文
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/764,316 priority Critical patent/US9922589B2/en
Priority to EP14882162.2A priority patent/EP3165998B1/en
Publication of WO2016000369A1 publication Critical patent/WO2016000369A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Definitions

  • the present disclosure relates to a transmitting electrode scanning circuit, an array substrate, and a display device.
  • Embedded touch screen panel In-Cell TSP
  • the uppermost common electrode VCOM ITO
  • TX transmit
  • the TX drive signal on the VCOM ITO is added by the external drive IC through a fan-out structure located in the seal area.
  • the use of a fan-out emitter electrode is affected by the width of the seal region, which limits the application of the embedded (In-Cell) technology to large-size and narrow-frame panels.
  • the TX Fan-out is located above or below the gate integrated drive circuit (GOA) of the array substrate.
  • the signal crosstalk causes the emitter electrode and the GOA to interact with each other, which brings reliability problems of touch and panel display.
  • a transmitting electrode scanning circuit including a plurality of cascaded sub-scanning circuits, each of the sub-scanning circuits including a shift register unit, a scan signal generating unit, and a driving output unit; wherein:
  • the shift register unit is configured to shift the received start signal to obtain a start signal of the next-stage sub-scanning circuit and a transmit electrode drive control signal, and output a start signal of the next-stage sub-scan circuit Going to the shift register unit of the next sub-scanning circuit, outputting the obtained emitter electrode driving control signal to the scan signal generating unit;
  • the scan signal generating unit is connected to the emitter electrode driving signal line for generating according to the emitter electrode driving control signal received from the shift register unit and the emitter electrode driving signal received from the emitter electrode driving signal line Transmitting an electrode scan signal, and inputting the obtained emitter electrode scan signal to a scan signal input end of the drive output unit;
  • the driving output unit is configured to convert a high level of the received transmitting electrode scan signal into a transmitting electrode driving high level, and convert the low level of the transmitting electrode scanning signal into a transmitting electrode drive Move low and output to the emitter electrode.
  • the shift register unit is further configured to output an inverted signal of the emitter electrode driving control signal to the scan signal generating unit;
  • the scan signal generating unit includes five thin film field effect transistors, wherein the first thin film field effect transistor and the second thin film field effect transistor are P-channel thin film field effect transistors, third thin film field effect transistors, and fourth thin film field effect The transistor and the fifth thin film field effect transistor are N-channel type thin film field effect transistors; and,
  • the gates of the first thin film field effect transistor and the fifth thin film field effect transistor are connected to the inverted signal of the driving electrode driving control signal; the source of the first thin film field effect transistor is connected to the bias high level, the drain and the second The source of the thin film field effect transistor is connected; the source of the fifth thin film field effect transistor is connected to the output end of the scan signal generating unit, and the drain is connected to the bias low level;
  • the gates of the second thin film field effect transistor and the fourth thin film field effect transistor are both connected to the emitter driving signal line; the drain of the second thin film field effect transistor is connected to the output end of the scanning signal generating unit; the fourth thin film field The source of the effect transistor is connected to the bias low level, and the drain is connected to the source of the third thin film field effect transistor;
  • the gate of the third thin film field effect transistor is connected to the emitter electrode driving control signal, and the drain is connected to the output end of the scanning signal generating unit.
  • the shift register unit is further configured to output an inverted signal of the emitter electrode driving control signal to the scan signal generating unit;
  • the scan signal generating unit includes five thin film field effect transistors, wherein the first thin film field effect transistor and the second thin film field effect transistor are P-channel thin film field effect transistors, second thin film field effect transistors, and third thin film field effect The transistor and the fourth thin film field effect transistor are N-channel thin film field effect transistors; and
  • the gates of the first thin film field effect transistor and the third thin film field effect transistor are both connected to the emitter driving signal line; the source of the first thin film field effect transistor is connected to the bias high level, the drain and the second thin film field effect a source of the transistor is connected; a source of the third thin film field effect transistor is connected to a source of the fourth thin film field effect transistor, and a drain is connected to an output end of the scan signal generating unit;
  • the gates of the second thin film field effect transistor and the fifth thin film field effect transistor are connected to the inverted signal of the transmitting electrode driving control signal; the drain of the second thin film field effect transistor is connected to the output end of the scanning signal generating unit; The source of the five thin film field effect transistor is biased to a low level, and the drain is connected to the output of the scan signal generating unit.
  • the gate of the fourth thin film field effect transistor is connected to the emitter electrode to drive a control signal, and the source is connected to a bias low level.
  • the scan signal generating unit includes a NAND gate and an inverter; one input terminal of the NAND gate is connected to the transmitting electrode driving signal line, and the other input terminal is connected to the transmitting electrode driving control signal, The output end is connected to the input end of the inverting module; the output end of the inverting module is connected to the output end of the scan signal generating unit.
  • the drive output unit includes: two transmission gates,
  • the positive control end of the first transmission gate and the negative control end of the second transmission gate are all connected to the transmitting electrode scanning signal; the negative control end of the first transmission gate and the positive control end of the second transmission gate are both connected to the transmitting electrode scanning Inverted signal of the signal;
  • the output ends of the first transmission gate and the second transmission gate are both connected to the transmitting electrode; the voltage input end of the first transmission gate is connected to the transmitting electrode to drive the low level, and the voltage input end of the second transmission gate is connected to the transmitting electrode driving High level.
  • the driving output unit includes sixth, seventh, eighth, and ninth thin film field effect transistors, wherein the sixth thin film field effect transistor and the eighth thin film field effect transistor are two P-channel thin film field effects a transistor, a seventh thin film field effect transistor, and a ninth thin film field effect transistor are N-channel thin film field effect transistors; and
  • the gates of the sixth thin film field effect transistor and the seventh thin film field effect transistor are both connected to the output end of the scan signal generating unit; the source of the sixth thin film field effect transistor is driven to a high level, and the drain is connected to a drain of the seventh thin film field effect transistor; a source of the seventh thin film field effect transistor is driven to a low level;
  • the gates of the eighth thin film field effect transistor and the ninth thin film field effect transistor are both connected to the drain of the seventh thin film field effect transistor; the source of the eighth thin film field effect transistor is driven to a high level, and the drain is connected to The emitter electrode; the source of the ninth thin film field effect transistor is biased to a low level, and the drain is connected to the emitter electrode.
  • the present disclosure also provides an array substrate, comprising the emitter electrode scanning circuit of any of the above.
  • the emitter electrode scanning circuit is integrated in a frame seal region of the array substrate.
  • the common electrodes of the plurality of rows of pixels of the array substrate constitute a row of emitter electrodes.
  • the present disclosure also provides a display device comprising the array substrate of any of the above.
  • the transmitting electrode scanning circuit provided by the present disclosure includes a sub-scan of a plurality of shift register unit cascades In the circuit, each sub-scanning circuit respectively supplies a driving signal to the transmitting electrode, thereby avoiding introducing a plurality of driving signal lines from outside the array substrate. And the plurality of sub-scanning circuits share the transmitting electrode driving signal line and only need one initial signal input to drive the transmitting electrode scanning circuit to transmit the transmitting electrode driving signal row by row. Therefore, the emitter electrode scanning circuit of the present disclosure is suitable for integration into the frame sealant region of the array substrate, and does not need to provide a fan-out structure with a large number of input lines, which is advantageous for narrowing the display device, and avoids input lines and on the other hand. Crosstalk generated between gate voltage lines.
  • 1 is a schematic structural view of a known display panel
  • FIG. 2 is a schematic structural diagram of a transmitting electrode scanning circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of an external driving signal of a transmitting electrode scanning circuit and a GOA provided in an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a TX generating unit in a transmitting electrode scanning circuit according to an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of respective signals when a transmitting electrode scanning circuit is provided in an embodiment of the present disclosure
  • TX Scanner 6 is a timing diagram of each signal when another TX Scanner is provided in the embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of another TX generating unit in a transmitting electrode scanning circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another TX generating unit in a transmitting electrode scanning circuit provided in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a driving output unit in a transmitting electrode scanning circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another driving output unit in a transmitting electrode scanning circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of accessing an external driving signal in a display device provided in an embodiment of the present disclosure.
  • GOA_STV is the start signal of the GOA
  • GOA_CLK and GOA_CLKB are a pair of clock signals of the GOA that are inverted from each other;
  • TX Scanner is a transmitting electrode scanning circuit
  • TX_STV is the start signal of TX Scanner
  • TX_CLK and TX_CLKB are a pair of mutually inverted clock signals of the TX Scanner
  • TX_CN is a transmitting electrode driving control signal
  • /TX_CN is the inverted signal of TX_CN
  • TX is a transmitting electrode driving signal
  • TX_OUT is a transmitting electrode scan signal
  • /TX_OUT is the inverted signal of TX_OUT
  • TXCOM is the high level of the TX driving voltage
  • DCCOM is the low level of the TX drive voltage, which is equal to the DC common level of the LCD display
  • VGH is biased high
  • VGL is biased low
  • the TX Scan unit is a sub-scanning circuit of the TX Scanner
  • S/R is a shift register unit
  • TX_1, TX_2, TX_3, ... TX_n-1, TX_n, TX_n+1, ..., TX_last are corresponding row driving electrodes or driving signals;
  • COMOUT_1, COMOUT_2, COMOUT_3, ... COMOUT_n-1, COMOUT_n, COMOUT_n+1, ..., COMPUT_last_level are common electrode signals received by the corresponding row driving electrodes;
  • STV_OUT and TX_CN are signals obtained by shifting S/R to STV;
  • the high level of GOA_STV, GOA_CLK, GOA_CLKB, TX_STV, TX_CLK, TX_CLKB and TX signals is VGH, the low level is VGL, and VGL ⁇ DCCOM ⁇ TXCOM ⁇ VGH.
  • FIG. 1 is a schematic structural view of a known display panel. As shown in Figure 1, in a conventional design, the TX drive signal on the VCOM ITO is externally driven by a fan-out structure (Fan-out) located in the Seal area.
  • Fan-out fan-out structure
  • the circuit includes a plurality of cascaded sub-scanning circuits TX Scan unit, each of the sub-scanning circuits TX Scan unit includes a shift register unit S/R and a scan signal generating unit (TX generation And a drive output unit, the TX generation unit is connected to the shift register unit S/R and the drive output unit, respectively.
  • TX Scanner transmitting electrode scanning circuit
  • the shift register unit S/R is used to shift the received STV to obtain STV_OUT and TX_CN under the control of TX_CLK and TX_CLKB, and input STV_OUT to the next-stage sub-scanning circuit TX Scan unit
  • TX_CN is input as a transmitting electrode driving control signal into the TX generating unit;
  • the TX generating unit is a scan signal generating unit, configured to generate a transmit electrode scan signal TX_OUT according to TX_CN and TX;
  • the driving output unit is configured to convert the received high level signal of TX_OUT into TXCOM, and convert the low level signal of TX_OUT into DCCOM, and then output to the transmitting electrode.
  • VGL and VGH are generally the operating voltage of the circuit, and the value of the voltage is generally large, and driving the TX does not require such a large voltage. Therefore, it is converted to a lower voltage in the embodiment of the present disclosure.
  • the TXCOM here can be the voltage required to detect the IC, and the DCCOM can be the common electrode voltage.
  • the transmitting electrode scanning circuit provided in the embodiment of the present disclosure includes a plurality of sub-scanning circuits cascaded by shift registering units, each of which provides a driving signal to the transmitting electrodes, thereby avoiding introducing a plurality of driving signals from outside the array substrate. line. And the plurality of sub-scanning circuits share the transmitting electrode driving signal line and only need one initial signal input to drive the transmitting electrode scanning circuit to transmit the transmitting electrode driving signal row by row. Therefore, the emitter electrode scanning circuit of the embodiment of the present disclosure is suitable for integration into the frame sealant region of the array substrate, and does not need to provide a fan-out structure with a large number of input lines, which is advantageous for narrowing the display device and avoiding input on the other hand. Crosstalk between the line and the gate voltage line.
  • FIG 3 is a schematic diagram of an external driving signal integrated with a transmitting electrode scanning circuit and a gate drive (GOA) provided by the present disclosure.
  • GAA gate drive
  • TX_CLK and TX_CLKB input the clock square wave
  • TX_STV inputs the initial square wave signal
  • the transmitting electrode scanning circuit works, and continuously outputs the TX driving signal as the VCOM ITO of the TX electrode.
  • the drive signals TX_1, TX_2 to TX_n are outputted from COM_1 to COM_n line by line.
  • GOA_CLK, GOA_CLKB and GOA_STV are both maintained as VGL, DCCOM
  • TXCOM is the high level VDD required for RX detection of the driver IC. That is, the GOA circuit is suspended, and the emitter electrode scanning circuit outputs the TX driving signal to the VCOM ITO row by row.
  • a specific structure of the TX generating unit in the sub-scanning circuit TX Scan unit may include: five thin film field effect transistors (TFTs) T1, T2, T3, T4, T5, where T1, T2 In the case of a P-channel type TFT, T3, T4, and T5 are N-channel type TFTs.
  • TFTs thin film field effect transistors
  • the gates of T1 and T5 are both connected to the inverted signal /TX_CN; the source of T1 is connected to VGH, the drain is connected to the source of T2; the drain of T5 is connected to the output TX_OUT of the TX generating unit, The source is connected to the VGL;
  • T2 and T4 are both connected to the TX signal line; the drain of T2 is connected to the output terminal TX_OUT of the TX generating unit; the source of T4 is connected to VGL, and the drain is connected to the source of T3;
  • the gate of T3 is connected to TX_CN, and the drain is connected to the output of the TX generating unit.
  • an inverter can be set in the shift register unit S/R or TX generating unit to realize the inversion of the TX_CN to obtain the inverted signal /TX_CN, and then the inverted signal /TX_CN is connected to the T1 and T5.
  • FIG. 5 is a timing chart of respective signals when the sub-scanning circuit of the TX generating unit of FIG. 4 operates.
  • TX_CN is high level VGH
  • /TX_CN is low level VGL
  • T1 and T3 are turned on
  • T5 is turned off
  • the TX generating unit outputs high frequency scanning signal TX_OUT in the TX electrode scanning time by controlling T2 and T4.
  • the drive output unit converts the high and low levels of TX_OUT from VGH and VGL to TXCOM and DCCOM, and outputs them to the TX electrode.
  • FIG. 6 shows a waveform diagram of driving signals output to the respective TX electrodes (TX_1, TX_2, TX_3, ..., TX_n-1, TX_n).
  • each of the TX electrodes receives a common electrode signal (COMOUT_1, COMOUT_2, COMOUT_3, ..., COMOUT_n-1, COMOUT_n) in the display phase.
  • the shift register unit S/R is also used to output the inverted signal /TX_CN of TX_CN to the TX generating unit.
  • Fig. 7 shows another structural diagram of the TX generating unit. As shown in FIG. 7, the TX generating unit includes:
  • TFTs Five thin film field effect transistors (TFTs) T1, T2, T3, T4, T5, wherein T1, T2 are P-channel TFTs, and T3, T4, T5 are N-channel TFTs;
  • T1 and T3 are connected to the TX signal line; the source of T1 is connected to VGH, the drain is connected to the source of T2; the source of T3 is connected to the drain of T4, and the output of the drain and TX generating unit Connected
  • T2 and T5 are both connected to /TX_CN; the drain of T2 is connected to the output of the TX generating unit, the source of T5 is connected to VGL, and the drain is connected to the output of the TX generating unit;
  • T4 The gate of T4 is connected to TX_CN, and the source is connected to VGL.
  • TX_CN when TX_CN is high level VGH, /TX_CN is low level VGL, T4 and T2 are turned on, T5 is turned off, TX passes control T1 and T3, and outputs high frequency during TX electrode scan time. Scan signal TX_OUT. After the TX_OUT is input to the drive output unit, the drive output unit converts the high and low levels of TX_OUT from VGH and VGL to TXCOM and DCCOM, and outputs them to the TX electrode.
  • the shift register unit S/R can also output only TX_CN.
  • FIG. 8 is a diagram showing the structure of a TX generating unit when the shift register unit S/R outputs only TX_CN.
  • the TX generating unit includes: a NAND gate NAND1 and an inverting module INV1; one input terminal of the NAND1 is connected to the TX signal line, the other input terminal is connected to the TX_CN, and the output terminal/TX_OUT is connected to The input of INV1; the output of INV1 is connected to the output TX_OUT of the TX generating unit.
  • the working principle of the circuit is: when TX_CN is high, the high frequency TX signal outputs TX_OUT through NAND1 and INV1, and when TX_CN is low, the high frequency TX signal is not output.
  • FIG. 9 is a schematic structural diagram of a driving output unit in a transmitting electrode scanning circuit according to an embodiment of the present disclosure.
  • an exemplary structure of the drive output unit of FIG. 2 may include: two transfer gates TR1 and TR2,
  • the positive control terminal of TR1 and the negative control terminal of TR2 are both connected to TX_OUT; the negative control terminal of TR1 and the positive control terminal of TR2 are both connected to the inverted signal of TX_OUT/TX_OUT;
  • TR1 and TR2 are connected to the transmitting electrode (ie, output TX driving signal or common electrode signal COMOUT); the voltage input terminal of TR1 is connected to DCCOM, and the voltage input terminal of TR2 is connected to TXCOM.
  • the driving output unit works as follows: When TX_OUT and /TX_OUT input high frequency TX drive control signals, TR1 and TR2 are alternately turned on, and high-low level TXC and DCCOM high-frequency TX drive square wave signals are output; when TX drive When the control signals TX_OUT and /TX_OUT are input to VGH and VGL, respectively, TR1 is turned on, TR2 is turned off, and the output terminal outputs DCCOM level.
  • the driving output unit is the structure shown in FIG. 9, the corresponding TX generating unit may be the TX generating unit described in FIG. Alternatively, as shown in FIG. 4 or FIG. 7, an additional inverter needs to be added to the circuit to provide TX_OUT and /TX_OUT for the drive output unit shown in FIG.
  • FIG. 10 is a schematic structural diagram of another driving output unit in a transmitting electrode scanning circuit according to an embodiment of the present disclosure.
  • another exemplary structure of the driving output unit in FIG. 2 may include: four TFTs, that is, T6, T7, T8, and T9, wherein T6 and T8 are P-channel TFTs, T7 and T9 is an N-channel type TFT;
  • the gates of T6 and T7 are both connected to the output end of the TX generating unit; the source of T6 is connected to VGH, the drain is connected to the drain of T7; the source of T7 is connected to VGL;
  • T8 and T9 are connected to the source of T7; the source of T8 is connected to TXCOM, the drain is connected to the emitter electrode; the source of T9 is connected to DCCOM, and the drain is connected to the emitter electrode (ie, the output TX drive) Signal or common electrode signal COMOUT).
  • T6 and T7 constitute the first stage of the buffer inverter, its working high and low level is VGH and VGL, where T8 and T9 constitute the second stage of the output drive inverter, its working high and low level is TXCOM and DCCOM .
  • TX_OUT drives the inverter through the buffer inverter and the output, the high-frequency TX-driven square wave signals of TXCOM and DCCOM are output to the emitter electrode.
  • the TX generating unit may select the TX generating unit described in any of the above. Regardless of whether the input signal is TX_OUT or /TX_OUT, the drive output unit can supply the drive voltage to the TX according to the input signal.
  • the present disclosure also provides an array substrate including the above-described emitter electrode scanning circuit.
  • FIG. 11 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.
  • the emitter electrode scanning circuit is integrated in the sealant seal region of the array substrate Array.
  • Fig. 12 is a diagram showing the access of an external driving signal integrated with a transmitting electrode scanning circuit and a GOA.
  • the gate drive external inputs (GOA_CLK, GOA_CLKB, GOA_STV) are output to the array substrate through the GOA, and the external inputs (TX_CLK, TX_CLKB, TX_STV, TX, TXCOM, DCCOM) of the emitter electrode scan circuit pass through the emitter electrode.
  • the scan circuit outputs to the array substrate.
  • the external input of the transmitting electrode scanning circuit includes only the six signals in the figure, that is, only the six signal lines can be used to drive the transmitting electrode scanning circuit to the transmitting electrode (TX1). , TX2 ... TXn) Supply Tx drive signal, which can realize the narrowing of the panel and reduce the crosstalk with the control line of the GOA.
  • the common electrodes of the plurality of rows of pixels of the array substrate correspond to a row of emitter electrodes.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • the display device can be any product or component having display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.

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Abstract

提供了一种发射电极扫描电路、阵列基板及显示装置。该发射电极扫描电路包括多个级联的子扫描电路，每一个子扫描电路包括移位寄存单元、扫描信号生成单元和驱动输出单元。每个子扫描电路分别向发射电极提供驱动信号，这样就避免从阵列基板外引入多条驱动信号线。并且多个子扫描电路共用发射电极驱动信号线且只需要一个起始信号输入即可驱动发射电极扫描电路逐行发送发射电极驱动信号。该发射电极扫描电路适于集成到阵列基板的封框胶区域，不需要设置输入线路繁多的扇出结构，有利于实现显示装置的窄边化，另一方面也避免了输入线路与栅极电压线之间产生的串扰。

Description

发射电极扫描电路、阵列基板和显示装置 技术领域
本公开涉及一种发射电极扫描电路、阵列基板和显示装置。
背景技术
嵌入式触摸屏面板(In-Cell TSP)技术是目前TSP技术发展的重要方向。在嵌入式触摸屏面板中，通常使用最上层的公共电极(VCOM ITO)作发射(TX)电极。而传统设计中VCOM ITO上的TX驱动信号是外部驱动IC通过位于封框胶(Seal)区域的扇出结构(Fan-out)加入的。
随着面板(Panel)尺寸增大，发射电极数量将增多，则发射扇出结构(TX Fan-out)的布置需要更多空间。因此，采用扇出(Fan-out)方式的发射电极，受封框胶(Seal)区域宽度等影响，限制了嵌入式(In-Cell)技术在大尺寸和窄边框面板上的应用。另外发射扇出结构(TX Fan-out)位于阵列基板栅极集成驱动电路(GOA)上方或下方，信号串扰造成发射电极和GOA相互影响，带来触摸(Touch)和面板显示的可靠性问题。
发明内容
在本公开实施例中提供了一种发射电极扫描电路，包括多个级联的子扫描电路，每一个子扫描电路包括移位寄存单元、扫描信号生成单元和驱动输出单元；其中：
所述移位寄存单元，用于对接收到的起始信号进行移位得到下一级子扫描电路的起始信号以及发射电极驱动控制信号，并将下一级子扫描电路的起始信号输出到下一级子扫描电路的移位寄存单元，将得到的发射电极驱动控制信号输出到所述扫描信号生成单元；
所述扫描信号生成单元，与发射电极驱动信号线相连，用于根据从所述移位寄存单元接收到的发射电极驱动控制信号和从所述发射电极驱动信号线接收到的发射电极驱动信号生成发射电极扫描信号，并将得到的发射电极扫描信号输入到所述驱动输出单元的扫描信号输入端；
所述驱动输出单元，用于将接收到的发射电极扫描信号的高电平转换为发射电极驱动高电平，将所述发射电极扫描信号的低电平转换为发射电极驱 动低电平，并输出到发射电极。
可替换地，所述移位寄存单元还用于将发射电极驱动控制信号的反相信号输出到所述扫描信号生成单元；
所述扫描信号生成单元包括五个薄膜场效应晶体管，其中第一薄膜场效应晶体管和第二薄膜场效应晶体管为P沟道型薄膜场效应晶体管，第三薄膜场效应晶体管、第四薄膜场效应晶体管和第五薄膜场效应晶体管为N沟道型薄膜场效应晶体管；并且，
第一薄膜场效应晶体管和第五薄膜场效应晶体管的栅极接入发射电极驱动控制信号的反相信号；第一薄膜场效应晶体管的源极接入偏置高电平，漏极与第二薄膜场效应晶体管的源极相连；第五薄膜场效应晶体管的源极与所述扫描信号生成单元的输出端相连，漏极接入偏置低电平；
第二薄膜场效应晶体管和第四薄膜场效应晶体管的栅极均与发射电极驱动信号线相连；第二薄膜场效应晶体管的漏极连接到所述扫描信号生成单元的输出端；第四薄膜场效应晶体管的源极接入偏置低电平，漏极接入第三薄膜场效应晶体管的源极；
第三薄膜场效应晶体管的栅极接入发射电极驱动控制信号，漏极与所述扫描信号生成单元的输出端相连。
可替换地，所述移位寄存单元还用于将发射电极驱动控制信号的反相信号输出到所述扫描信号生成单元；
所述扫描信号生成单元包括五个薄膜场效应晶体管，其中第一薄膜场效应晶体管和第二薄膜场效应晶体管为P沟道型薄膜场效应晶体管，第二薄膜场效应晶体管、第三薄膜场效应晶体管、第四薄膜场效应晶体管为N型沟道薄膜场效应晶体管；并且，
第一薄膜场效应晶体管和第三薄膜场效应晶体管的栅极均与发射电极驱动信号线相连；第一薄膜场效应晶体管的源极接入偏置高电平，漏极与第二薄膜场效应晶体管的源极相连；第三薄膜场效应晶体管的源极与第四薄膜场效应晶体管的源极相连，漏极与所述扫描信号生成单元的输出端相连；
第二薄膜场效应晶体管和第五薄膜场效应晶体管的栅极接入发射电极驱动控制信号的反相信号；第二薄膜场效应晶体管的漏极与所述扫描信号生成单元的输出端相连；第五薄膜场效应晶体管的源极接入偏置低电平，漏极与所述扫描信号生成单元的输出端相连。
第四薄膜场效应晶体管的栅极接入发射电极驱动控制信号，源极接入偏置低电平。
可替换地，所述扫描信号生成单元包括一个与非门和一个反相器；所述与非门的一个输入端与发射电极驱动信号线相连，另一输入端接入发射电极驱动控制信号，输出端接入到反相模块的输入端；反相模块的输出端接入到所述扫描信号生成单元的输出端。
可替换地，所述驱动输出单元包括：两个传输门，
其中，第一传输门的正控制端、第二传输门的负控制端均接入发射电极扫描信号；第一传输门的负控制端和第二传输门的正控制端均接入发射电极扫描信号的反相信号；
第一传输门和第二传输门的输出端均与所述发射电极相连；第一传输门的电压输入端连接到发射电极驱动低电平，第二传输门的电压输入端接入发射电极驱动高电平。
可替换地，所述驱动输出单元包括第六、第七、第八、第九薄膜场效应晶体管，其中第六薄膜场效应晶体管和第八薄膜场效应晶体管为两个P沟道型薄膜场效应晶体管，第七薄膜场效应晶体管和第九薄膜场效应晶体管为N沟道型薄膜场效应晶体管；并且，
第六薄膜场效应晶体管和第七薄膜场效应晶体管的栅极均接入所述扫描信号生成单元的输出端；第六薄膜场效应晶体管的源极接入驱动高电平，漏极接入到第七薄膜场效应晶体管的漏极；第七薄膜场效应晶体管的源极接入驱动低电平；
第八薄膜场效应晶体管和第九薄膜场效应晶体管的栅极均连接到第七薄膜场效应晶体管的漏极；第八薄膜场效应晶体管的源极接入驱动高电平，漏极接入到发射电极；第九薄膜场效应晶体管的源极接入偏置低电平，漏极接入到发射电极。
本公开还提供了一种阵列基板，其中，包括上述任一项所述的发射电极扫描电路。
可替换地，所述发射电极扫描电路集成在所述阵列基板的封框胶区域。
可替换地，所述阵列基板的多行像素的公共电极构成一行发射电极。
本公开还提供了一种显示装置，其中，包括上述任一项所述的阵列基板。
本公开提供的发射电极扫描电路中，包括多个移位寄存单元级联的子扫 描电路，每个子扫描电路分别向发射电极提供驱动信号，这样就避免从阵列基板外引入多条驱动信号线。并且多个子扫描电路共用发射电极驱动信号线且只需要一个起始信号输入即可驱动发射电极扫描电路逐行发送发射电极驱动信号。从而本公开的发射电极扫描电路适于集成到阵列基板的封框胶区域，不需要设置输入线路繁多的扇出结构，有利于实现显示装置的窄边化，另一方面也避免了输入线路与栅极电压线之间产生的串扰。
附图说明
图1为已知的显示面板的结构示意图；
图2为本公开实施例中提供的一种发射电极扫描电路的结构示意图；
图3为本公开实施例中提供的发射电极扫描电路和GOA的外部驱动信号示意图；
图4为本公开实施例中提供的发射电极扫描电路中一种TX产生单元的结构示意图；
图5为本公开实施例中提供的一种发射电极扫描电路工作时各个信号的时序图；
图6为本公开实施例中提供的另一种TX Scanner工作时各个信号的时序图；
图7为本公开实施例中提供的发射电极扫描电路中另一种TX产生单元的结构示意图；
图8本公开实施例中提供的发射电极扫描电路中另一种TX产生单元的结构示意图；
图9为本公开实施例中提供的发射电极扫描电路中一种驱动输出单元的结构示意图；
图10为本公开实施例中提供的发射电极扫描电路中另一种驱动输出单元的结构示意图；
图11为本公开实施例中提供的显示装置的结构示意图；
图12为本公开实施例中提供的显示装置中外部驱动信号的接入示意图。
具体实施方式
下面结合附图对本公开的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本公开的技术方案，而不能以此来限制本公开的保护范围。
为了便于描述，首先对本公开中所涉及的一些术语进行说明：
GOA_STV为GOA的起始信号；
GOA_CLK和GOA_CLKB为GOA的一对彼此反相的时钟信号；
TX Scanner为发射电极扫描电路；
TX_STV为TX Scanner的起始信号；
TX_CLK和TX_CLKB为TX Scanner的一对彼此反相的时钟信号；
TX_CN为发射电极驱动控制信号；
/TX_CN为TX_CN的反相信号；
TX为发射电极驱动信号；
TX_OUT为发射电极扫描信号；
/TX_OUT为TX_OUT的反相信号；
TXCOM为TX驱动电压的高电平；
DCCOM为TX驱动电压的低电平，等于LCD显示的直流公共电平；
VGH为偏置高电平；
VGL为偏置低电平；
TX Scan unit为TX Scanner的一个子扫描电路；
S/R为移位寄存单元；
TX_1、TX_2、TX_3……TX_n-1、TX_n、TX_n+1、……、TX_last为对应行驱动电极或驱动信号；
COMOUT_1、COMOUT_2、COMOUT_3……COMOUT_n-1、COMOUT_n、COMOUT_n+1、……、COMPUT_last_level为对应行驱动电极接收的公共电极信号；
其中STV_OUT和TX_CN为S/R对STV移位得到的信号；
其中GOA_STV，GOA_CLK，GOA_CLKB，TX_STV，TX_CLK，TX_CLKB和TX信号的高电平为VGH，低电平为VGL，且VGL<DCCOM<TXCOM<VGH。
图1为已知的显示面板的结构示意图。如图1所示，在传统设计中，VCOM ITO上的TX驱动信号是外部驱动IC通过位于封框胶(Seal)区域的扇出结构(Fan-out)加入的。
图2为本公开实施例中提供的发射电极扫描电路(TX Scanner)的结构示意图。如图2所示，该电路包括多个级联的子扫描电路TX Scan unit，每一个子扫描电路TX Scan unit包括移位寄存单元S/R、扫描信号生成单元(TX产生 单元)和驱动输出单元，TX产生单元分别与移位寄存单元S/R和所述驱动输出单元相连。
在图2电路中，移位寄存单元S/R用于在TX_CLK和TX_CLKB的控制下，对接收到的STV进行移位得到STV_OUT以及TX_CN，并将STV_OUT输入到下一级子扫描电路TX Scan unit中作为下一级的子扫描电路TX Scan unit的STV，将TX_CN作为发射电极驱动控制信号输入到TX产生单元中；
TX产生单元为扫描信号生成单元，用于根据TX_CN和TX生成发射电极扫描信号TX_OUT；
驱动输出单元用于将接收到的TX_OUT的高电平信号转换为TXCOM，并将TX_OUT的低电平信号转换为DCCOM，之后输出到发射电极。
实际应用中，VGL和VGH一般为电路的工作电压，电压的值一般较大，而驱动TX并不需要这么大的电压。因此，本公开实施例中将其转换为一个较低的电压。这里的TXCOM可以为检测IC所需的电压，DCCOM可以为公共电极电压。
本公开实施例中提供的发射电极扫描电路，包括多个移位寄存单元级联的子扫描电路，每个子扫描电路分别向发射电极提供驱动信号，这样就避免从阵列基板外引入多条驱动信号线。并且多个子扫描电路共用发射电极驱动信号线且只需要一个起始信号输入即可驱动发射电极扫描电路逐行发送发射电极驱动信号。从而本公开实施例的发射电极扫描电路适于集成到阵列基板的封框胶区域，不需要设置输入线路繁多的扇出结构，有利于实现显示装置的窄边化，另一方面也避免了输入线路与栅极电压线之间产生的串扰。
图3为集成了本公开提供的发射电极扫描电路和栅极驱动(GOA)的外部驱动信号示意图。
如图3所示，在LCD显示阶段(图中所示的LCD Pixel charging)，GOA_CLK和GOA_CLKB输入时钟方波，GOA_STV输入起始方波信号，GOA工作，SD(源漏)线输入像素灰阶电压，面板Panel进行一帧画面的刷新。在这个阶段，TX_CLK，TX_CLKB，TX_STV，TX均保持为VGL，DCCOM和TXCOM均保持为COM电压，即发射电极扫描电路暂停工作，VCOM ITO输出COM直流电压。
在Touch检测阶段(图中所示的TSP Tx scanning)，TX_CLK和TX_CLKB输入时钟方波，TX_STV输入起始方波信号，发射电极扫描电路工作，持续输出TX驱动信号，作为TX电极的VCOM ITO，从COM_1到COM_n逐行输出驱动信号TX_1，TX_2到TX_n。本阶段GOA_CLK，GOA_CLKB和GOA_STV均保持为VGL，DCCOM 为COM电平，TXCOM为驱动IC的RX检测所需高电平VDD。即GOA电路暂停工作，发射电极扫描电路逐行输出TX驱动信号到VCOM ITO。
一种示例性的可选方案是，移位寄存单元S/R还用于将TX_CN的反相信号/TX_CN输出到TX产生单元。此时，如图4所示，子扫描电路TX Scan unit中TX产生单元的一种具体结构可以包括：五个薄膜场效应晶体管(TFT)T1、T2、T3、T4、T5，其中T1、T2为P沟道型TFT，T3、T4、T5为N沟道型TFT。
图4中，T1和T5的栅极均接入反相信号/TX_CN；T1的源极接入VGH，漏极与T2的源极相连；T5的漏极与TX产生单元的输出端TX_OUT相连，源极接入VGL；
T2和T4的栅极均与TX信号线相连；T2的漏极连接到TX产生单元的输出端TX_OUT；T4的源极接入VGL，漏极连接T3的源极；
T3的栅极接入TX_CN，漏极与TX产生单元的输出端相连。
实际应用中，可以在移位寄存单元S/R或TX产生单元中设置一个反相器，实现对TX_CN的反相得到反相信号/TX_CN，之后将反相信号/TX_CN接入到T1和T5的栅极，并将TX_CN接入到T3的栅极。
图5为图4中的TX产生单元的子扫描电路工作时，各个信号的时序图。当TX_CN为高电平VGH，/TX_CN为低电平VGL时，T1和T3导通，T5截止，TX产生单元通过控制T2和T4，在TX电极扫描时间内输出高频率的扫描信号TX_OUT。TX_OUT输入到驱动输出单元后，驱动输出单元将TX_OUT的高低电平由VGH和VGL转换为TXCOM和DCCOM，并输出给TX电极。
图6示出输出到各个TX电极(TX_1、TX_2、TX_3……TX_n-1、TX_n)的驱动信号的波形图。如图6所示，在显示阶段各个TX电极对应接收公共电极信号(COMOUT_1、COMOUT_2、COMOUT_3……COMOUT_n-1、COMOUT_n)。
移位寄存单元S/R还用于将TX_CN的反相信号/TX_CN输出到TX产生单元。
图7示出TX产生单元的另一种结构示意图。如图7所示，该TX产生单元包括：
五个薄膜场效应晶体管(TFT)T1、T2、T3、T4、T5，其中T1、T2为P沟道型TFT，T3、T4、T5为N沟道型TFT；
T1和T3的栅极均与TX信号线相连；T1的源极接入VGH，漏极与T2的源极相连；T3的源极与T4的漏极相连，漏极与TX产生单元的输出端相连；
T2和T5的栅极均接入/TX_CN；T2的漏极与TX产生单元的输出端相连，T5的源极入VGL，漏极与TX产生单元的输出端相连；
T4的栅极接入TX_CN，源极接入VGL。
采用图7所示的结构，当TX_CN为高电平VGH，/TX_CN为低电平VGL时，T4和T2导通，T5截止，TX通过控制T1和T3，在TX电极扫描时间内输出高频率的扫描信号TX_OUT。TX_OUT输入到驱动输出单元后，驱动输出单元将TX_OUT的高低电平由VGH和VGL转换为TXCOM和DCCOM，并输出给TX电极。
当然，移位寄存单元S/R也可以仅输出TX_CN。
图8示出移位寄存单元S/R仅输出TX_CN时的TX产生单元的结构示意图。如图8所示，该TX产生单元包括：一个与非门NAND1和一个反相模块INV1；NAND1的一个输入端与TX信号线相连，另一输入端接入TX_CN，输出端/TX_OUT接入到INV1的输入端；INV1的输出端接入到TX产生单元的输出端TX_OUT。
此时，该电路的工作原理为：当TX_CN为高电平时，高频率的TX信号通过NAND1和INV1输出TX_OUT，当TX_CN为低电平时，高频率的TX信号不会被输出。
图9为本公开实施例中提供的发射电极扫描电路中一种驱动输出单元的结构示意图。如图9所示，图2中的驱动输出单元的一种示例性的结构可以包括：两个传输门TR1和TR2，
其中，TR1的正控制端和TR2的负控制端均接入TX_OUT；TR1的负控制端和TR2的正控制端均接入TX_OUT的反相信号/TX_OUT；
TR1和TR2的输出端均与发射电极相连(即输出TX驱动信号或公共电极信号COMOUT)；TR1的电压输入端连接到DCCOM，TR2的电压输入端接入TXCOM。
该驱动输出单元的工作原理为：当TX_OUT和/TX_OUT输入高频率TX驱动控制信号时，TR1和TR2交替导通，输出高低电平为TXCOM和DCCOM的高频率TX驱动方波信号；当TX驱动控制信号TX_OUT和/TX_OUT分别输入VGH和VGL时，TR1开启，TR2关闭，输出端输出DCCOM电平。
需要指出的是，当驱动输出单元为图9所示的结构时，对应的TX产生单元可以为图8中所述的TX生成单元。或者，也可以选用图4或图7中的，此时需要在电路中额外的添加一个反相器，以为图9中所示的驱动输出单元提供TX_OUT和/TX_OUT。
图10为本公开实施例中提供的发射电极扫描电路中另一种驱动输出单元的结构示意图。如图10所示，图2中的驱动输出单元另外一种示例性的结构可以包括：四个TFT，即T6、T7、T8、T9，其中T6和T8为P沟道型TFT，T7和第T9为N沟道型TFT；
其中，T6和T7的栅极均接入TX产生单元的输出端；T6的源极接入VGH，漏极接入到T7的漏极；T7的源极接入VGL；
T8和T9的栅极均连接到T7的源极；T8的源极接入TXCOM，漏极接入到发射电极；T9的源极接入DCCOM，漏极接入到发射电极(即输出TX驱动信号或公共电极信号COMOUT)。
这样相当于T6和T7组成第一级的缓冲反相器，其工作高低电平为VGH和VGL，其中T8和T9组成第二级的输出驱动反相器，其工作高低电平为TXCOM和DCCOM。TX_OUT通过缓冲反相器和输出驱动反相器后，输出高低电平分别为TXCOM和DCCOM的高频率TX驱动方波信号到发射电极。
不难理解，当驱动输出单元选用如图10所示的结构时，TX产生单元可以选用上述任一项所述的TX产生单元。不管是输入的信号是TX_OUT还是/TX_OUT，驱动输出单元都能够根据输入的信号为TX提供驱动电压。
基于相同的构思，本公开还提供了一种阵列基板，包括上述的发射电极扫描电路。
图11为本公开实施例中提供的显示装置的结构示意图。
示例性地，如图11所示，发射电极扫描电路集成在阵列基板Array的封框胶Seal区域。
图12示出了集成有发射电极扫描电路和GOA的外部驱动信号的接入示意图。如12所示，栅极驱动的外部输入(GOA_CLK、GOA_CLKB、GOA_STV)均通过GOA输出到阵列基板上，发射电极扫描电路的外部输入(TX_CLK、TX_CLKB、TX_STV、TX、TXCOM、DCCOM)通过发射电极扫描电路输出到阵列基板上。与图1对比可以看出，不管面板有多大，发射电极扫描电路的外部输入都仅包括图中的六个信号，也就是说仅使用六条信号线即可驱动发射电极扫描电路向发射电极(TX1、TX2……TXn)供应Tx驱动信号，可实现面板的窄边化，并减少与GOA的控制线的串扰。
示例性地，所述阵列基板的多行像素的公共电极对应于一行发射电极。
本公开实施例还提供了一种显示装置，包括上述的阵列基板。
显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本公开的示例性实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改 进和润饰，这些改进和润饰也应视为本公开的保护范围。
本申请要求于2014年7月4日递交的中国专利申请第201410318306.1号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (10)

  1. 一种发射电极扫描电路，包括多个级联的子扫描电路，每一个子扫描电路包括：
    移位寄存单元，用于对接收到的起始信号进行移位得到下一级子扫描电路的起始信号以及发射电极驱动控制信号，并将下一级子扫描电路的起始信号输出到下一级子扫描电路的移位寄存单元；
    扫描信号生成单元，与发射电极驱动信号线相连，用于根据从所述移位寄存单元接收到的发射电极驱动控制信号和从所述发射电极驱动信号线接收到的发射电极驱动信号生成发射电极扫描信号；
    驱动输出单元，用于从所述扫描信号生成单元接收发射电极扫描信号，并将接收到的发射电极扫描信号的高电平转换为发射电极驱动高电平，将所述发射电极扫描信号的低电平转换为发射电极驱动低电平，并输出到发射电极。
  2. 如权利要求1所述的发射电极扫描电路，其中，所述移位寄存单元还用于将发射电极驱动控制信号的反相信号输出到所述扫描信号生成单元；
    所述扫描信号生成单元包括五个薄膜场效应晶体管，其中第一薄膜场效应晶体管和第二薄膜场效应晶体管为P沟道型薄膜场效应晶体管，第三薄膜场效应晶体管、第四薄膜场效应晶体管和第五薄膜场效应晶体管为N沟道型薄膜场效应晶体管；并且，
    第一薄膜场效应晶体管和第五薄膜场效应晶体管的栅极接入发射电极驱动控制信号的反相信号；第一薄膜场效应晶体管的源极接入偏置高电平，漏极与第二薄膜场效应晶体管的源极相连；第五薄膜场效应晶体管的源极与所述扫描信号生成单元的输出端相连，漏极接入偏置低电平；
    第二薄膜场效应晶体管和第四薄膜场效应晶体管的栅极均与发射电极驱动信号线相连；第二薄膜场效应晶体管的漏极连接到所述扫描信号生成单元的输出端；第四薄膜场效应晶体管的源极接入偏置低电平，漏极接入第三薄膜场效应晶体管的源极；
    第三薄膜场效应晶体管的栅极接入发射电极驱动控制信号，漏极与所述扫描信号生成单元的输出端相连。
  3. 如权利要求1所述的发射电极扫描电路，其中，
    所述移位寄存单元还用于将发射电极驱动控制信号的反相信号输出到所述扫描信号生成单元；
    所述扫描信号生成单元包括五个薄膜场效应晶体管，其中第一薄膜场效应晶体管和第二薄膜场效应晶体管为P沟道型薄膜场效应晶体管，第二薄膜场效应晶体管、第三薄膜场效应晶体管、第四薄膜场效应晶体管为N型沟道薄膜场效应晶体管；并且，
    第一薄膜场效应晶体管和第三薄膜场效应晶体管的栅极均与发射电极驱动信号线相连；第一薄膜场效应晶体管的源极接入偏置高电平，漏极与第二薄膜场效应晶体管的源极相连；第三薄膜场效应晶体管的源极与第四薄膜场效应晶体管的源极相连，漏极与所述扫描信号生成单元的输出端相连；
    第二薄膜场效应晶体管和第五薄膜场效应晶体管的栅极接入发射电极驱动控制信号的反相信号；第二薄膜场效应晶体管的漏极与所述扫描信号生成单元的输出端相连；第五薄膜场效应晶体管的源极接入偏置低电平，漏极与所述扫描信号生成单元的输出端相连；
    第四薄膜场效应晶体管的栅极接入发射电极驱动控制信号，源极接入偏置低电平。
  4. 如权利要求1所述的发射电极扫描电路，其中，
    所述扫描信号生成单元包括一个与非门和一个反相器；所述与非门的一个输入端与发射电极驱动信号线相连，另一输入端接入发射电极驱动控制信号，输出端接入到反相模块的输入端；反相模块的输出端接入到所述扫描信号生成单元的输出端。
  5. 如权利要求1-4之一所述的发射电极扫描电路，其中，所述驱动输出单元包括：两个传输门，
    其中，第一传输门的正控制端、第二传输门的负控制端均接入发射电极扫描信号；第一传输门的负控制端和第二传输门的正控制端均接入发射电极扫描信号的反相信号；
    第一传输门和第二传输门的输出端均与所述发射电极相连；第一传输门的电压输入端连接到发射电极驱动低电平，第二传输门的电压输入端接入发射电极驱动高电平。
  6. 如权利要求1-4之一所述的发射电极扫描电路，其中，所述驱动输出单 元包括第六、第七、第八、第九薄膜场效应晶体管，其中第六薄膜场效应晶体管和第八薄膜场效应晶体管为两个P沟道型薄膜场效应晶体管，第七薄膜场效应晶体管和第九薄膜场效应晶体管为N沟道型薄膜场效应晶体管；并且，
    第六薄膜场效应晶体管和第七薄膜场效应晶体管的栅极均接入所述扫描信号生成单元的输出端；第六薄膜场效应晶体管的源极接入驱动高电平，漏极接入到第七薄膜场效应晶体管的漏极；第七薄膜场效应晶体管的源极接入驱动低电平；
    第八薄膜场效应晶体管和第九薄膜场效应晶体管的栅极均连接到第七薄膜场效应晶体管的漏极；第八薄膜场效应晶体管的源极接入驱动高电平，漏极接入到发射电极；第九薄膜场效应晶体管的源极接入偏置低电平，漏极接入到发射电极。
  7. 一种阵列基板，包括如权利要求1-6任一项所述的发射电极扫描电路。
  8. 如权利要求7所述的阵列基板，其中，所述发射电极扫描电路集成在所述阵列基板的封框胶区域。
  9. 如权利要求7或8所述的阵列基板，其中，所述阵列基板的多行像素的公共电极构成一行发射电极。
  10. 一种显示装置，包括如权利要求7-9任一项所述的阵列基板。
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