WO2014192077A1

WO2014192077A1 - Authentication processing device and authentication processing method

Info

Publication number: WO2014192077A1
Application number: PCT/JP2013/064747
Authority: WO
Inventors: 孝一清水
Original assignee: 三菱電機株式会社
Priority date: 2013-05-28
Filing date: 2013-05-28
Publication date: 2014-12-04
Also published as: TW201445349A

Abstract

An authentication processing device is provided with an authentication circuit for using a PUF circuit to determine whether a semiconductor device under authentication is an authentic device on the basis of responses, which are unique information, to challenge inputs. The authentication circuit stores authentic-device responses to challenge inputs to an authentic device and an authentic-device error rate, which is the rate at which authentic-device responses are not obtained in response to repeated challenge inputs to an authentic device, in advance in a database. At the time of the authentication of the device under authentication, the authentication circuit calculates, on the basis of the authentic-device responses stored in the database, the error rate of the device under authentication for a sequence of responses generated for N challenge repetitions and determines that the device under authentication is an authentic device if the calculated error rate is within a permissible range that includes the authentic-device error rate.

Description

Authentication processing apparatus and authentication processing method

The present invention relates to an authentication processing apparatus and an authentication processing method for determining that a device is a genuine product manufactured by an authorized manufacturer.

模倣 Imitation of product equipment is a problem. Various damages to legitimate manufacturers have occurred, such as the loss of sales by cheap counterfeit products, or a decline in brand image due to poor counterfeit products. In addition, for example, counterfeit goods that do not function properly, such as airbags that do not open, may threaten consumer safety. Against this background, it is becoming increasingly important to prevent counterfeits.

In order to prevent such counterfeits, a procedure for confirming that the device is genuine can be considered when the device is operating. In particular, authentication using cryptographic processing is difficult to imitate and has high security, and is widely used for the purpose of determining genuine products. However, with the recent increase in analysis technology, there has been a risk that the function of a device such as an LSI that performs authentication processing will be copied or the circuit itself will be copied. Against this background, techniques that enable some countermeasures are becoming important along with techniques that prevent imitation itself, even if imitation is allowed.

There is a conventional authentication method that can detect a counterfeit product even if the device is copied (see, for example, Patent Document 1). Patent Document 1 proposes a method for distinguishing between a genuine product and a counterfeit product by confirming whether the time required for the authentication process of the device is within a predetermined range. The counterfeit product uses a device having a lower grade than the regular product or an inexpensive microcomputer, and therefore tends to have a longer processing time than the regular product. Therefore, even if the function is completely imitated, counterfeits with a long processing time can be eliminated.

In addition, as an authentication method that can counter the copy of the circuit itself, there is a method of authenticating a genuine product using a response of Physical Unclonable Function (PUF) (for example, see Patent Document 2). The PUF is a function whose behavior is determined according to a different physical quantity for each individual device, and an output (response) different for each device is generated for a given input (challenge). Therefore, even if the circuit is copied, the response output by the counterfeit product is different from that of the regular product, and thus it is possible to detect the counterfeit product.

JP 2012-174195 A JP 2011-123909 A

However, the following problems remain in the method of Patent Document 1 and the method of using a PUF represented by Patent Document 2. In the method of Patent Document 1, the processing time can be observed from the outside, and the attacker can know the processing time relatively easily. However, since it is assumed that the counterfeit product uses a low-grade device, the high-speed processing time of the genuine product is not imitated. However, as time elapses from the product launch, the device price decreases, and there is a possibility that a device of the same grade as the genuine product can be used at low cost. As a result, a counterfeit product that imitates the processing time may be produced.

Also, it is known that some existing PUFs as disclosed in Patent Document 2 can be attacked by machine learning. That is, by modeling the PUF, the behavior of the device-specific PUF can be expressed as a model parameter, and the parameter can be obtained by machine learning. As a result, a device-specific response to the challenge can be calculated with a software model. As described above, there is a possibility that a counterfeit product is made even by a method using the PUF.

The present invention has been made to solve the above-described problems. Even when a device function, a circuit itself, or a device-specific behavior such as a PUF is copied, it is still imitated. It is an object of the present invention to obtain an authentication processing apparatus and an authentication processing method that can detect a product.

The authentication processing apparatus according to the present invention uses a PUF circuit designed to output a response, which is information unique to each semiconductor device, for each challenge input based on the physical feature amount of the semiconductor device. , An authentication processing apparatus including an authentication circuit that performs an authentication process as to whether or not a semiconductor device that is an authentication target product is a genuine product based on a response that is unique information. Along with the authentic response to the input, the percentage of the normal response that is not obtained when the challenge input is repeated N (N is an integer of 2 or more) times for the authentic product is stored in the database in advance as an authentic error rate. When authenticating a product subject to authentication, the challenge is repeated N times to generate a response sequence consisting of N responses. For the generated response column, calculate the error rate of the authentication target product based on the genuine product response registered in the database, and the calculated error rate of the authentication target product is the genuine product registered in the database. When it is within the allowable range including the error rate, it is determined that the authentication target product is a genuine product.

The authentication processing method according to the present invention uses a PUF circuit designed to output a response, which is information unique to each semiconductor device, for each challenge input based on the physical feature of the semiconductor device. An authentication processing method in an authentication processing apparatus including an authentication circuit that performs authentication processing as to whether or not a semiconductor device that is an authentication target product is a genuine product based on a response that is unique information, the authentication circuit In addition to the regular product response to the challenge input in the regular product, the ratio that the regular product response is not obtained when the challenge input is repeated N (N is an integer of 2 or more) times for the regular product in advance as the regular product error rate. Repeat the challenge N times when performing registration steps stored in the database and authenticating products for authentication A response string consisting of N responses is generated, and the error rate of the authentication target product is calculated based on the genuine response registered in the database for the generated response sequence. When the rate is within an allowable range including the regular product error rate registered in the database, a verification step of determining that the product to be authenticated is a regular product is provided.

According to the present invention, as statistical information regarding the response of the PUF, by verifying whether or not it is a genuine product using an error rate for repeated processing, the function of the device, the circuit itself, or the PUF Even when a device-specific behavior is copied, an authentication processing apparatus and an authentication processing method that can detect a counterfeit product can be obtained.

It is explanatory drawing which shows the basic idea of the authentication processing apparatus and authentication processing method in Embodiment 1 of this invention. It is a circuit block diagram for performing an iterative process with the authentication processing apparatus in Embodiment 1 of this invention. It is a flowchart regarding a series of repetition processes performed with the authentication processing apparatus provided with the structure of FIG. 2 in Embodiment 1 of this invention. It is explanatory drawing of the verification process in Embodiment 2 of this invention. It is a circuit block diagram for performing the verification process which uses a different challenge with the authentication processing apparatus in Embodiment 2 of this invention. It is a flowchart regarding a series of repetition processes performed with the authentication processing apparatus provided with the structure of FIG. 5 in Embodiment 2 of this invention.

Hereinafter, preferred embodiments of an authentication processing apparatus and an authentication processing method of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
The basic idea of the present invention is to perform authentication using not only the PUF response itself but also statistical information regarding the PUF response. FIG. 1 is an explanatory diagram showing a basic idea of an authentication processing device and an authentication processing method according to Embodiment 1 of the present invention. The product 101 includes a PUF circuit 102 therein, and is designed to return a device-specific response 104 to the challenge 103 by using the PUF circuit 102. Here, “repetition processing” is considered in which a response string is generated by obtaining a response to a same challenge multiple times.

Generally, since the PUF response includes an error, the response from the product 101 does not always have the same value every time. As an example, FIG. 1 shows a case where responses are obtained five times. In this example, when A is given five times as the challenge 103, the value is returned five times as the response 104 (corresponding to the response string), four of which are 1 and 1 is 0. .

In this way, when the results included in the response sequence are different, 1 that occupies the majority in the 5 times corresponds to a correct response when A is given to the product 101 (corresponding to a regular product response, Simply referred to as “response”). Also, since an incorrect response 0 is output once out of 5 times, the error rate related to the genuine product (corresponding to the regular product error rate, but is simply referred to as “error rate” below) is 20%. It can be interpreted as being.

Since the number of repetitions is as small as 5, the error rate has a coarse accuracy of 20%. However, in practice, the accuracy of the regular product error rate can be increased by arbitrarily increasing the number of repetitions. . Here, in order to simplify the description, the number of repetitions is assumed to be 5 thereafter.

By combining the response and error rate obtained in this way, even if the PUF challenge / response is imitated, the authentic product can still be authenticated. First, the response to each challenge and the error rate are registered in the database 105 when the product is manufactured. For example, the data 106 represents information on the genuine product 1, information indicating a challenge-response relationship in which a response 1 is returned for the challenge A and a response 0 is returned for the challenge B; Statistical information that the error rate is 20% is included. Such data is registered in the database 105 in advance.

The error rate can use an individual error rate for each challenge / response or an average error rate for all challenge / responses. In the following, the explanation will be made on the assumption that the average error rate for all challenges and responses is used.

When verifying a product, verify both the response to a challenge and the error rate. For example, when B is given 5 times as a challenge 108 to the product 107, 4 times 0 and 1 time 1 are obtained as a response 109 (corresponding to a response string). This verification result indicates that the response when the challenge B is given to the product 107 is 0 and the error rate is 20%. When the verification result is compared with the genuine product data 106 registered in advance in the database 105, it can be seen that the product 107 is the genuine product 1 because they match.

On the other hand, it is assumed that the counterfeit product 110 imitates the challenge response of the PUF of the regular product 1 and can return a correct response to the given challenge 111. Therefore, if B is given five times as the challenge 111, the correct value 0 is returned five times as the response 112. This verification result indicates that the response 112 (corresponding to the response string) when the imitation product 110 is given B as the challenge 111 is 0 and the error rate is 0%. Since the error rate of 0% based on the verification result does not match the error rate of 20% of the data 106 of the regular product 1, it can be seen that the verified product is a counterfeit product.

FIG. 2 is a circuit configuration diagram for repeatedly executing processing by the authentication processing device according to Embodiment 1 of the present invention. The circuit (authentication circuit) 201 illustrated in FIG. 2 includes a challenge register 203, a control circuit 204, a PUF circuit 205, and a response evaluation circuit 206.

Then, when the challenge 202 is input, the circuit 201 repeatedly generates a PUF response to the challenge 202, and as a result, outputs a response 210 and statistical information 215 regarding the error rate.

The overall operation is controlled by the control circuit 204. In addition, as described with reference to FIG. 1, the response 210 output as a result of repetition is configured so that which of 0/1 is generated, that is, a majority decision result.

The challenge input from 202 is held in the challenge register 203. Then, the value held in the challenge register 203 is input to the PUF circuit 205, so that a PUF response to the challenge is generated. Here, the response generation is repeatedly performed a plurality of times by the control circuit 204. FIG. 2 shows a configuration when the number of repetitions is (2 to the Nth power-1). For example, when N = 3, the number of repetitions is (2 to the power of −1) = 7.

At this time, the response evaluation circuit 206 determines a final response 210 as a result of the iterative processing. For this purpose, the N-bit counter 208 counts the number of 0s and 1s in (2 N-1) iterations. Specifically, first, the N-bit counter 208 is initialized with 0, and each time a response is generated by the PUF circuit 205, the response value is added to the current value of the counter 208 using the adder 207. The result is newly held as the value of the counter 208.

As a result, when the responses of (2 to the power of N-1) are all 0, the value of the N-bit counter 208 is 0, and the value of the counter 208 increases according to the number of times that 1 is included in the response. If so, the value of the counter 208 is (2 to the power of N-1). At this time, the most significant bit of the N-bit counter 208 is a 0/1 majority result in response generation repetition.

Specifically, for example, when N = 3, if the value of the N-bit counter 208 is 100, 101, 110, or 111 (equivalent to 4 to 7 in decimal) in binary notation, there are many 1s. 000, 001, 010, 011 (corresponding to 0 to 3 in decimal) indicates that there are many 0s, but the majority result appears in the most significant bit. Therefore, the response evaluation circuit 206 holds the value of the most significant bit of the N-bit counter 208 in the response register 209 and outputs this as the final response 210.

At this time, the control circuit 204 evaluates the value of the N-bit counter 208 and outputs statistical information 215 regarding the error rate. The error number evaluation circuit 211 in the control circuit 204 is a circuit that obtains and outputs the number of errors from the counter value, and sets the counter value 212 to 00 ... 0 (all 0) or 11 ... 1 (all 1). XOR the data 213 indicated by () and hold it in the error count register 214. The value of the data 213 is 00... 0 when the most significant bit of the counter value is 0, and 11.

The value of the error number register 214 obtained in this way is the number of errors in the response generation of (2 N-1) times. Specifically, for example, if N = 3 and the counter value 212 is 101 in binary notation (corresponding to 5 in decimal), the value of the error count register is the XOR result of 101 and 111 010 (10 This is equivalent to 2 in decimal), and represents that the error was 2 times in 7 response generations.

FIG. 3 is a flowchart relating to a series of repetitive processes executed by the authentication processing apparatus having the configuration of FIG. 2 in the first embodiment of the present invention. Hereinafter, the flow of a series of processes will be described according to each step.

First, the challenge 202 is input to the circuit 201 in step S301. Next, in step S302, a loop for repeating the processes of steps S303 to S305 N times is started.

In S303, a response of the PUF circuit 205 to the challenge 202 input in the previous step S301 is generated. Next, in step S304, the processing is divided according to the response value of the PUF circuit 205 generated in the previous step S303. Specifically, if the value is 0, the process proceeds to step S306, and if the value is 1, the process proceeds to step S305.

When the process proceeds to step S305, the value of the N-bit counter 208 is incremented by one. In step S306, the series of processes in steps S303 to S305 described above are repeated, and the loop is terminated by repeating N times.

Next, in step S307, the response register 209 in the response evaluation circuit 206 obtains a final response 210 from the counter value of the N-bit counter 208 obtained in a loop of N times.

In step S308, the error count evaluation circuit 211 in the control circuit 204 calculates the error count 215 from the counter value of the N-bit counter 208 determined in a loop of N times.

Then, the response evaluation circuit 206 outputs the response 210 obtained in the previous step S307 from the circuit 201 in step S309. Further, in step S310, the control circuit 204 outputs the number of errors 215 obtained in the previous step S308 from the circuit 201.

Then, in step S311, the subsequent processing is performed by dividing into registration processing or verification processing. Specifically, when the processing result is registered in the database 105, the process proceeds to step S312. When the verification based on the processing result is performed, the process proceeds to S313.

When the process proceeds to step S312, the response 210 output from the circuit 201 in the previous step S309 and the error count 215 output from the circuit 201 in the previous step S310 are registered in the database 105, and the series of processes ends.

On the other hand, when the process proceeds to step S313, the response 210 output from the circuit 201 in the previous S309, the error count 215 output from the circuit 201 in the previous step S310, and the regularity already registered in the database 105 are obtained. If at least one of the response 210 or the number of errors 215 does not match, it is determined that the product is a counterfeit product, and the series of processes ends.

As described above, according to the first embodiment, even when the PUF challenge / response is imitated, the statistical information (corresponding to the number of errors or error rate for repeated processing) of the PUF response is the genuine data. By verifying whether they match, an authentication method that can still detect a counterfeit and a circuit therefor are realized.

Regarding the error rate, in addition to the exact match, the error rate calculated for the product to be certified is within the allowable range including the error rate of the regular product data, so it is a genuine product. It can be judged.

Embodiment 2. FIG.
In the first embodiment, the case has been described in which a response string is generated by repeatedly using the same challenge and the verification process is performed. On the other hand, in the second embodiment, a case where a response sequence is generated using different challenges and a verification process is performed will be described.

FIG. 4 is an explanatory diagram of the verification process according to the second embodiment of the present invention. Specifically, the verification process of the second embodiment using a different challenge is shown in contrast to the verification process of the first embodiment that repeatedly uses the same challenge. Note that database registration at the time of manufacturing in the second embodiment is performed in the same manner as in the first embodiment.

The verification process 401 shown in the upper part of FIG. 4 represents the verification process using the same challenge as in the first embodiment. The same challenge 403 is input to the genuine product 402 that is the verification target product, and a response 404 (corresponding to a response string) is output. The authenticator collates the data 405 consisting of repeated responses of the genuine product acquired from the database 105 with the actual response 404 for the genuine product 402 to confirm that four of the five responses are correct, and that The result error rate can be confirmed to be 20%, and the verification target product can be confirmed to be the regular product 402.

However, in this method, since a response to the same challenge is output a plurality of times, an error rate can be estimated if the response 404 is wiretapped. That is, as a result of inputting the same challenge B five times, the value 0 is output four times and the value 1 is output once. Therefore, it can be estimated that the value 1 is incorrect and the error rate is 20%. Therefore, there is a possibility that a counterfeit product that also imitates the error rate is allowed, for example, an error is generated stochastically using pseudorandom number generation by software.

On the other hand, a verification process 406 shown in the lower part of FIG. 4 represents a verification process using different challenges according to the second embodiment. A different challenge 408 is input to the regular product 407 that is the verification target product, and a response 409 (corresponding to a response string) is output. The authenticator collates the data 410, which is obtained from the database 105 and includes the genuine response 409 for each challenge, and the actual response 409 for the genuine product 407, so that four responses out of five are correct. As a result, it can be confirmed that the error rate is 20%, and the verification target product can be confirmed to be a regular product 407.

In the verification method according to the second embodiment, responses to different challenges A to E are output only once. For this reason, just by eavesdropping on the response 409, it is not possible to determine which response to which challenge is correct and to which challenge the response is incorrect, and the error rate cannot be estimated. Therefore, imitation of the error rate can be prevented.

FIG. 5 is a circuit configuration diagram for executing verification processing 406 using different challenges in the authentication processing apparatus according to Embodiment 2 of the present invention. The circuit (authentication circuit) 501 illustrated in FIG. 5 includes a control circuit 504, a selector 505, a challenge register 506, an adder 507, a PUF circuit 508, and a response register 509.

Then, when the challenge 502 is input, the circuit 501 generates an increasing sequence of different challenges starting from the value of the challenge 502, and sequentially outputs responses 503 for the different challenges.

The entire circuit is controlled by the control circuit 504. The circuit is roughly divided into a challenge register 506, a PUF circuit 508, and a response register 509, and is a circuit that generates a response of the PUF circuit 508 with respect to a given challenge 502. However, by providing a selector 505 in front of the challenge register 506, the value of the challenge register 506 can be changed.

With this configuration, when a challenge 502 is input, this challenge is selected by the selector 505, and a response corresponding to this challenge is generated by the PUF circuit 508 and held in the response register 509. Thereafter, a value obtained by adding 1 to the challenge is selected by the selector 505 by the adder 507, and a response corresponding to the value is generated by the PUF circuit 508 and held in the response register 509.

Hereinafter, similarly, 1 is added to the value of the challenge one after another, and a response corresponding to the value is generated and held in the response register. In this way, responses of the PUF circuit 508 are generated one after another with respect to an increasing sequence of challenges starting from the value of the challenge 502 input first, and responses 503 corresponding to the different challenges are output one after another. Go.

In the circuit 501, the adder 507 increments the challenge value by 1. However, the method for changing the challenge is not limited to this method. For example, a configuration in which a value is changed using a linear feedback shift register may be used.

Further, for simplicity of description, the circuit 501 is shown as a configuration that does not have a circuit for obtaining an error rate therein, but the error rate is similar to the circuit 201 of FIG. 2 in the first embodiment. An error number evaluation circuit 211 for obtaining the above may be included.

FIG. 6 is a flowchart relating to a series of repetitive processes executed by the authentication processing apparatus having the configuration of FIG. 5 in the second embodiment of the present invention. Hereinafter, the flow of a series of processes will be described according to each step.

First, in S601, the registration process or the verification process is divided into subsequent processes. Specifically, if the processing result is registered in the database 105, the process proceeds to step S602, and if verification based on the processing result is performed, the process proceeds to S609.

When the process proceeds to step S602 for registration in the database, a loop that repeats the subsequent steps S603 to S605 M times is started.

In step S <b> 603, the challenge 502 is input to the circuit 501. Next, in step S604, a response of the PUF circuit 508 to the challenge 502 input in the previous step S603 is generated. Next, in step S605, the response generated in step S604 is output. In step S606, the series of processes in steps S603 to S605 described above is repeated M times, and the loop is terminated.

Next, in step S607, a final response and an error rate are calculated from the M PUF responses for the same challenge obtained in a loop of M times. In step S608, the response and error rate obtained in the previous step S607 are registered in the database 105, and the series of processes ends.

Note that the response obtained by the series of steps S602 to S609 is for one challenge, and for different challenges, the database is constructed by individually performing these series of processes. It becomes. Of course, the error rate can be calculated as the average of the error rates obtained for each of the different challenges.

On the other hand, when the processing proceeds to S609 in order to perform verification based on the processing result, the challenge 502 is input to the circuit 501. Next, in step S610, a loop is started in which the processes in subsequent steps S611 to S613 are repeated N times.

In step S611, a response of the PUF circuit 508 to the challenge 502 input in the previous step S609 is generated. Next, in step S612, the response generated in step S611 is output. In step S613, the adder 507 increments the challenge value by one. In step S614, the series of processes in steps S611 to S613 described above is repeated N times, and the loop is terminated.

Next, in step S615, the response sequence of the PUF circuit 508 for N different challenges obtained in a loop of N iterations is compared with the response sequence based on the value of the genuine product already registered in the database 105. However, it will be judged whether the product is genuine or counterfeit.

In addition, in the case where an error occurs for a challenge in the comparison of the response sequence obtained by verification for a different challenge and the response sequence of a genuine product acquired in advance, the error rate is also taken into consideration to determine whether the product is a genuine product. It is possible to identify whether or not.

As described above, according to the second embodiment, instead of repeatedly using the same challenge, it is possible to prevent imitation of an error rate by determining whether the product is a genuine product based on a response result to a different challenge. An authentication method capable of detecting a counterfeit product more reliably and a circuit therefor are realized.

Claims

The response, which is the unique information, using a PUF circuit designed to output a response, which is information unique to each semiconductor device, for each challenge input based on a physical feature quantity of the semiconductor device An authentication processing apparatus including an authentication circuit for performing an authentication process as to whether or not the semiconductor device as a product to be authenticated is a genuine product based on
The authentication circuit authenticates the ratio that the authentic response cannot be obtained when the challenge input is repeated N times (N is an integer of 2 or more) for the authentic product, along with the authentic response to the challenge input in the authentic product. The product error rate is stored in the database in advance, and when authenticating the product to be authenticated, a challenge is repeated N times to generate a response string composed of N responses, and the generated response string The error rate of the product to be authenticated is calculated based on the genuine product response registered in the database, and the calculated error rate of the product to be authenticated is the error rate of the genuine product registered in the database. An authentication processing device that determines that the product to be authenticated is a genuine product if it is within an allowable range.
The authentication processing device according to claim 1,
The authentication circuit generates the response string by repeating the same challenge input N times when authenticating the product to be authenticated, and performs the authentication process based on the error rate for the same challenge input Authentication processing device.
The authentication processing device according to claim 2,
The authentication circuit includes:
A response evaluation circuit that identifies the genuine response by a majority result in a plurality of responses to the same challenge input in the genuine product,
An authentication processing device comprising: an error number evaluation circuit that specifies a ratio of the regular product response obtained in the plurality of responses as the regular product error rate when the regular product response is identified by the majority result. .
The authentication processing device according to claim 1,
The authentication circuit stores the genuine product response in the database in advance for each of a plurality of different N challenge inputs, and M (( When M is an integer greater than or equal to 2 times, the ratio that the genuine product response is not obtained in a total of M × N authentication processes is stored in the database in advance as a regular product error rate, and the product to be certified When the authentication is performed, the response sequence is generated from responses to N different challenge inputs, and the generated response sequence is registered in the database corresponding to each of the N different challenges. The error rate of the product to be authenticated is calculated based on the genuine product response, and the calculated authentication Error rate of the target products, if within the allowable range including the genuine error rate registered in the database, the authentication processing unit, wherein the authentication object article is determined to be genuine.
The authentication processing device according to claim 4,
The authentication circuit includes:
The challenge input as a reference in the genuine product is acquired, and the challenge input as the reference is incremented by 1 using an adder to generate the N different challenge inputs, and the N challenge inputs An authentication processing apparatus comprising: a response evaluation circuit that individually identifies the genuine product response for each of the N challenge inputs based on a majority decision result of a plurality of responses to each of the inputs.
The response, which is the unique information, using a PUF circuit designed to output a response, which is information unique to each semiconductor device, for each challenge input based on a physical feature quantity of the semiconductor device An authentication processing method in an authentication processing apparatus including an authentication circuit that performs an authentication process as to whether or not the semiconductor device that is an authentication target product is a genuine product based on:
In the authentication circuit,
Along with the regular product response to the challenge input in the regular product, the percentage that the regular product response is not obtained when the challenge input is repeated N (N is an integer of 2 or more) times for the regular product in advance as the regular product error rate. A registration step stored in the database;
When authenticating the product to be authenticated, the challenge is repeated N times to generate a response string composed of N responses, and the generated response string is added to the genuine product response registered in the database. And calculating the error rate of the product to be authenticated based on the error rate of the product to be authenticated is within an allowable range including the genuine product error rate registered in the database. An authentication processing method comprising: a verification step of determining that the product is genuine.