WO2013042755A1 - Organic semiconductor element - Google Patents

Abstract

An organic semiconductor device of the present invention is a bottom-gate organic semiconductor element wherein a gate layer is formed on a substrate and an organic semiconductor layer, in which a source/drain region and a channel region are formed, is arranged on an insulating layer that is formed on the gate layer. The insulating film is formed on the lateral surface and the upper surface of the gate layer, and a channel region is formed on at least the lateral surface of the gate layer.

Description

Organic semiconductor device

The present invention relates to an organic semiconductor element, and more particularly to a structure of an organic semiconductor element formed using a printing technique.

In recent years, wireless sensor systems are rapidly spreading, and a huge number of sensor nodes are required to obtain highly accurate sensor information. Therefore, low-cost and easy manufacture is required for the sensor terminal, and a sensor terminal using an organic semiconductor that satisfies this requirement is required. Furthermore, the manufacture of silicon semiconductor devices and compound semiconductor devices using vapor deposition processes and vacuum processes requires the introduction of equipment and initial investment, and it is difficult to reduce costs. On the other hand, in recent years, a method for producing an organic semiconductor element using a low-cost printing process has been widely researched and developed.
Here, FIGS. 9 and 10 show the structure of a basic organic transistor as a background art, and FIG. 8 shows the structure of a general silicon FET for comparison.
As shown in FIG. 8, in a general silicon FET, the silicon substrate 30 also serves as a semiconductor layer in which source / drain regions 40 and 41 and a channel region are formed.
On the other hand, in this organic transistor, as shown in FIG. 10, the organic semiconductor layer 130 is a separate layer from the substrate 100. Further, in order to avoid deterioration of the characteristics of the organic semiconductor due to the thermal process, the organic semiconductor layer 130 is configured to be the uppermost part.
Accordingly, as shown in FIG. 10, the cross-sectional structure of a general organic transistor is as follows: substrate 100, gate layer 110, insulating layer 120, source / drain (hereinafter referred to as S / D) electrode 140, and organic semiconductor layer 130 from the bottom. accumulate. However, the order of the S / D electrode 140 and the organic semiconductor layer 130 may be switched.
This structure is hereinafter referred to as a bottom gate type. Further, in the general silicon FET shown in FIG. 8, the gate layer 10 and the S / D layers 40 and 41 do not overlap in layout, but in the bottom gate type organic transistor shown in FIG. / D layers 140 and 141 are configured to overlap. Therefore, basically, as shown in FIG. 9, the channel region 150 of the bottom-gate organic transistor is a region between S / D in the organic semiconductor layer 130.
In such a general organic semiconductor element, an organic material that is considered promising as a semiconductor often has a mobility several orders of magnitude smaller than that of silicon, and even an organic semiconductor called P3HT having a relatively high mobility is 0. It is about 0.01 cm ² / v · s (silicon is about 100). Therefore, with a channel aspect ratio (channel width / channel length) comparable to that of a silicon semiconductor device, only a drive current of about 1/1000 can be obtained, and there is a problem that the operating current required for the sensor node circuit is insufficient. Yes.
In order to solve such a problem, for example, in FIGS. 6 and 7 of Patent Document 1 (Japanese Patent Application Laid-Open No. 2006-091089), an etching process technique or the like is used to connect a semiconductor layer and a gate oxide film in parallel to the substrate. However, the structure of a transistor in which a second gate layer is stacked has been proposed. However, the organic semiconductor element disclosed in Patent Document 1 has a problem. That is, since the number of layers to be stacked increases in this structure, it is difficult to miniaturize the printing process technology in which the misalignment of each layer is large. In addition, contact holes for short-circuiting the upper and lower gate layers are necessary, but it is difficult to put it into practical use in a printing process technique that basically does not have an interlayer contact creation process.
The present invention has been proposed to solve such problems, and an object thereof is to provide a device structure that increases the drive current of an organic semiconductor device that can be produced by a printing process.

The organic semiconductor device of the present invention is a bottom gate type organic semiconductor element having an organic semiconductor layer in which a gate layer is provided on a substrate and a source / drain region and a channel region are formed via an insulating layer provided thereon. The insulating film is formed on a side surface and an upper surface of the gate layer, and a channel region is formed at least on the side surface of the gate layer.
Furthermore, the organic semiconductor device of the present invention is a bottom gate type organic semiconductor having an organic semiconductor layer in which a gate layer is provided on a substrate and a source / drain region and a channel region are formed via an insulating layer provided thereon. An element, wherein a plurality of the gate layers are formed in parallel in a direction in which the source / drain regions extend in the organic semiconductor layer.
Furthermore, the organic semiconductor device of the present invention is a bottom gate type organic semiconductor having a gate layer on a substrate and an organic semiconductor layer in which a source / drain region and a channel region are formed via an insulating layer provided thereon. An element, wherein a plurality of first gate layers and a plurality of second gate layers to which signals different from the first gate layer are applied are formed in the organic semiconductor layer, and the source / drain regions are It is characterized by being alternately formed in parallel in the extending direction.

It is a top view of the organic transistor for demonstrating 1st embodiment of this invention. It is the top view to which the gate isolation | separation part vicinity of the organic transistor structure for demonstrating 1st embodiment of this invention was expanded. It is sectional drawing of the S / D direction which expanded the gate isolation | separation part vicinity of the organic transistor structure for describing 1st embodiment of this invention. It is sectional drawing of the channel direction of the organic transistor structure for demonstrating 1st embodiment of this invention. It is a top view of the organic transistor structure of 4 gate isolation | separation structure for demonstrating 2nd embodiment of this invention. It is a figure which shows the example of application to the mixer part of the radio | wireless communication for demonstrating 3rd embodiment of this invention. It is a top view which shows the Example utilized as a back gate for demonstrating 3rd embodiment of this invention. It is sectional drawing of FIG. It is a top view which shows a general silicon FET structure. It is sectional drawing which shows a general silicon FET structure. It is a top view which shows a general silicon FET structure. It is a top view which shows a general organic transistor structure. It is sectional drawing in the dotted-line part of FIG.

(First embodiment)
The organic semiconductor element as the first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, a gate layer 110 formed by printing or applying nano silver ink or the like on a substrate 100 is divided into a plurality of portions in the direction of the S / D formation region in the organic semiconductor layer 130 (2 in FIG. 1). (Shows the split configuration). That is, a plurality of gate layers that are electrically connected outside the organic semiconductor layer 130 are formed in parallel in the organic semiconductor layer 130 in the direction in which the S / D region extends.
As shown in FIG. 2, polyimide formed by coating, printing, or an insulating material having a high dielectric constant is formed on the gate layer 110. Accordingly, the insulating films 120 and 121 are formed on the side surfaces and the upper surface of the gate layers 110 and 111, respectively. In the case of this embodiment, the thickness B of the insulating layer formed on the side surface of the gate layer is thinner than the thickness A of the insulating layer on the upper surface of the gate layer.
Therefore, on the plane, the S / D region and the divided gate layer 110 vertically intersect in the organic semiconductor region 130.
In the conventional organic transistor structure, the channel of the transistor is generated on the gate layer 110 via the insulating film 120 as shown in FIG. On the other hand, in the structure of the present invention, not only the channel region is formed in the region on the gate layer 110 (111) via the insulating film 120 (121) shown in FIG. Thus, a channel region is also formed on the side wall of the gate layer 110 (111) through the insulating film 120 (121). As a result, the channel width can be increased as compared with the prior art.
Another effect is that the electric field between the gate and the organic semiconductor is improved from the upper part of the gate layer 110 and the amount of current is improved by forming the side wall portion of the insulating layer 120 (121) thin. Can be expected.
(Second embodiment)
Generally, as shown in FIG. 8C, a silicon FET has a structure called a finger type. That is, in order to reduce the S / D capacitance, a transistor configuration in which the gate layer 10 is divided in the S / D direction is common. The present invention can also be applied to the finger type.
In the bottom gate type organic transistor, as shown in FIG. 4, a finger type can be formed by dividing the S / D electrodes 140 and 141 into a plurality in the channel length direction. In this embodiment, each of the S / D electrodes 140 and 141 is divided into two.
In addition to this, in this embodiment, the gate layer 110 is further divided in the S / D direction as in the first embodiment. In this embodiment, it is divided into four.
In other words, in order to obtain the maximum driving current, a structure in which the division of the gate layer in the S / D direction and the division of the S / D layer in the channel direction is combined in the region of the organic semiconductor layer 130. A more effective current amount can be obtained.
The number of gate layers and S / D electrodes to be divided may be two or more.
(Third embodiment)
A third embodiment will be described with reference to FIGS. 5, 6, and 7. FIG. This embodiment shows a case where it is used as a mixer circuit of a wireless receiving unit.
As shown in FIG. 5, this is an example in which a transistor constituting a mixer circuit is applied to the present invention.
An RF reception signal is input to the drain terminal 200 and a local signal is input to the back gate 230. At this time, while the switch is turned on by the clock input to the gate terminal 210, the mixer operation can be performed using the local signal, and the baseband signal can be extracted from the terminal 220.
FIG. 6 shows a plan view of a structure in which a local signal is applied to the back gate. The gate layer 110 divided into two and the back gate layer divided into two are arranged alternately in the S / D direction. In this embodiment, each of the S / D electrodes 140 and 141 is divided into two.
In the cross-sectional structure of the channel portion, an insulating layer 121 is formed on the top and side surfaces of the back gate layer 11 as shown in FIG. Accordingly, the back gate layer 11 is formed so that the side surface thereof faces the side surface of the gate layer 110 constituting the channel region.
Since a different voltage can be input to the back gate layer 111 with respect to a voltage input to the gate layer 110, an electric field across the side wall channel portion 151 from the gate layer can be controlled by a voltage applied to the back gate layer 111. It becomes.
As a result, it is possible to control the side wall portion, which is a part of the channel, with four terminals with respect to the bottom gate type transistor that has been conventionally only capable of three-terminal control (gate / drain / source).
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2011-206947 for which it applied on September 22, 2011, and takes in those the indications of all here.

According to the present invention, since a double gate structure can be formed without using multiple layers, the drive current can be increased without increasing the mask cost and the ink cost. In addition, since the two gate electrodes can be short-circuited without using the contact hole formation process, it is possible to form a device in a printing process in which contact hole formation is difficult.

110, 111 Gate layer 120, 121 Insulating layer 130 Organic semiconductor layer 140, 141 S / D electrode

Claims (9)

1. A bottom gate type organic semiconductor device having an organic semiconductor layer in which a gate layer is provided on a substrate and a source / drain region and a channel region are formed through an insulating layer provided thereon, A bottom gate type organic semiconductor device, wherein the insulating film is formed on a side surface and an upper surface, and a channel region is formed at least on a side surface of the gate layer.
2. 2. The bottom gate type organic semiconductor device according to claim 1, wherein the insulating film formed on the side surface is thinner than the insulating film formed on the upper surface of the gate layer.
3. A bottom gate type organic semiconductor device having an organic semiconductor layer in which a gate layer is provided on a substrate and a source / drain region and a channel region are formed through an insulating layer provided thereon, and a plurality of the gates A layer is formed in parallel in the direction in which the source / drain regions extend in the organic semiconductor layer.
4. The bottom gate type organic semiconductor device according to claim 3, wherein the insulating film is formed on a side surface and an upper surface of the gate layer, and a channel region is formed at least on the side surface of the gate layer.
5. 5. The bottom gate type organic semiconductor device according to claim 3, wherein a plurality of the source / drain regions are formed in parallel in the channel region direction in the organic semiconductor layer.
6. 5. The bottom gate type organic semiconductor device according to claim 4, wherein the thickness of the insulating film formed on the side surface is smaller than the thickness of the insulating film formed on the upper surface of the gate layer.
7. A bottom gate type organic semiconductor device having an organic semiconductor layer in which a gate layer is provided on a substrate and a source / drain region and a channel region are formed through an insulating layer provided on the substrate. And a plurality of second gate layers to which signals different from the first gate layer are applied are alternately formed in parallel in the organic semiconductor layer in a direction in which the source / drain regions extend. A bottom-gate organic semiconductor element characterized by the above.
8. The bottom gate type organic semiconductor device according to claim 7, wherein the insulating film is formed on a side surface and an upper surface of the first gate layer, and a channel region is formed at least on the side surface of the gate layer.
9. 9. The bottom gate type organic semiconductor device according to claim 8, wherein a thickness of the insulating film formed on the side surface is thinner than a thickness of the insulating film formed on the upper surface of the first gate layer. .

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